1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/cpufreq.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/opp.h> 16 #include <linux/platform_device.h> 17 #include <linux/regulator/consumer.h> 18 19 #define PU_SOC_VOLTAGE_NORMAL 1250000 20 #define PU_SOC_VOLTAGE_HIGH 1275000 21 #define FREQ_1P2_GHZ 1200000000 22 23 static struct regulator *arm_reg; 24 static struct regulator *pu_reg; 25 static struct regulator *soc_reg; 26 27 static struct clk *arm_clk; 28 static struct clk *pll1_sys_clk; 29 static struct clk *pll1_sw_clk; 30 static struct clk *step_clk; 31 static struct clk *pll2_pfd2_396m_clk; 32 33 static struct device *cpu_dev; 34 static struct cpufreq_frequency_table *freq_table; 35 static unsigned int transition_latency; 36 37 static int imx6q_verify_speed(struct cpufreq_policy *policy) 38 { 39 return cpufreq_frequency_table_verify(policy, freq_table); 40 } 41 42 static unsigned int imx6q_get_speed(unsigned int cpu) 43 { 44 return clk_get_rate(arm_clk) / 1000; 45 } 46 47 static int imx6q_set_target(struct cpufreq_policy *policy, 48 unsigned int target_freq, unsigned int relation) 49 { 50 struct cpufreq_freqs freqs; 51 struct opp *opp; 52 unsigned long freq_hz, volt, volt_old; 53 unsigned int index; 54 int ret; 55 56 ret = cpufreq_frequency_table_target(policy, freq_table, target_freq, 57 relation, &index); 58 if (ret) { 59 dev_err(cpu_dev, "failed to match target frequency %d: %d\n", 60 target_freq, ret); 61 return ret; 62 } 63 64 freqs.new = freq_table[index].frequency; 65 freq_hz = freqs.new * 1000; 66 freqs.old = clk_get_rate(arm_clk) / 1000; 67 68 if (freqs.old == freqs.new) 69 return 0; 70 71 rcu_read_lock(); 72 opp = opp_find_freq_ceil(cpu_dev, &freq_hz); 73 if (IS_ERR(opp)) { 74 rcu_read_unlock(); 75 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); 76 return PTR_ERR(opp); 77 } 78 79 volt = opp_get_voltage(opp); 80 rcu_read_unlock(); 81 volt_old = regulator_get_voltage(arm_reg); 82 83 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", 84 freqs.old / 1000, volt_old / 1000, 85 freqs.new / 1000, volt / 1000); 86 87 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); 88 89 /* scaling up? scale voltage before frequency */ 90 if (freqs.new > freqs.old) { 91 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 92 if (ret) { 93 dev_err(cpu_dev, 94 "failed to scale vddarm up: %d\n", ret); 95 freqs.new = freqs.old; 96 goto post_notify; 97 } 98 99 /* 100 * Need to increase vddpu and vddsoc for safety 101 * if we are about to run at 1.2 GHz. 102 */ 103 if (freqs.new == FREQ_1P2_GHZ / 1000) { 104 regulator_set_voltage_tol(pu_reg, 105 PU_SOC_VOLTAGE_HIGH, 0); 106 regulator_set_voltage_tol(soc_reg, 107 PU_SOC_VOLTAGE_HIGH, 0); 108 } 109 } 110 111 /* 112 * The setpoints are selected per PLL/PDF frequencies, so we need to 113 * reprogram PLL for frequency scaling. The procedure of reprogramming 114 * PLL1 is as below. 115 * 116 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it 117 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 118 * - Disable pll2_pfd2_396m_clk 119 */ 120 clk_set_parent(step_clk, pll2_pfd2_396m_clk); 121 clk_set_parent(pll1_sw_clk, step_clk); 122 if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) { 123 clk_set_rate(pll1_sys_clk, freqs.new * 1000); 124 clk_set_parent(pll1_sw_clk, pll1_sys_clk); 125 } 126 127 /* Ensure the arm clock divider is what we expect */ 128 ret = clk_set_rate(arm_clk, freqs.new * 1000); 129 if (ret) { 130 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); 131 regulator_set_voltage_tol(arm_reg, volt_old, 0); 132 freqs.new = freqs.old; 133 goto post_notify; 134 } 135 136 /* scaling down? scale voltage after frequency */ 137 if (freqs.new < freqs.old) { 138 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 139 if (ret) { 140 dev_warn(cpu_dev, 141 "failed to scale vddarm down: %d\n", ret); 142 ret = 0; 143 } 144 145 if (freqs.old == FREQ_1P2_GHZ / 1000) { 146 regulator_set_voltage_tol(pu_reg, 147 PU_SOC_VOLTAGE_NORMAL, 0); 148 regulator_set_voltage_tol(soc_reg, 149 PU_SOC_VOLTAGE_NORMAL, 0); 150 } 151 } 152 153 post_notify: 154 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); 155 156 return ret; 157 } 158 159 static int imx6q_cpufreq_init(struct cpufreq_policy *policy) 160 { 161 int ret; 162 163 ret = cpufreq_frequency_table_cpuinfo(policy, freq_table); 164 if (ret) { 165 dev_err(cpu_dev, "invalid frequency table: %d\n", ret); 166 return ret; 167 } 168 169 policy->cpuinfo.transition_latency = transition_latency; 170 policy->cur = clk_get_rate(arm_clk) / 1000; 171 cpumask_setall(policy->cpus); 172 cpufreq_frequency_table_get_attr(freq_table, policy->cpu); 173 174 return 0; 175 } 176 177 static int imx6q_cpufreq_exit(struct cpufreq_policy *policy) 178 { 179 cpufreq_frequency_table_put_attr(policy->cpu); 180 return 0; 181 } 182 183 static struct freq_attr *imx6q_cpufreq_attr[] = { 184 &cpufreq_freq_attr_scaling_available_freqs, 185 NULL, 186 }; 187 188 static struct cpufreq_driver imx6q_cpufreq_driver = { 189 .verify = imx6q_verify_speed, 190 .target = imx6q_set_target, 191 .get = imx6q_get_speed, 192 .init = imx6q_cpufreq_init, 193 .exit = imx6q_cpufreq_exit, 194 .name = "imx6q-cpufreq", 195 .attr = imx6q_cpufreq_attr, 196 }; 197 198 static int imx6q_cpufreq_probe(struct platform_device *pdev) 199 { 200 struct device_node *np; 201 struct opp *opp; 202 unsigned long min_volt, max_volt; 203 int num, ret; 204 205 cpu_dev = &pdev->dev; 206 207 np = of_node_get(cpu_dev->of_node); 208 if (!np) { 209 dev_err(cpu_dev, "failed to find cpu0 node\n"); 210 return -ENOENT; 211 } 212 213 arm_clk = devm_clk_get(cpu_dev, "arm"); 214 pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys"); 215 pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw"); 216 step_clk = devm_clk_get(cpu_dev, "step"); 217 pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m"); 218 if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) || 219 IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) { 220 dev_err(cpu_dev, "failed to get clocks\n"); 221 ret = -ENOENT; 222 goto put_node; 223 } 224 225 arm_reg = devm_regulator_get(cpu_dev, "arm"); 226 pu_reg = devm_regulator_get(cpu_dev, "pu"); 227 soc_reg = devm_regulator_get(cpu_dev, "soc"); 228 if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) { 229 dev_err(cpu_dev, "failed to get regulators\n"); 230 ret = -ENOENT; 231 goto put_node; 232 } 233 234 /* We expect an OPP table supplied by platform */ 235 num = opp_get_opp_count(cpu_dev); 236 if (num < 0) { 237 ret = num; 238 dev_err(cpu_dev, "no OPP table is found: %d\n", ret); 239 goto put_node; 240 } 241 242 ret = opp_init_cpufreq_table(cpu_dev, &freq_table); 243 if (ret) { 244 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); 245 goto put_node; 246 } 247 248 if (of_property_read_u32(np, "clock-latency", &transition_latency)) 249 transition_latency = CPUFREQ_ETERNAL; 250 251 /* 252 * OPP is maintained in order of increasing frequency, and 253 * freq_table initialised from OPP is therefore sorted in the 254 * same order. 255 */ 256 rcu_read_lock(); 257 opp = opp_find_freq_exact(cpu_dev, 258 freq_table[0].frequency * 1000, true); 259 min_volt = opp_get_voltage(opp); 260 opp = opp_find_freq_exact(cpu_dev, 261 freq_table[--num].frequency * 1000, true); 262 max_volt = opp_get_voltage(opp); 263 rcu_read_unlock(); 264 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); 265 if (ret > 0) 266 transition_latency += ret * 1000; 267 268 /* Count vddpu and vddsoc latency in for 1.2 GHz support */ 269 if (freq_table[num].frequency == FREQ_1P2_GHZ / 1000) { 270 ret = regulator_set_voltage_time(pu_reg, PU_SOC_VOLTAGE_NORMAL, 271 PU_SOC_VOLTAGE_HIGH); 272 if (ret > 0) 273 transition_latency += ret * 1000; 274 ret = regulator_set_voltage_time(soc_reg, PU_SOC_VOLTAGE_NORMAL, 275 PU_SOC_VOLTAGE_HIGH); 276 if (ret > 0) 277 transition_latency += ret * 1000; 278 } 279 280 ret = cpufreq_register_driver(&imx6q_cpufreq_driver); 281 if (ret) { 282 dev_err(cpu_dev, "failed register driver: %d\n", ret); 283 goto free_freq_table; 284 } 285 286 of_node_put(np); 287 return 0; 288 289 free_freq_table: 290 opp_free_cpufreq_table(cpu_dev, &freq_table); 291 put_node: 292 of_node_put(np); 293 return ret; 294 } 295 296 static int imx6q_cpufreq_remove(struct platform_device *pdev) 297 { 298 cpufreq_unregister_driver(&imx6q_cpufreq_driver); 299 opp_free_cpufreq_table(cpu_dev, &freq_table); 300 301 return 0; 302 } 303 304 static struct platform_driver imx6q_cpufreq_platdrv = { 305 .driver = { 306 .name = "imx6q-cpufreq", 307 .owner = THIS_MODULE, 308 }, 309 .probe = imx6q_cpufreq_probe, 310 .remove = imx6q_cpufreq_remove, 311 }; 312 module_platform_driver(imx6q_cpufreq_platdrv); 313 314 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 315 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver"); 316 MODULE_LICENSE("GPL"); 317