1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Freescale Semiconductor, Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/cpu.h> 8 #include <linux/cpufreq.h> 9 #include <linux/err.h> 10 #include <linux/module.h> 11 #include <linux/nvmem-consumer.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/pm_opp.h> 15 #include <linux/platform_device.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/regmap.h> 19 20 #define PU_SOC_VOLTAGE_NORMAL 1250000 21 #define PU_SOC_VOLTAGE_HIGH 1275000 22 #define FREQ_1P2_GHZ 1200000000 23 24 static struct regulator *arm_reg; 25 static struct regulator *pu_reg; 26 static struct regulator *soc_reg; 27 28 enum IMX6_CPUFREQ_CLKS { 29 ARM, 30 PLL1_SYS, 31 STEP, 32 PLL1_SW, 33 PLL2_PFD2_396M, 34 /* MX6UL requires two more clks */ 35 PLL2_BUS, 36 SECONDARY_SEL, 37 }; 38 #define IMX6Q_CPUFREQ_CLK_NUM 5 39 #define IMX6UL_CPUFREQ_CLK_NUM 7 40 41 static int num_clks; 42 static struct clk_bulk_data clks[] = { 43 { .id = "arm" }, 44 { .id = "pll1_sys" }, 45 { .id = "step" }, 46 { .id = "pll1_sw" }, 47 { .id = "pll2_pfd2_396m" }, 48 { .id = "pll2_bus" }, 49 { .id = "secondary_sel" }, 50 }; 51 52 static struct device *cpu_dev; 53 static struct cpufreq_frequency_table *freq_table; 54 static unsigned int max_freq; 55 static unsigned int transition_latency; 56 57 static u32 *imx6_soc_volt; 58 59 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) 60 { 61 struct dev_pm_opp *opp; 62 unsigned long freq_hz, volt, volt_old; 63 unsigned int old_freq, new_freq; 64 bool pll1_sys_temp_enabled = false; 65 int ret; 66 67 new_freq = freq_table[index].frequency; 68 freq_hz = new_freq * 1000; 69 old_freq = clk_get_rate(clks[ARM].clk) / 1000; 70 71 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); 72 if (IS_ERR(opp)) { 73 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); 74 return PTR_ERR(opp); 75 } 76 77 volt = dev_pm_opp_get_voltage(opp); 78 dev_pm_opp_put(opp); 79 80 volt_old = regulator_get_voltage(arm_reg); 81 82 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", 83 old_freq / 1000, volt_old / 1000, 84 new_freq / 1000, volt / 1000); 85 86 /* scaling up? scale voltage before frequency */ 87 if (new_freq > old_freq) { 88 if (!IS_ERR(pu_reg)) { 89 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 90 if (ret) { 91 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); 92 return ret; 93 } 94 } 95 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 96 if (ret) { 97 dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret); 98 return ret; 99 } 100 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 101 if (ret) { 102 dev_err(cpu_dev, 103 "failed to scale vddarm up: %d\n", ret); 104 return ret; 105 } 106 } 107 108 /* 109 * The setpoints are selected per PLL/PDF frequencies, so we need to 110 * reprogram PLL for frequency scaling. The procedure of reprogramming 111 * PLL1 is as below. 112 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change 113 * flow is slightly different from other i.MX6 OSC. 114 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below: 115 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it 116 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 117 * - Disable pll2_pfd2_396m_clk 118 */ 119 if (of_machine_is_compatible("fsl,imx6ul") || 120 of_machine_is_compatible("fsl,imx6ull")) { 121 /* 122 * When changing pll1_sw_clk's parent to pll1_sys_clk, 123 * CPU may run at higher than 528MHz, this will lead to 124 * the system unstable if the voltage is lower than the 125 * voltage of 528MHz, so lower the CPU frequency to one 126 * half before changing CPU frequency. 127 */ 128 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000); 129 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 130 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) 131 clk_set_parent(clks[SECONDARY_SEL].clk, 132 clks[PLL2_BUS].clk); 133 else 134 clk_set_parent(clks[SECONDARY_SEL].clk, 135 clks[PLL2_PFD2_396M].clk); 136 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk); 137 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); 138 if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) { 139 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); 140 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 141 } 142 } else { 143 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); 144 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); 145 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) { 146 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); 147 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 148 } else { 149 /* pll1_sys needs to be enabled for divider rate change to work. */ 150 pll1_sys_temp_enabled = true; 151 clk_prepare_enable(clks[PLL1_SYS].clk); 152 } 153 } 154 155 /* Ensure the arm clock divider is what we expect */ 156 ret = clk_set_rate(clks[ARM].clk, new_freq * 1000); 157 if (ret) { 158 int ret1; 159 160 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); 161 ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0); 162 if (ret1) 163 dev_warn(cpu_dev, 164 "failed to restore vddarm voltage: %d\n", ret1); 165 return ret; 166 } 167 168 /* PLL1 is only needed until after ARM-PODF is set. */ 169 if (pll1_sys_temp_enabled) 170 clk_disable_unprepare(clks[PLL1_SYS].clk); 171 172 /* scaling down? scale voltage after frequency */ 173 if (new_freq < old_freq) { 174 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 175 if (ret) 176 dev_warn(cpu_dev, 177 "failed to scale vddarm down: %d\n", ret); 178 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 179 if (ret) 180 dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret); 181 if (!IS_ERR(pu_reg)) { 182 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 183 if (ret) 184 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret); 185 } 186 } 187 188 return 0; 189 } 190 191 static int imx6q_cpufreq_init(struct cpufreq_policy *policy) 192 { 193 policy->clk = clks[ARM].clk; 194 cpufreq_generic_init(policy, freq_table, transition_latency); 195 policy->suspend_freq = max_freq; 196 197 return 0; 198 } 199 200 static struct cpufreq_driver imx6q_cpufreq_driver = { 201 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK | 202 CPUFREQ_IS_COOLING_DEV, 203 .verify = cpufreq_generic_frequency_table_verify, 204 .target_index = imx6q_set_target, 205 .get = cpufreq_generic_get, 206 .init = imx6q_cpufreq_init, 207 .register_em = cpufreq_register_em_with_opp, 208 .name = "imx6q-cpufreq", 209 .suspend = cpufreq_generic_suspend, 210 }; 211 212 static void imx6x_disable_freq_in_opp(struct device *dev, unsigned long freq) 213 { 214 int ret = dev_pm_opp_disable(dev, freq); 215 216 if (ret < 0 && ret != -ENODEV) 217 dev_warn(dev, "failed to disable %ldMHz OPP\n", freq / 1000000); 218 } 219 220 #define OCOTP_CFG3 0x440 221 #define OCOTP_CFG3_SPEED_SHIFT 16 222 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3 223 #define OCOTP_CFG3_SPEED_996MHZ 0x2 224 #define OCOTP_CFG3_SPEED_852MHZ 0x1 225 226 static int imx6q_opp_check_speed_grading(struct device *dev) 227 { 228 u32 val; 229 int ret; 230 231 if (of_property_present(dev->of_node, "nvmem-cells")) { 232 ret = nvmem_cell_read_u32(dev, "speed_grade", &val); 233 if (ret) 234 return ret; 235 } else { 236 struct regmap *ocotp; 237 238 ocotp = syscon_regmap_lookup_by_compatible("fsl,imx6q-ocotp"); 239 if (IS_ERR(ocotp)) 240 return -ENOENT; 241 242 /* 243 * SPEED_GRADING[1:0] defines the max speed of ARM: 244 * 2b'11: 1200000000Hz; 245 * 2b'10: 996000000Hz; 246 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. 247 * 2b'00: 792000000Hz; 248 * We need to set the max speed of ARM according to fuse map. 249 */ 250 regmap_read(ocotp, OCOTP_CFG3, &val); 251 } 252 253 val >>= OCOTP_CFG3_SPEED_SHIFT; 254 val &= 0x3; 255 256 if (val < OCOTP_CFG3_SPEED_996MHZ) 257 imx6x_disable_freq_in_opp(dev, 996000000); 258 259 if (of_machine_is_compatible("fsl,imx6q") || 260 of_machine_is_compatible("fsl,imx6qp")) { 261 if (val != OCOTP_CFG3_SPEED_852MHZ) 262 imx6x_disable_freq_in_opp(dev, 852000000); 263 264 if (val != OCOTP_CFG3_SPEED_1P2GHZ) 265 imx6x_disable_freq_in_opp(dev, 1200000000); 266 } 267 268 return 0; 269 } 270 271 #define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2 272 #define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2 273 #define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3 274 275 static int imx6ul_opp_check_speed_grading(struct device *dev) 276 { 277 u32 val; 278 int ret = 0; 279 280 if (of_property_present(dev->of_node, "nvmem-cells")) { 281 ret = nvmem_cell_read_u32(dev, "speed_grade", &val); 282 if (ret) 283 return ret; 284 } else { 285 struct regmap *ocotp; 286 287 ocotp = syscon_regmap_lookup_by_compatible("fsl,imx6ul-ocotp"); 288 if (IS_ERR(ocotp)) 289 ocotp = syscon_regmap_lookup_by_compatible("fsl,imx6ull-ocotp"); 290 291 if (IS_ERR(ocotp)) 292 return -ENOENT; 293 294 regmap_read(ocotp, OCOTP_CFG3, &val); 295 } 296 297 /* 298 * Speed GRADING[1:0] defines the max speed of ARM: 299 * 2b'00: Reserved; 300 * 2b'01: 528000000Hz; 301 * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL; 302 * 2b'11: 900000000Hz on i.MX6ULL only; 303 * We need to set the max speed of ARM according to fuse map. 304 */ 305 val >>= OCOTP_CFG3_SPEED_SHIFT; 306 val &= 0x3; 307 308 if (of_machine_is_compatible("fsl,imx6ul")) 309 if (val != OCOTP_CFG3_6UL_SPEED_696MHZ) 310 imx6x_disable_freq_in_opp(dev, 696000000); 311 312 if (of_machine_is_compatible("fsl,imx6ull")) { 313 if (val < OCOTP_CFG3_6ULL_SPEED_792MHZ) 314 imx6x_disable_freq_in_opp(dev, 792000000); 315 316 if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ) 317 imx6x_disable_freq_in_opp(dev, 900000000); 318 } 319 320 return ret; 321 } 322 323 static int imx6q_cpufreq_probe(struct platform_device *pdev) 324 { 325 struct device_node *np; 326 struct dev_pm_opp *opp; 327 unsigned long min_volt, max_volt; 328 int num, ret; 329 const struct property *prop; 330 const __be32 *val; 331 u32 nr, i, j; 332 u32 soc_opp_count = 0; 333 334 cpu_dev = get_cpu_device(0); 335 if (!cpu_dev) { 336 pr_err("failed to get cpu0 device\n"); 337 return -ENODEV; 338 } 339 340 np = of_node_get(cpu_dev->of_node); 341 if (!np) { 342 dev_err(cpu_dev, "failed to find cpu0 node\n"); 343 return -ENOENT; 344 } 345 346 if (of_machine_is_compatible("fsl,imx6ul") || 347 of_machine_is_compatible("fsl,imx6ull")) 348 num_clks = IMX6UL_CPUFREQ_CLK_NUM; 349 else 350 num_clks = IMX6Q_CPUFREQ_CLK_NUM; 351 352 ret = clk_bulk_get(cpu_dev, num_clks, clks); 353 if (ret) 354 goto put_node; 355 356 arm_reg = regulator_get(cpu_dev, "arm"); 357 pu_reg = regulator_get_optional(cpu_dev, "pu"); 358 soc_reg = regulator_get(cpu_dev, "soc"); 359 if (PTR_ERR(arm_reg) == -EPROBE_DEFER || 360 PTR_ERR(soc_reg) == -EPROBE_DEFER || 361 PTR_ERR(pu_reg) == -EPROBE_DEFER) { 362 ret = -EPROBE_DEFER; 363 dev_dbg(cpu_dev, "regulators not ready, defer\n"); 364 goto put_reg; 365 } 366 if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) { 367 dev_err(cpu_dev, "failed to get regulators\n"); 368 ret = -ENOENT; 369 goto put_reg; 370 } 371 372 ret = dev_pm_opp_of_add_table(cpu_dev); 373 if (ret < 0) { 374 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); 375 goto put_reg; 376 } 377 378 if (of_machine_is_compatible("fsl,imx6ul") || 379 of_machine_is_compatible("fsl,imx6ull")) { 380 ret = imx6ul_opp_check_speed_grading(cpu_dev); 381 } else { 382 ret = imx6q_opp_check_speed_grading(cpu_dev); 383 } 384 if (ret) { 385 dev_err_probe(cpu_dev, ret, "failed to read ocotp\n"); 386 goto out_free_opp; 387 } 388 389 num = dev_pm_opp_get_opp_count(cpu_dev); 390 if (num < 0) { 391 ret = num; 392 dev_err(cpu_dev, "no OPP table is found: %d\n", ret); 393 goto out_free_opp; 394 } 395 396 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); 397 if (ret) { 398 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); 399 goto out_free_opp; 400 } 401 402 /* Make imx6_soc_volt array's size same as arm opp number */ 403 imx6_soc_volt = devm_kcalloc(&pdev->dev, num, sizeof(*imx6_soc_volt), 404 GFP_KERNEL); 405 if (imx6_soc_volt == NULL) { 406 ret = -ENOMEM; 407 goto free_freq_table; 408 } 409 410 prop = of_find_property(np, "fsl,soc-operating-points", NULL); 411 if (!prop || !prop->value) 412 goto soc_opp_out; 413 414 /* 415 * Each OPP is a set of tuples consisting of frequency and 416 * voltage like <freq-kHz vol-uV>. 417 */ 418 nr = prop->length / sizeof(u32); 419 if (nr % 2 || (nr / 2) < num) 420 goto soc_opp_out; 421 422 for (j = 0; j < num; j++) { 423 val = prop->value; 424 for (i = 0; i < nr / 2; i++) { 425 unsigned long freq = be32_to_cpup(val++); 426 unsigned long volt = be32_to_cpup(val++); 427 if (freq_table[j].frequency == freq) { 428 imx6_soc_volt[soc_opp_count++] = volt; 429 break; 430 } 431 } 432 } 433 434 soc_opp_out: 435 /* use fixed soc opp volt if no valid soc opp info found in dtb */ 436 if (soc_opp_count != num) { 437 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n"); 438 for (j = 0; j < num; j++) 439 imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL; 440 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ) 441 imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH; 442 } 443 444 if (of_property_read_u32(np, "clock-latency", &transition_latency)) 445 transition_latency = CPUFREQ_DEFAULT_TRANSITION_LATENCY_NS; 446 447 /* 448 * Calculate the ramp time for max voltage change in the 449 * VDDSOC and VDDPU regulators. 450 */ 451 ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 452 if (ret > 0) 453 transition_latency += ret * 1000; 454 if (!IS_ERR(pu_reg)) { 455 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 456 if (ret > 0) 457 transition_latency += ret * 1000; 458 } 459 460 /* 461 * OPP is maintained in order of increasing frequency, and 462 * freq_table initialised from OPP is therefore sorted in the 463 * same order. 464 */ 465 max_freq = freq_table[--num].frequency; 466 opp = dev_pm_opp_find_freq_exact(cpu_dev, 467 freq_table[0].frequency * 1000, true); 468 min_volt = dev_pm_opp_get_voltage(opp); 469 dev_pm_opp_put(opp); 470 opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true); 471 max_volt = dev_pm_opp_get_voltage(opp); 472 dev_pm_opp_put(opp); 473 474 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); 475 if (ret > 0) 476 transition_latency += ret * 1000; 477 478 ret = cpufreq_register_driver(&imx6q_cpufreq_driver); 479 if (ret) { 480 dev_err(cpu_dev, "failed register driver: %d\n", ret); 481 goto free_freq_table; 482 } 483 484 of_node_put(np); 485 return 0; 486 487 free_freq_table: 488 imx6_soc_volt = NULL; 489 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 490 out_free_opp: 491 dev_pm_opp_of_remove_table(cpu_dev); 492 put_reg: 493 if (!IS_ERR(arm_reg)) 494 regulator_put(arm_reg); 495 if (!IS_ERR(pu_reg)) 496 regulator_put(pu_reg); 497 if (!IS_ERR(soc_reg)) 498 regulator_put(soc_reg); 499 500 clk_bulk_put(num_clks, clks); 501 put_node: 502 of_node_put(np); 503 504 return ret; 505 } 506 507 static void imx6q_cpufreq_remove(struct platform_device *pdev) 508 { 509 cpufreq_unregister_driver(&imx6q_cpufreq_driver); 510 imx6_soc_volt = NULL; 511 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 512 dev_pm_opp_of_remove_table(cpu_dev); 513 regulator_put(arm_reg); 514 if (!IS_ERR(pu_reg)) 515 regulator_put(pu_reg); 516 regulator_put(soc_reg); 517 518 clk_bulk_put(num_clks, clks); 519 } 520 521 static struct platform_driver imx6q_cpufreq_platdrv = { 522 .driver = { 523 .name = "imx6q-cpufreq", 524 }, 525 .probe = imx6q_cpufreq_probe, 526 .remove = imx6q_cpufreq_remove, 527 }; 528 module_platform_driver(imx6q_cpufreq_platdrv); 529 530 MODULE_ALIAS("platform:imx6q-cpufreq"); 531 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 532 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver"); 533 MODULE_LICENSE("GPL"); 534