1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/cpu.h> 11 #include <linux/cpufreq.h> 12 #include <linux/cpu_cooling.h> 13 #include <linux/err.h> 14 #include <linux/module.h> 15 #include <linux/nvmem-consumer.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/pm_opp.h> 19 #include <linux/platform_device.h> 20 #include <linux/regulator/consumer.h> 21 22 #define PU_SOC_VOLTAGE_NORMAL 1250000 23 #define PU_SOC_VOLTAGE_HIGH 1275000 24 #define FREQ_1P2_GHZ 1200000000 25 26 static struct regulator *arm_reg; 27 static struct regulator *pu_reg; 28 static struct regulator *soc_reg; 29 30 enum IMX6_CPUFREQ_CLKS { 31 ARM, 32 PLL1_SYS, 33 STEP, 34 PLL1_SW, 35 PLL2_PFD2_396M, 36 /* MX6UL requires two more clks */ 37 PLL2_BUS, 38 SECONDARY_SEL, 39 }; 40 #define IMX6Q_CPUFREQ_CLK_NUM 5 41 #define IMX6UL_CPUFREQ_CLK_NUM 7 42 43 static int num_clks; 44 static struct clk_bulk_data clks[] = { 45 { .id = "arm" }, 46 { .id = "pll1_sys" }, 47 { .id = "step" }, 48 { .id = "pll1_sw" }, 49 { .id = "pll2_pfd2_396m" }, 50 { .id = "pll2_bus" }, 51 { .id = "secondary_sel" }, 52 }; 53 54 static struct device *cpu_dev; 55 static struct thermal_cooling_device *cdev; 56 static bool free_opp; 57 static struct cpufreq_frequency_table *freq_table; 58 static unsigned int max_freq; 59 static unsigned int transition_latency; 60 61 static u32 *imx6_soc_volt; 62 static u32 soc_opp_count; 63 64 static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) 65 { 66 struct dev_pm_opp *opp; 67 unsigned long freq_hz, volt, volt_old; 68 unsigned int old_freq, new_freq; 69 bool pll1_sys_temp_enabled = false; 70 int ret; 71 72 new_freq = freq_table[index].frequency; 73 freq_hz = new_freq * 1000; 74 old_freq = clk_get_rate(clks[ARM].clk) / 1000; 75 76 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); 77 if (IS_ERR(opp)) { 78 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz); 79 return PTR_ERR(opp); 80 } 81 82 volt = dev_pm_opp_get_voltage(opp); 83 dev_pm_opp_put(opp); 84 85 volt_old = regulator_get_voltage(arm_reg); 86 87 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", 88 old_freq / 1000, volt_old / 1000, 89 new_freq / 1000, volt / 1000); 90 91 /* scaling up? scale voltage before frequency */ 92 if (new_freq > old_freq) { 93 if (!IS_ERR(pu_reg)) { 94 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 95 if (ret) { 96 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); 97 return ret; 98 } 99 } 100 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 101 if (ret) { 102 dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret); 103 return ret; 104 } 105 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 106 if (ret) { 107 dev_err(cpu_dev, 108 "failed to scale vddarm up: %d\n", ret); 109 return ret; 110 } 111 } 112 113 /* 114 * The setpoints are selected per PLL/PDF frequencies, so we need to 115 * reprogram PLL for frequency scaling. The procedure of reprogramming 116 * PLL1 is as below. 117 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change 118 * flow is slightly different from other i.MX6 OSC. 119 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below: 120 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it 121 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it 122 * - Disable pll2_pfd2_396m_clk 123 */ 124 if (of_machine_is_compatible("fsl,imx6ul") || 125 of_machine_is_compatible("fsl,imx6ull")) { 126 /* 127 * When changing pll1_sw_clk's parent to pll1_sys_clk, 128 * CPU may run at higher than 528MHz, this will lead to 129 * the system unstable if the voltage is lower than the 130 * voltage of 528MHz, so lower the CPU frequency to one 131 * half before changing CPU frequency. 132 */ 133 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000); 134 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 135 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) 136 clk_set_parent(clks[SECONDARY_SEL].clk, 137 clks[PLL2_BUS].clk); 138 else 139 clk_set_parent(clks[SECONDARY_SEL].clk, 140 clks[PLL2_PFD2_396M].clk); 141 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk); 142 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); 143 if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) { 144 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); 145 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 146 } 147 } else { 148 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); 149 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); 150 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) { 151 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000); 152 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); 153 } else { 154 /* pll1_sys needs to be enabled for divider rate change to work. */ 155 pll1_sys_temp_enabled = true; 156 clk_prepare_enable(clks[PLL1_SYS].clk); 157 } 158 } 159 160 /* Ensure the arm clock divider is what we expect */ 161 ret = clk_set_rate(clks[ARM].clk, new_freq * 1000); 162 if (ret) { 163 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); 164 regulator_set_voltage_tol(arm_reg, volt_old, 0); 165 return ret; 166 } 167 168 /* PLL1 is only needed until after ARM-PODF is set. */ 169 if (pll1_sys_temp_enabled) 170 clk_disable_unprepare(clks[PLL1_SYS].clk); 171 172 /* scaling down? scale voltage after frequency */ 173 if (new_freq < old_freq) { 174 ret = regulator_set_voltage_tol(arm_reg, volt, 0); 175 if (ret) { 176 dev_warn(cpu_dev, 177 "failed to scale vddarm down: %d\n", ret); 178 ret = 0; 179 } 180 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); 181 if (ret) { 182 dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret); 183 ret = 0; 184 } 185 if (!IS_ERR(pu_reg)) { 186 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); 187 if (ret) { 188 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret); 189 ret = 0; 190 } 191 } 192 } 193 194 return 0; 195 } 196 197 static void imx6q_cpufreq_ready(struct cpufreq_policy *policy) 198 { 199 cdev = of_cpufreq_cooling_register(policy); 200 201 if (!cdev) 202 dev_err(cpu_dev, 203 "running cpufreq without cooling device: %ld\n", 204 PTR_ERR(cdev)); 205 } 206 207 static int imx6q_cpufreq_init(struct cpufreq_policy *policy) 208 { 209 int ret; 210 211 policy->clk = clks[ARM].clk; 212 ret = cpufreq_generic_init(policy, freq_table, transition_latency); 213 policy->suspend_freq = max_freq; 214 215 return ret; 216 } 217 218 static int imx6q_cpufreq_exit(struct cpufreq_policy *policy) 219 { 220 cpufreq_cooling_unregister(cdev); 221 222 return 0; 223 } 224 225 static struct cpufreq_driver imx6q_cpufreq_driver = { 226 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, 227 .verify = cpufreq_generic_frequency_table_verify, 228 .target_index = imx6q_set_target, 229 .get = cpufreq_generic_get, 230 .init = imx6q_cpufreq_init, 231 .exit = imx6q_cpufreq_exit, 232 .name = "imx6q-cpufreq", 233 .ready = imx6q_cpufreq_ready, 234 .attr = cpufreq_generic_attr, 235 .suspend = cpufreq_generic_suspend, 236 }; 237 238 #define OCOTP_CFG3 0x440 239 #define OCOTP_CFG3_SPEED_SHIFT 16 240 #define OCOTP_CFG3_SPEED_1P2GHZ 0x3 241 #define OCOTP_CFG3_SPEED_996MHZ 0x2 242 #define OCOTP_CFG3_SPEED_852MHZ 0x1 243 244 static void imx6q_opp_check_speed_grading(struct device *dev) 245 { 246 struct device_node *np; 247 void __iomem *base; 248 u32 val; 249 250 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp"); 251 if (!np) 252 return; 253 254 base = of_iomap(np, 0); 255 if (!base) { 256 dev_err(dev, "failed to map ocotp\n"); 257 goto put_node; 258 } 259 260 /* 261 * SPEED_GRADING[1:0] defines the max speed of ARM: 262 * 2b'11: 1200000000Hz; 263 * 2b'10: 996000000Hz; 264 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz. 265 * 2b'00: 792000000Hz; 266 * We need to set the max speed of ARM according to fuse map. 267 */ 268 val = readl_relaxed(base + OCOTP_CFG3); 269 val >>= OCOTP_CFG3_SPEED_SHIFT; 270 val &= 0x3; 271 272 if (val < OCOTP_CFG3_SPEED_996MHZ) 273 if (dev_pm_opp_disable(dev, 996000000)) 274 dev_warn(dev, "failed to disable 996MHz OPP\n"); 275 276 if (of_machine_is_compatible("fsl,imx6q") || 277 of_machine_is_compatible("fsl,imx6qp")) { 278 if (val != OCOTP_CFG3_SPEED_852MHZ) 279 if (dev_pm_opp_disable(dev, 852000000)) 280 dev_warn(dev, "failed to disable 852MHz OPP\n"); 281 if (val != OCOTP_CFG3_SPEED_1P2GHZ) 282 if (dev_pm_opp_disable(dev, 1200000000)) 283 dev_warn(dev, "failed to disable 1.2GHz OPP\n"); 284 } 285 iounmap(base); 286 put_node: 287 of_node_put(np); 288 } 289 290 #define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2 291 #define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2 292 #define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3 293 294 static int imx6ul_opp_check_speed_grading(struct device *dev) 295 { 296 u32 val; 297 int ret = 0; 298 299 if (of_find_property(dev->of_node, "nvmem-cells", NULL)) { 300 ret = nvmem_cell_read_u32(dev, "speed_grade", &val); 301 if (ret) 302 return ret; 303 } else { 304 struct device_node *np; 305 void __iomem *base; 306 307 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp"); 308 if (!np) 309 return -ENOENT; 310 311 base = of_iomap(np, 0); 312 of_node_put(np); 313 if (!base) { 314 dev_err(dev, "failed to map ocotp\n"); 315 return -EFAULT; 316 } 317 318 val = readl_relaxed(base + OCOTP_CFG3); 319 iounmap(base); 320 } 321 322 /* 323 * Speed GRADING[1:0] defines the max speed of ARM: 324 * 2b'00: Reserved; 325 * 2b'01: 528000000Hz; 326 * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL; 327 * 2b'11: 900000000Hz on i.MX6ULL only; 328 * We need to set the max speed of ARM according to fuse map. 329 */ 330 val >>= OCOTP_CFG3_SPEED_SHIFT; 331 val &= 0x3; 332 333 if (of_machine_is_compatible("fsl,imx6ul")) { 334 if (val != OCOTP_CFG3_6UL_SPEED_696MHZ) 335 if (dev_pm_opp_disable(dev, 696000000)) 336 dev_warn(dev, "failed to disable 696MHz OPP\n"); 337 } 338 339 if (of_machine_is_compatible("fsl,imx6ull")) { 340 if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ) 341 if (dev_pm_opp_disable(dev, 792000000)) 342 dev_warn(dev, "failed to disable 792MHz OPP\n"); 343 344 if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ) 345 if (dev_pm_opp_disable(dev, 900000000)) 346 dev_warn(dev, "failed to disable 900MHz OPP\n"); 347 } 348 349 return ret; 350 } 351 352 static int imx6q_cpufreq_probe(struct platform_device *pdev) 353 { 354 struct device_node *np; 355 struct dev_pm_opp *opp; 356 unsigned long min_volt, max_volt; 357 int num, ret; 358 const struct property *prop; 359 const __be32 *val; 360 u32 nr, i, j; 361 362 cpu_dev = get_cpu_device(0); 363 if (!cpu_dev) { 364 pr_err("failed to get cpu0 device\n"); 365 return -ENODEV; 366 } 367 368 np = of_node_get(cpu_dev->of_node); 369 if (!np) { 370 dev_err(cpu_dev, "failed to find cpu0 node\n"); 371 return -ENOENT; 372 } 373 374 if (of_machine_is_compatible("fsl,imx6ul") || 375 of_machine_is_compatible("fsl,imx6ull")) 376 num_clks = IMX6UL_CPUFREQ_CLK_NUM; 377 else 378 num_clks = IMX6Q_CPUFREQ_CLK_NUM; 379 380 ret = clk_bulk_get(cpu_dev, num_clks, clks); 381 if (ret) 382 goto put_node; 383 384 arm_reg = regulator_get(cpu_dev, "arm"); 385 pu_reg = regulator_get_optional(cpu_dev, "pu"); 386 soc_reg = regulator_get(cpu_dev, "soc"); 387 if (PTR_ERR(arm_reg) == -EPROBE_DEFER || 388 PTR_ERR(soc_reg) == -EPROBE_DEFER || 389 PTR_ERR(pu_reg) == -EPROBE_DEFER) { 390 ret = -EPROBE_DEFER; 391 dev_dbg(cpu_dev, "regulators not ready, defer\n"); 392 goto put_reg; 393 } 394 if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) { 395 dev_err(cpu_dev, "failed to get regulators\n"); 396 ret = -ENOENT; 397 goto put_reg; 398 } 399 400 ret = dev_pm_opp_of_add_table(cpu_dev); 401 if (ret < 0) { 402 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret); 403 goto put_reg; 404 } 405 406 if (of_machine_is_compatible("fsl,imx6ul") || 407 of_machine_is_compatible("fsl,imx6ull")) { 408 ret = imx6ul_opp_check_speed_grading(cpu_dev); 409 if (ret == -EPROBE_DEFER) 410 return ret; 411 if (ret) { 412 dev_err(cpu_dev, "failed to read ocotp: %d\n", 413 ret); 414 return ret; 415 } 416 } else { 417 imx6q_opp_check_speed_grading(cpu_dev); 418 } 419 420 /* Because we have added the OPPs here, we must free them */ 421 free_opp = true; 422 num = dev_pm_opp_get_opp_count(cpu_dev); 423 if (num < 0) { 424 ret = num; 425 dev_err(cpu_dev, "no OPP table is found: %d\n", ret); 426 goto out_free_opp; 427 } 428 429 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); 430 if (ret) { 431 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); 432 goto out_free_opp; 433 } 434 435 /* Make imx6_soc_volt array's size same as arm opp number */ 436 imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt), 437 GFP_KERNEL); 438 if (imx6_soc_volt == NULL) { 439 ret = -ENOMEM; 440 goto free_freq_table; 441 } 442 443 prop = of_find_property(np, "fsl,soc-operating-points", NULL); 444 if (!prop || !prop->value) 445 goto soc_opp_out; 446 447 /* 448 * Each OPP is a set of tuples consisting of frequency and 449 * voltage like <freq-kHz vol-uV>. 450 */ 451 nr = prop->length / sizeof(u32); 452 if (nr % 2 || (nr / 2) < num) 453 goto soc_opp_out; 454 455 for (j = 0; j < num; j++) { 456 val = prop->value; 457 for (i = 0; i < nr / 2; i++) { 458 unsigned long freq = be32_to_cpup(val++); 459 unsigned long volt = be32_to_cpup(val++); 460 if (freq_table[j].frequency == freq) { 461 imx6_soc_volt[soc_opp_count++] = volt; 462 break; 463 } 464 } 465 } 466 467 soc_opp_out: 468 /* use fixed soc opp volt if no valid soc opp info found in dtb */ 469 if (soc_opp_count != num) { 470 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n"); 471 for (j = 0; j < num; j++) 472 imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL; 473 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ) 474 imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH; 475 } 476 477 if (of_property_read_u32(np, "clock-latency", &transition_latency)) 478 transition_latency = CPUFREQ_ETERNAL; 479 480 /* 481 * Calculate the ramp time for max voltage change in the 482 * VDDSOC and VDDPU regulators. 483 */ 484 ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 485 if (ret > 0) 486 transition_latency += ret * 1000; 487 if (!IS_ERR(pu_reg)) { 488 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); 489 if (ret > 0) 490 transition_latency += ret * 1000; 491 } 492 493 /* 494 * OPP is maintained in order of increasing frequency, and 495 * freq_table initialised from OPP is therefore sorted in the 496 * same order. 497 */ 498 max_freq = freq_table[--num].frequency; 499 opp = dev_pm_opp_find_freq_exact(cpu_dev, 500 freq_table[0].frequency * 1000, true); 501 min_volt = dev_pm_opp_get_voltage(opp); 502 dev_pm_opp_put(opp); 503 opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true); 504 max_volt = dev_pm_opp_get_voltage(opp); 505 dev_pm_opp_put(opp); 506 507 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt); 508 if (ret > 0) 509 transition_latency += ret * 1000; 510 511 ret = cpufreq_register_driver(&imx6q_cpufreq_driver); 512 if (ret) { 513 dev_err(cpu_dev, "failed register driver: %d\n", ret); 514 goto free_freq_table; 515 } 516 517 of_node_put(np); 518 return 0; 519 520 free_freq_table: 521 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 522 out_free_opp: 523 if (free_opp) 524 dev_pm_opp_of_remove_table(cpu_dev); 525 put_reg: 526 if (!IS_ERR(arm_reg)) 527 regulator_put(arm_reg); 528 if (!IS_ERR(pu_reg)) 529 regulator_put(pu_reg); 530 if (!IS_ERR(soc_reg)) 531 regulator_put(soc_reg); 532 533 clk_bulk_put(num_clks, clks); 534 put_node: 535 of_node_put(np); 536 537 return ret; 538 } 539 540 static int imx6q_cpufreq_remove(struct platform_device *pdev) 541 { 542 cpufreq_unregister_driver(&imx6q_cpufreq_driver); 543 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); 544 if (free_opp) 545 dev_pm_opp_of_remove_table(cpu_dev); 546 regulator_put(arm_reg); 547 if (!IS_ERR(pu_reg)) 548 regulator_put(pu_reg); 549 regulator_put(soc_reg); 550 551 clk_bulk_put(num_clks, clks); 552 553 return 0; 554 } 555 556 static struct platform_driver imx6q_cpufreq_platdrv = { 557 .driver = { 558 .name = "imx6q-cpufreq", 559 }, 560 .probe = imx6q_cpufreq_probe, 561 .remove = imx6q_cpufreq_remove, 562 }; 563 module_platform_driver(imx6q_cpufreq_platdrv); 564 565 MODULE_ALIAS("platform:imx6q-cpufreq"); 566 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 567 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver"); 568 MODULE_LICENSE("GPL"); 569