1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2016 Linaro. 4 * Viresh Kumar <viresh.kumar@linaro.org> 5 */ 6 7 #include <linux/err.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 12 #include "cpufreq-dt.h" 13 14 /* 15 * Machines for which the cpufreq device is *always* created, mostly used for 16 * platforms using "operating-points" (V1) property. 17 */ 18 static const struct of_device_id allowlist[] __initconst = { 19 { .compatible = "allwinner,sun4i-a10", }, 20 { .compatible = "allwinner,sun5i-a10s", }, 21 { .compatible = "allwinner,sun5i-a13", }, 22 { .compatible = "allwinner,sun5i-r8", }, 23 { .compatible = "allwinner,sun6i-a31", }, 24 { .compatible = "allwinner,sun6i-a31s", }, 25 { .compatible = "allwinner,sun7i-a20", }, 26 { .compatible = "allwinner,sun8i-a23", }, 27 { .compatible = "allwinner,sun8i-a83t", }, 28 { .compatible = "allwinner,sun8i-h3", }, 29 30 { .compatible = "apm,xgene-shadowcat", }, 31 32 { .compatible = "arm,integrator-ap", }, 33 { .compatible = "arm,integrator-cp", }, 34 35 { .compatible = "hisilicon,hi3660", }, 36 37 { .compatible = "fsl,imx27", }, 38 { .compatible = "fsl,imx51", }, 39 { .compatible = "fsl,imx53", }, 40 41 { .compatible = "marvell,berlin", }, 42 { .compatible = "marvell,pxa250", }, 43 { .compatible = "marvell,pxa270", }, 44 45 { .compatible = "samsung,exynos3250", }, 46 { .compatible = "samsung,exynos4210", }, 47 { .compatible = "samsung,exynos5250", }, 48 #ifndef CONFIG_BL_SWITCHER 49 { .compatible = "samsung,exynos5800", }, 50 #endif 51 52 { .compatible = "renesas,emev2", }, 53 { .compatible = "renesas,r7s72100", }, 54 { .compatible = "renesas,r8a73a4", }, 55 { .compatible = "renesas,r8a7740", }, 56 { .compatible = "renesas,r8a7742", }, 57 { .compatible = "renesas,r8a7743", }, 58 { .compatible = "renesas,r8a7744", }, 59 { .compatible = "renesas,r8a7745", }, 60 { .compatible = "renesas,r8a7778", }, 61 { .compatible = "renesas,r8a7779", }, 62 { .compatible = "renesas,r8a7790", }, 63 { .compatible = "renesas,r8a7791", }, 64 { .compatible = "renesas,r8a7792", }, 65 { .compatible = "renesas,r8a7793", }, 66 { .compatible = "renesas,r8a7794", }, 67 { .compatible = "renesas,sh73a0", }, 68 69 { .compatible = "rockchip,rk2928", }, 70 { .compatible = "rockchip,rk3036", }, 71 { .compatible = "rockchip,rk3066a", }, 72 { .compatible = "rockchip,rk3066b", }, 73 { .compatible = "rockchip,rk3188", }, 74 { .compatible = "rockchip,rk3228", }, 75 { .compatible = "rockchip,rk3288", }, 76 { .compatible = "rockchip,rk3328", }, 77 { .compatible = "rockchip,rk3366", }, 78 { .compatible = "rockchip,rk3368", }, 79 { .compatible = "rockchip,rk3399", 80 .data = &(struct cpufreq_dt_platform_data) 81 { .have_governor_per_policy = true, }, 82 }, 83 84 { .compatible = "st-ericsson,u8500", }, 85 { .compatible = "st-ericsson,u8540", }, 86 { .compatible = "st-ericsson,u9500", }, 87 { .compatible = "st-ericsson,u9540", }, 88 89 { .compatible = "starfive,jh7110", }, 90 91 { .compatible = "ti,omap2", }, 92 { .compatible = "ti,omap4", }, 93 { .compatible = "ti,omap5", }, 94 95 { .compatible = "xlnx,zynq-7000", }, 96 { .compatible = "xlnx,zynqmp", }, 97 98 { } 99 }; 100 101 /* 102 * Machines for which the cpufreq device is *not* created, mostly used for 103 * platforms using "operating-points-v2" property. 104 */ 105 static const struct of_device_id blocklist[] __initconst = { 106 { .compatible = "allwinner,sun50i-h6", }, 107 { .compatible = "allwinner,sun50i-h616", }, 108 { .compatible = "allwinner,sun50i-h618", }, 109 { .compatible = "allwinner,sun50i-h700", }, 110 111 { .compatible = "apple,arm-platform", }, 112 113 { .compatible = "arm,vexpress", }, 114 115 { .compatible = "calxeda,highbank", }, 116 { .compatible = "calxeda,ecx-2000", }, 117 118 { .compatible = "fsl,imx7ulp", }, 119 { .compatible = "fsl,imx7d", }, 120 { .compatible = "fsl,imx7s", }, 121 { .compatible = "fsl,imx8mq", }, 122 { .compatible = "fsl,imx8mm", }, 123 { .compatible = "fsl,imx8mn", }, 124 { .compatible = "fsl,imx8mp", }, 125 126 { .compatible = "marvell,armadaxp", }, 127 128 { .compatible = "mediatek,mt2701", }, 129 { .compatible = "mediatek,mt2712", }, 130 { .compatible = "mediatek,mt7622", }, 131 { .compatible = "mediatek,mt7623", }, 132 { .compatible = "mediatek,mt8167", }, 133 { .compatible = "mediatek,mt817x", }, 134 { .compatible = "mediatek,mt8173", }, 135 { .compatible = "mediatek,mt8176", }, 136 { .compatible = "mediatek,mt8183", }, 137 { .compatible = "mediatek,mt8186", }, 138 { .compatible = "mediatek,mt8365", }, 139 { .compatible = "mediatek,mt8516", }, 140 141 { .compatible = "nvidia,tegra20", }, 142 { .compatible = "nvidia,tegra30", }, 143 { .compatible = "nvidia,tegra124", }, 144 { .compatible = "nvidia,tegra210", }, 145 { .compatible = "nvidia,tegra234", }, 146 147 { .compatible = "qcom,apq8096", }, 148 { .compatible = "qcom,msm8909", }, 149 { .compatible = "qcom,msm8996", }, 150 { .compatible = "qcom,msm8998", }, 151 { .compatible = "qcom,qcm2290", }, 152 { .compatible = "qcom,qcm6490", }, 153 { .compatible = "qcom,qcs404", }, 154 { .compatible = "qcom,qdu1000", }, 155 { .compatible = "qcom,sa8155p" }, 156 { .compatible = "qcom,sa8540p" }, 157 { .compatible = "qcom,sa8775p" }, 158 { .compatible = "qcom,sc7180", }, 159 { .compatible = "qcom,sc7280", }, 160 { .compatible = "qcom,sc8180x", }, 161 { .compatible = "qcom,sc8280xp", }, 162 { .compatible = "qcom,sdm670", }, 163 { .compatible = "qcom,sdm845", }, 164 { .compatible = "qcom,sdx75", }, 165 { .compatible = "qcom,sm6115", }, 166 { .compatible = "qcom,sm6350", }, 167 { .compatible = "qcom,sm6375", }, 168 { .compatible = "qcom,sm7225", }, 169 { .compatible = "qcom,sm8150", }, 170 { .compatible = "qcom,sm8250", }, 171 { .compatible = "qcom,sm8350", }, 172 { .compatible = "qcom,sm8450", }, 173 { .compatible = "qcom,sm8550", }, 174 175 { .compatible = "st,stih407", }, 176 { .compatible = "st,stih410", }, 177 { .compatible = "st,stih418", }, 178 179 { .compatible = "ti,am33xx", }, 180 { .compatible = "ti,am43", }, 181 { .compatible = "ti,dra7", }, 182 { .compatible = "ti,omap3", }, 183 { .compatible = "ti,am625", }, 184 { .compatible = "ti,am62a7", }, 185 { .compatible = "ti,am62p5", }, 186 187 { .compatible = "qcom,ipq5332", }, 188 { .compatible = "qcom,ipq6018", }, 189 { .compatible = "qcom,ipq8064", }, 190 { .compatible = "qcom,ipq8074", }, 191 { .compatible = "qcom,ipq9574", }, 192 { .compatible = "qcom,apq8064", }, 193 { .compatible = "qcom,msm8974", }, 194 { .compatible = "qcom,msm8960", }, 195 196 { } 197 }; 198 199 static bool __init cpu0_node_has_opp_v2_prop(void) 200 { 201 struct device_node *np __free(device_node) = of_cpu_device_node_get(0); 202 bool ret = false; 203 204 if (of_property_present(np, "operating-points-v2")) 205 ret = true; 206 207 return ret; 208 } 209 210 static int __init cpufreq_dt_platdev_init(void) 211 { 212 struct device_node *np __free(device_node) = of_find_node_by_path("/"); 213 const struct of_device_id *match; 214 const void *data = NULL; 215 216 if (!np) 217 return -ENODEV; 218 219 match = of_match_node(allowlist, np); 220 if (match) { 221 data = match->data; 222 goto create_pdev; 223 } 224 225 if (cpu0_node_has_opp_v2_prop() && !of_match_node(blocklist, np)) 226 goto create_pdev; 227 228 return -ENODEV; 229 230 create_pdev: 231 return PTR_ERR_OR_ZERO(platform_device_register_data(NULL, "cpufreq-dt", 232 -1, data, 233 sizeof(struct cpufreq_dt_platform_data))); 234 } 235 core_initcall(cpufreq_dt_platdev_init); 236 MODULE_LICENSE("GPL"); 237