1 /* 2 * CPU frequency scaling for Broadcom SoCs with AVS firmware that 3 * supports DVS or DVFS 4 * 5 * Copyright (c) 2016 Broadcom 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 /* 18 * "AVS" is the name of a firmware developed at Broadcom. It derives 19 * its name from the technique called "Adaptive Voltage Scaling". 20 * Adaptive voltage scaling was the original purpose of this firmware. 21 * The AVS firmware still supports "AVS mode", where all it does is 22 * adaptive voltage scaling. However, on some newer Broadcom SoCs, the 23 * AVS Firmware, despite its unchanged name, also supports DFS mode and 24 * DVFS mode. 25 * 26 * In the context of this document and the related driver, "AVS" by 27 * itself always means the Broadcom firmware and never refers to the 28 * technique called "Adaptive Voltage Scaling". 29 * 30 * The Broadcom STB AVS CPUfreq driver provides voltage and frequency 31 * scaling on Broadcom SoCs using AVS firmware with support for DFS and 32 * DVFS. The AVS firmware is running on its own co-processor. The 33 * driver supports both uniprocessor (UP) and symmetric multiprocessor 34 * (SMP) systems which share clock and voltage across all CPUs. 35 * 36 * Actual voltage and frequency scaling is done solely by the AVS 37 * firmware. This driver does not change frequency or voltage itself. 38 * It provides a standard CPUfreq interface to the rest of the kernel 39 * and to userland. It interfaces with the AVS firmware to effect the 40 * requested changes and to report back the current system status in a 41 * way that is expected by existing tools. 42 */ 43 44 #include <linux/cpufreq.h> 45 #include <linux/interrupt.h> 46 #include <linux/io.h> 47 #include <linux/module.h> 48 #include <linux/of_address.h> 49 #include <linux/platform_device.h> 50 #include <linux/semaphore.h> 51 52 #ifdef CONFIG_ARM_BRCMSTB_AVS_CPUFREQ_DEBUG 53 #include <linux/ctype.h> 54 #include <linux/debugfs.h> 55 #include <linux/slab.h> 56 #include <linux/uaccess.h> 57 #endif 58 59 /* Max number of arguments AVS calls take */ 60 #define AVS_MAX_CMD_ARGS 4 61 /* 62 * This macro is used to generate AVS parameter register offsets. For 63 * x >= AVS_MAX_CMD_ARGS, it returns 0 to protect against accidental memory 64 * access outside of the parameter range. (Offset 0 is the first parameter.) 65 */ 66 #define AVS_PARAM_MULT(x) ((x) < AVS_MAX_CMD_ARGS ? (x) : 0) 67 68 /* AVS Mailbox Register offsets */ 69 #define AVS_MBOX_COMMAND 0x00 70 #define AVS_MBOX_STATUS 0x04 71 #define AVS_MBOX_VOLTAGE0 0x08 72 #define AVS_MBOX_TEMP0 0x0c 73 #define AVS_MBOX_PV0 0x10 74 #define AVS_MBOX_MV0 0x14 75 #define AVS_MBOX_PARAM(x) (0x18 + AVS_PARAM_MULT(x) * sizeof(u32)) 76 #define AVS_MBOX_REVISION 0x28 77 #define AVS_MBOX_PSTATE 0x2c 78 #define AVS_MBOX_HEARTBEAT 0x30 79 #define AVS_MBOX_MAGIC 0x34 80 #define AVS_MBOX_SIGMA_HVT 0x38 81 #define AVS_MBOX_SIGMA_SVT 0x3c 82 #define AVS_MBOX_VOLTAGE1 0x40 83 #define AVS_MBOX_TEMP1 0x44 84 #define AVS_MBOX_PV1 0x48 85 #define AVS_MBOX_MV1 0x4c 86 #define AVS_MBOX_FREQUENCY 0x50 87 88 /* AVS Commands */ 89 #define AVS_CMD_AVAILABLE 0x00 90 #define AVS_CMD_DISABLE 0x10 91 #define AVS_CMD_ENABLE 0x11 92 #define AVS_CMD_S2_ENTER 0x12 93 #define AVS_CMD_S2_EXIT 0x13 94 #define AVS_CMD_BBM_ENTER 0x14 95 #define AVS_CMD_BBM_EXIT 0x15 96 #define AVS_CMD_S3_ENTER 0x16 97 #define AVS_CMD_S3_EXIT 0x17 98 #define AVS_CMD_BALANCE 0x18 99 /* PMAP and P-STATE commands */ 100 #define AVS_CMD_GET_PMAP 0x30 101 #define AVS_CMD_SET_PMAP 0x31 102 #define AVS_CMD_GET_PSTATE 0x40 103 #define AVS_CMD_SET_PSTATE 0x41 104 105 /* Different modes AVS supports (for GET_PMAP/SET_PMAP) */ 106 #define AVS_MODE_AVS 0x0 107 #define AVS_MODE_DFS 0x1 108 #define AVS_MODE_DVS 0x2 109 #define AVS_MODE_DVFS 0x3 110 111 /* 112 * PMAP parameter p1 113 * unused:31-24, mdiv_p0:23-16, unused:15-14, pdiv:13-10 , ndiv_int:9-0 114 */ 115 #define NDIV_INT_SHIFT 0 116 #define NDIV_INT_MASK 0x3ff 117 #define PDIV_SHIFT 10 118 #define PDIV_MASK 0xf 119 #define MDIV_P0_SHIFT 16 120 #define MDIV_P0_MASK 0xff 121 /* 122 * PMAP parameter p2 123 * mdiv_p4:31-24, mdiv_p3:23-16, mdiv_p2:15:8, mdiv_p1:7:0 124 */ 125 #define MDIV_P1_SHIFT 0 126 #define MDIV_P1_MASK 0xff 127 #define MDIV_P2_SHIFT 8 128 #define MDIV_P2_MASK 0xff 129 #define MDIV_P3_SHIFT 16 130 #define MDIV_P3_MASK 0xff 131 #define MDIV_P4_SHIFT 24 132 #define MDIV_P4_MASK 0xff 133 134 /* Different P-STATES AVS supports (for GET_PSTATE/SET_PSTATE) */ 135 #define AVS_PSTATE_P0 0x0 136 #define AVS_PSTATE_P1 0x1 137 #define AVS_PSTATE_P2 0x2 138 #define AVS_PSTATE_P3 0x3 139 #define AVS_PSTATE_P4 0x4 140 #define AVS_PSTATE_MAX AVS_PSTATE_P4 141 142 /* CPU L2 Interrupt Controller Registers */ 143 #define AVS_CPU_L2_SET0 0x04 144 #define AVS_CPU_L2_INT_MASK BIT(31) 145 146 /* AVS Command Status Values */ 147 #define AVS_STATUS_CLEAR 0x00 148 /* Command/notification accepted */ 149 #define AVS_STATUS_SUCCESS 0xf0 150 /* Command/notification rejected */ 151 #define AVS_STATUS_FAILURE 0xff 152 /* Invalid command/notification (unknown) */ 153 #define AVS_STATUS_INVALID 0xf1 154 /* Non-AVS modes are not supported */ 155 #define AVS_STATUS_NO_SUPP 0xf2 156 /* Cannot set P-State until P-Map supplied */ 157 #define AVS_STATUS_NO_MAP 0xf3 158 /* Cannot change P-Map after initial P-Map set */ 159 #define AVS_STATUS_MAP_SET 0xf4 160 /* Max AVS status; higher numbers are used for debugging */ 161 #define AVS_STATUS_MAX 0xff 162 163 /* Other AVS related constants */ 164 #define AVS_LOOP_LIMIT 10000 165 #define AVS_TIMEOUT 300 /* in ms; expected completion is < 10ms */ 166 #define AVS_FIRMWARE_MAGIC 0xa11600d1 167 168 #define BRCM_AVS_CPUFREQ_PREFIX "brcmstb-avs" 169 #define BRCM_AVS_CPUFREQ_NAME BRCM_AVS_CPUFREQ_PREFIX "-cpufreq" 170 #define BRCM_AVS_CPU_DATA "brcm,avs-cpu-data-mem" 171 #define BRCM_AVS_CPU_INTR "brcm,avs-cpu-l2-intr" 172 #define BRCM_AVS_HOST_INTR "sw_intr" 173 174 struct pmap { 175 unsigned int mode; 176 unsigned int p1; 177 unsigned int p2; 178 unsigned int state; 179 }; 180 181 struct private_data { 182 void __iomem *base; 183 void __iomem *avs_intr_base; 184 struct device *dev; 185 #ifdef CONFIG_ARM_BRCMSTB_AVS_CPUFREQ_DEBUG 186 struct dentry *debugfs; 187 #endif 188 struct completion done; 189 struct semaphore sem; 190 struct pmap pmap; 191 }; 192 193 #ifdef CONFIG_ARM_BRCMSTB_AVS_CPUFREQ_DEBUG 194 195 enum debugfs_format { 196 DEBUGFS_NORMAL, 197 DEBUGFS_FLOAT, 198 DEBUGFS_REV, 199 }; 200 201 struct debugfs_data { 202 struct debugfs_entry *entry; 203 struct private_data *priv; 204 }; 205 206 struct debugfs_entry { 207 char *name; 208 u32 offset; 209 fmode_t mode; 210 enum debugfs_format format; 211 }; 212 213 #define DEBUGFS_ENTRY(name, mode, format) { \ 214 #name, AVS_MBOX_##name, mode, format \ 215 } 216 217 /* 218 * These are used for debugfs only. Otherwise we use AVS_MBOX_PARAM() directly. 219 */ 220 #define AVS_MBOX_PARAM1 AVS_MBOX_PARAM(0) 221 #define AVS_MBOX_PARAM2 AVS_MBOX_PARAM(1) 222 #define AVS_MBOX_PARAM3 AVS_MBOX_PARAM(2) 223 #define AVS_MBOX_PARAM4 AVS_MBOX_PARAM(3) 224 225 /* 226 * This table stores the name, access permissions and offset for each hardware 227 * register and is used to generate debugfs entries. 228 */ 229 static struct debugfs_entry debugfs_entries[] = { 230 DEBUGFS_ENTRY(COMMAND, S_IWUSR, DEBUGFS_NORMAL), 231 DEBUGFS_ENTRY(STATUS, S_IWUSR, DEBUGFS_NORMAL), 232 DEBUGFS_ENTRY(VOLTAGE0, 0, DEBUGFS_FLOAT), 233 DEBUGFS_ENTRY(TEMP0, 0, DEBUGFS_FLOAT), 234 DEBUGFS_ENTRY(PV0, 0, DEBUGFS_FLOAT), 235 DEBUGFS_ENTRY(MV0, 0, DEBUGFS_FLOAT), 236 DEBUGFS_ENTRY(PARAM1, S_IWUSR, DEBUGFS_NORMAL), 237 DEBUGFS_ENTRY(PARAM2, S_IWUSR, DEBUGFS_NORMAL), 238 DEBUGFS_ENTRY(PARAM3, S_IWUSR, DEBUGFS_NORMAL), 239 DEBUGFS_ENTRY(PARAM4, S_IWUSR, DEBUGFS_NORMAL), 240 DEBUGFS_ENTRY(REVISION, 0, DEBUGFS_REV), 241 DEBUGFS_ENTRY(PSTATE, 0, DEBUGFS_NORMAL), 242 DEBUGFS_ENTRY(HEARTBEAT, 0, DEBUGFS_NORMAL), 243 DEBUGFS_ENTRY(MAGIC, S_IWUSR, DEBUGFS_NORMAL), 244 DEBUGFS_ENTRY(SIGMA_HVT, 0, DEBUGFS_NORMAL), 245 DEBUGFS_ENTRY(SIGMA_SVT, 0, DEBUGFS_NORMAL), 246 DEBUGFS_ENTRY(VOLTAGE1, 0, DEBUGFS_FLOAT), 247 DEBUGFS_ENTRY(TEMP1, 0, DEBUGFS_FLOAT), 248 DEBUGFS_ENTRY(PV1, 0, DEBUGFS_FLOAT), 249 DEBUGFS_ENTRY(MV1, 0, DEBUGFS_FLOAT), 250 DEBUGFS_ENTRY(FREQUENCY, 0, DEBUGFS_NORMAL), 251 }; 252 253 static int brcm_avs_target_index(struct cpufreq_policy *, unsigned int); 254 255 static char *__strtolower(char *s) 256 { 257 char *p; 258 259 for (p = s; *p; p++) 260 *p = tolower(*p); 261 262 return s; 263 } 264 265 #endif /* CONFIG_ARM_BRCMSTB_AVS_CPUFREQ_DEBUG */ 266 267 static void __iomem *__map_region(const char *name) 268 { 269 struct device_node *np; 270 void __iomem *ptr; 271 272 np = of_find_compatible_node(NULL, NULL, name); 273 if (!np) 274 return NULL; 275 276 ptr = of_iomap(np, 0); 277 of_node_put(np); 278 279 return ptr; 280 } 281 282 static int __issue_avs_command(struct private_data *priv, int cmd, bool is_send, 283 u32 args[]) 284 { 285 unsigned long time_left = msecs_to_jiffies(AVS_TIMEOUT); 286 void __iomem *base = priv->base; 287 unsigned int i; 288 int ret; 289 u32 val; 290 291 ret = down_interruptible(&priv->sem); 292 if (ret) 293 return ret; 294 295 /* 296 * Make sure no other command is currently running: cmd is 0 if AVS 297 * co-processor is idle. Due to the guard above, we should almost never 298 * have to wait here. 299 */ 300 for (i = 0, val = 1; val != 0 && i < AVS_LOOP_LIMIT; i++) 301 val = readl(base + AVS_MBOX_COMMAND); 302 303 /* Give the caller a chance to retry if AVS is busy. */ 304 if (i == AVS_LOOP_LIMIT) { 305 ret = -EAGAIN; 306 goto out; 307 } 308 309 /* Clear status before we begin. */ 310 writel(AVS_STATUS_CLEAR, base + AVS_MBOX_STATUS); 311 312 /* We need to send arguments for this command. */ 313 if (args && is_send) { 314 for (i = 0; i < AVS_MAX_CMD_ARGS; i++) 315 writel(args[i], base + AVS_MBOX_PARAM(i)); 316 } 317 318 /* Protect from spurious interrupts. */ 319 reinit_completion(&priv->done); 320 321 /* Now issue the command & tell firmware to wake up to process it. */ 322 writel(cmd, base + AVS_MBOX_COMMAND); 323 writel(AVS_CPU_L2_INT_MASK, priv->avs_intr_base + AVS_CPU_L2_SET0); 324 325 /* Wait for AVS co-processor to finish processing the command. */ 326 time_left = wait_for_completion_timeout(&priv->done, time_left); 327 328 /* 329 * If the AVS status is not in the expected range, it means AVS didn't 330 * complete our command in time, and we return an error. Also, if there 331 * is no "time left", we timed out waiting for the interrupt. 332 */ 333 val = readl(base + AVS_MBOX_STATUS); 334 if (time_left == 0 || val == 0 || val > AVS_STATUS_MAX) { 335 dev_err(priv->dev, "AVS command %#x didn't complete in time\n", 336 cmd); 337 dev_err(priv->dev, " Time left: %u ms, AVS status: %#x\n", 338 jiffies_to_msecs(time_left), val); 339 ret = -ETIMEDOUT; 340 goto out; 341 } 342 343 /* This command returned arguments, so we read them back. */ 344 if (args && !is_send) { 345 for (i = 0; i < AVS_MAX_CMD_ARGS; i++) 346 args[i] = readl(base + AVS_MBOX_PARAM(i)); 347 } 348 349 /* Clear status to tell AVS co-processor we are done. */ 350 writel(AVS_STATUS_CLEAR, base + AVS_MBOX_STATUS); 351 352 /* Convert firmware errors to errno's as much as possible. */ 353 switch (val) { 354 case AVS_STATUS_INVALID: 355 ret = -EINVAL; 356 break; 357 case AVS_STATUS_NO_SUPP: 358 ret = -ENOTSUPP; 359 break; 360 case AVS_STATUS_NO_MAP: 361 ret = -ENOENT; 362 break; 363 case AVS_STATUS_MAP_SET: 364 ret = -EEXIST; 365 break; 366 case AVS_STATUS_FAILURE: 367 ret = -EIO; 368 break; 369 } 370 371 out: 372 up(&priv->sem); 373 374 return ret; 375 } 376 377 static irqreturn_t irq_handler(int irq, void *data) 378 { 379 struct private_data *priv = data; 380 381 /* AVS command completed execution. Wake up __issue_avs_command(). */ 382 complete(&priv->done); 383 384 return IRQ_HANDLED; 385 } 386 387 static char *brcm_avs_mode_to_string(unsigned int mode) 388 { 389 switch (mode) { 390 case AVS_MODE_AVS: 391 return "AVS"; 392 case AVS_MODE_DFS: 393 return "DFS"; 394 case AVS_MODE_DVS: 395 return "DVS"; 396 case AVS_MODE_DVFS: 397 return "DVFS"; 398 } 399 return NULL; 400 } 401 402 static void brcm_avs_parse_p1(u32 p1, unsigned int *mdiv_p0, unsigned int *pdiv, 403 unsigned int *ndiv) 404 { 405 *mdiv_p0 = (p1 >> MDIV_P0_SHIFT) & MDIV_P0_MASK; 406 *pdiv = (p1 >> PDIV_SHIFT) & PDIV_MASK; 407 *ndiv = (p1 >> NDIV_INT_SHIFT) & NDIV_INT_MASK; 408 } 409 410 static void brcm_avs_parse_p2(u32 p2, unsigned int *mdiv_p1, 411 unsigned int *mdiv_p2, unsigned int *mdiv_p3, 412 unsigned int *mdiv_p4) 413 { 414 *mdiv_p4 = (p2 >> MDIV_P4_SHIFT) & MDIV_P4_MASK; 415 *mdiv_p3 = (p2 >> MDIV_P3_SHIFT) & MDIV_P3_MASK; 416 *mdiv_p2 = (p2 >> MDIV_P2_SHIFT) & MDIV_P2_MASK; 417 *mdiv_p1 = (p2 >> MDIV_P1_SHIFT) & MDIV_P1_MASK; 418 } 419 420 static int brcm_avs_get_pmap(struct private_data *priv, struct pmap *pmap) 421 { 422 u32 args[AVS_MAX_CMD_ARGS]; 423 int ret; 424 425 ret = __issue_avs_command(priv, AVS_CMD_GET_PMAP, false, args); 426 if (ret || !pmap) 427 return ret; 428 429 pmap->mode = args[0]; 430 pmap->p1 = args[1]; 431 pmap->p2 = args[2]; 432 pmap->state = args[3]; 433 434 return 0; 435 } 436 437 static int brcm_avs_set_pmap(struct private_data *priv, struct pmap *pmap) 438 { 439 u32 args[AVS_MAX_CMD_ARGS]; 440 441 args[0] = pmap->mode; 442 args[1] = pmap->p1; 443 args[2] = pmap->p2; 444 args[3] = pmap->state; 445 446 return __issue_avs_command(priv, AVS_CMD_SET_PMAP, true, args); 447 } 448 449 static int brcm_avs_get_pstate(struct private_data *priv, unsigned int *pstate) 450 { 451 u32 args[AVS_MAX_CMD_ARGS]; 452 int ret; 453 454 ret = __issue_avs_command(priv, AVS_CMD_GET_PSTATE, false, args); 455 if (ret) 456 return ret; 457 *pstate = args[0]; 458 459 return 0; 460 } 461 462 static int brcm_avs_set_pstate(struct private_data *priv, unsigned int pstate) 463 { 464 u32 args[AVS_MAX_CMD_ARGS]; 465 466 args[0] = pstate; 467 468 return __issue_avs_command(priv, AVS_CMD_SET_PSTATE, true, args); 469 } 470 471 static unsigned long brcm_avs_get_voltage(void __iomem *base) 472 { 473 return readl(base + AVS_MBOX_VOLTAGE1); 474 } 475 476 static unsigned long brcm_avs_get_frequency(void __iomem *base) 477 { 478 return readl(base + AVS_MBOX_FREQUENCY) * 1000; /* in kHz */ 479 } 480 481 /* 482 * We determine which frequencies are supported by cycling through all P-states 483 * and reading back what frequency we are running at for each P-state. 484 */ 485 static struct cpufreq_frequency_table * 486 brcm_avs_get_freq_table(struct device *dev, struct private_data *priv) 487 { 488 struct cpufreq_frequency_table *table; 489 unsigned int pstate; 490 int i, ret; 491 492 /* Remember P-state for later */ 493 ret = brcm_avs_get_pstate(priv, &pstate); 494 if (ret) 495 return ERR_PTR(ret); 496 497 table = devm_kzalloc(dev, (AVS_PSTATE_MAX + 1) * sizeof(*table), 498 GFP_KERNEL); 499 if (!table) 500 return ERR_PTR(-ENOMEM); 501 502 for (i = AVS_PSTATE_P0; i <= AVS_PSTATE_MAX; i++) { 503 ret = brcm_avs_set_pstate(priv, i); 504 if (ret) 505 return ERR_PTR(ret); 506 table[i].frequency = brcm_avs_get_frequency(priv->base); 507 table[i].driver_data = i; 508 } 509 table[i].frequency = CPUFREQ_TABLE_END; 510 511 /* Restore P-state */ 512 ret = brcm_avs_set_pstate(priv, pstate); 513 if (ret) 514 return ERR_PTR(ret); 515 516 return table; 517 } 518 519 #ifdef CONFIG_ARM_BRCMSTB_AVS_CPUFREQ_DEBUG 520 521 #define MANT(x) (unsigned int)(abs((x)) / 1000) 522 #define FRAC(x) (unsigned int)(abs((x)) - abs((x)) / 1000 * 1000) 523 524 static int brcm_avs_debug_show(struct seq_file *s, void *data) 525 { 526 struct debugfs_data *dbgfs = s->private; 527 void __iomem *base; 528 u32 val, offset; 529 530 if (!dbgfs) { 531 seq_puts(s, "No device pointer\n"); 532 return 0; 533 } 534 535 base = dbgfs->priv->base; 536 offset = dbgfs->entry->offset; 537 val = readl(base + offset); 538 switch (dbgfs->entry->format) { 539 case DEBUGFS_NORMAL: 540 seq_printf(s, "%u\n", val); 541 break; 542 case DEBUGFS_FLOAT: 543 seq_printf(s, "%d.%03d\n", MANT(val), FRAC(val)); 544 break; 545 case DEBUGFS_REV: 546 seq_printf(s, "%c.%c.%c.%c\n", (val >> 24 & 0xff), 547 (val >> 16 & 0xff), (val >> 8 & 0xff), 548 val & 0xff); 549 break; 550 } 551 seq_printf(s, "0x%08x\n", val); 552 553 return 0; 554 } 555 556 #undef MANT 557 #undef FRAC 558 559 static ssize_t brcm_avs_seq_write(struct file *file, const char __user *buf, 560 size_t size, loff_t *ppos) 561 { 562 struct seq_file *s = file->private_data; 563 struct debugfs_data *dbgfs = s->private; 564 struct private_data *priv = dbgfs->priv; 565 void __iomem *base, *avs_intr_base; 566 bool use_issue_command = false; 567 unsigned long val, offset; 568 char str[128]; 569 int ret; 570 char *str_ptr = str; 571 572 if (size >= sizeof(str)) 573 return -E2BIG; 574 575 memset(str, 0, sizeof(str)); 576 ret = copy_from_user(str, buf, size); 577 if (ret) 578 return ret; 579 580 base = priv->base; 581 avs_intr_base = priv->avs_intr_base; 582 offset = dbgfs->entry->offset; 583 /* 584 * Special case writing to "command" entry only: if the string starts 585 * with a 'c', we use the driver's __issue_avs_command() function. 586 * Otherwise, we perform a raw write. This should allow testing of raw 587 * access as well as using the higher level function. (Raw access 588 * doesn't clear the firmware return status after issuing the command.) 589 */ 590 if (str_ptr[0] == 'c' && offset == AVS_MBOX_COMMAND) { 591 use_issue_command = true; 592 str_ptr++; 593 } 594 if (kstrtoul(str_ptr, 0, &val) != 0) 595 return -EINVAL; 596 597 /* 598 * Setting the P-state is a special case. We need to update the CPU 599 * frequency we report. 600 */ 601 if (val == AVS_CMD_SET_PSTATE) { 602 struct cpufreq_policy *policy; 603 unsigned int pstate; 604 605 policy = cpufreq_cpu_get(smp_processor_id()); 606 /* Read back the P-state we are about to set */ 607 pstate = readl(base + AVS_MBOX_PARAM(0)); 608 if (use_issue_command) { 609 ret = brcm_avs_target_index(policy, pstate); 610 return ret ? ret : size; 611 } 612 policy->cur = policy->freq_table[pstate].frequency; 613 } 614 615 if (use_issue_command) { 616 ret = __issue_avs_command(priv, val, false, NULL); 617 } else { 618 /* Locking here is not perfect, but is only for debug. */ 619 ret = down_interruptible(&priv->sem); 620 if (ret) 621 return ret; 622 623 writel(val, base + offset); 624 /* We have to wake up the firmware to process a command. */ 625 if (offset == AVS_MBOX_COMMAND) 626 writel(AVS_CPU_L2_INT_MASK, 627 avs_intr_base + AVS_CPU_L2_SET0); 628 up(&priv->sem); 629 } 630 631 return ret ? ret : size; 632 } 633 634 static struct debugfs_entry *__find_debugfs_entry(const char *name) 635 { 636 int i; 637 638 for (i = 0; i < ARRAY_SIZE(debugfs_entries); i++) 639 if (strcasecmp(debugfs_entries[i].name, name) == 0) 640 return &debugfs_entries[i]; 641 642 return NULL; 643 } 644 645 static int brcm_avs_debug_open(struct inode *inode, struct file *file) 646 { 647 struct debugfs_data *data; 648 fmode_t fmode; 649 int ret; 650 651 /* 652 * seq_open(), which is called by single_open(), clears "write" access. 653 * We need write access to some files, so we preserve our access mode 654 * and restore it. 655 */ 656 fmode = file->f_mode; 657 /* 658 * Check access permissions even for root. We don't want to be writing 659 * to read-only registers. Access for regular users has already been 660 * checked by the VFS layer. 661 */ 662 if ((fmode & FMODE_WRITER) && !(inode->i_mode & S_IWUSR)) 663 return -EACCES; 664 665 data = kmalloc(sizeof(*data), GFP_KERNEL); 666 if (!data) 667 return -ENOMEM; 668 /* 669 * We use the same file system operations for all our debug files. To 670 * produce specific output, we look up the file name upon opening a 671 * debugfs entry and map it to a memory offset. This offset is then used 672 * in the generic "show" function to read a specific register. 673 */ 674 data->entry = __find_debugfs_entry(file->f_path.dentry->d_iname); 675 data->priv = inode->i_private; 676 677 ret = single_open(file, brcm_avs_debug_show, data); 678 if (ret) 679 kfree(data); 680 file->f_mode = fmode; 681 682 return ret; 683 } 684 685 static int brcm_avs_debug_release(struct inode *inode, struct file *file) 686 { 687 struct seq_file *seq_priv = file->private_data; 688 struct debugfs_data *data = seq_priv->private; 689 690 kfree(data); 691 return single_release(inode, file); 692 } 693 694 static const struct file_operations brcm_avs_debug_ops = { 695 .open = brcm_avs_debug_open, 696 .read = seq_read, 697 .write = brcm_avs_seq_write, 698 .llseek = seq_lseek, 699 .release = brcm_avs_debug_release, 700 }; 701 702 static void brcm_avs_cpufreq_debug_init(struct platform_device *pdev) 703 { 704 struct private_data *priv = platform_get_drvdata(pdev); 705 struct dentry *dir; 706 int i; 707 708 if (!priv) 709 return; 710 711 dir = debugfs_create_dir(BRCM_AVS_CPUFREQ_NAME, NULL); 712 if (IS_ERR_OR_NULL(dir)) 713 return; 714 priv->debugfs = dir; 715 716 for (i = 0; i < ARRAY_SIZE(debugfs_entries); i++) { 717 /* 718 * The DEBUGFS_ENTRY macro generates uppercase strings. We 719 * convert them to lowercase before creating the debugfs 720 * entries. 721 */ 722 char *entry = __strtolower(debugfs_entries[i].name); 723 fmode_t mode = debugfs_entries[i].mode; 724 725 if (!debugfs_create_file(entry, S_IFREG | S_IRUGO | mode, 726 dir, priv, &brcm_avs_debug_ops)) { 727 priv->debugfs = NULL; 728 debugfs_remove_recursive(dir); 729 break; 730 } 731 } 732 } 733 734 static void brcm_avs_cpufreq_debug_exit(struct platform_device *pdev) 735 { 736 struct private_data *priv = platform_get_drvdata(pdev); 737 738 if (priv && priv->debugfs) { 739 debugfs_remove_recursive(priv->debugfs); 740 priv->debugfs = NULL; 741 } 742 } 743 744 #else 745 746 static void brcm_avs_cpufreq_debug_init(struct platform_device *pdev) {} 747 static void brcm_avs_cpufreq_debug_exit(struct platform_device *pdev) {} 748 749 #endif /* CONFIG_ARM_BRCMSTB_AVS_CPUFREQ_DEBUG */ 750 751 /* 752 * To ensure the right firmware is running we need to 753 * - check the MAGIC matches what we expect 754 * - brcm_avs_get_pmap() doesn't return -ENOTSUPP or -EINVAL 755 * We need to set up our interrupt handling before calling brcm_avs_get_pmap()! 756 */ 757 static bool brcm_avs_is_firmware_loaded(struct private_data *priv) 758 { 759 u32 magic; 760 int rc; 761 762 rc = brcm_avs_get_pmap(priv, NULL); 763 magic = readl(priv->base + AVS_MBOX_MAGIC); 764 765 return (magic == AVS_FIRMWARE_MAGIC) && (rc != -ENOTSUPP) && 766 (rc != -EINVAL); 767 } 768 769 static unsigned int brcm_avs_cpufreq_get(unsigned int cpu) 770 { 771 struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); 772 struct private_data *priv = policy->driver_data; 773 774 return brcm_avs_get_frequency(priv->base); 775 } 776 777 static int brcm_avs_target_index(struct cpufreq_policy *policy, 778 unsigned int index) 779 { 780 return brcm_avs_set_pstate(policy->driver_data, 781 policy->freq_table[index].driver_data); 782 } 783 784 static int brcm_avs_suspend(struct cpufreq_policy *policy) 785 { 786 struct private_data *priv = policy->driver_data; 787 788 return brcm_avs_get_pmap(priv, &priv->pmap); 789 } 790 791 static int brcm_avs_resume(struct cpufreq_policy *policy) 792 { 793 struct private_data *priv = policy->driver_data; 794 int ret; 795 796 ret = brcm_avs_set_pmap(priv, &priv->pmap); 797 if (ret == -EEXIST) { 798 struct platform_device *pdev = cpufreq_get_driver_data(); 799 struct device *dev = &pdev->dev; 800 801 dev_warn(dev, "PMAP was already set\n"); 802 ret = 0; 803 } 804 805 return ret; 806 } 807 808 /* 809 * All initialization code that we only want to execute once goes here. Setup 810 * code that can be re-tried on every core (if it failed before) can go into 811 * brcm_avs_cpufreq_init(). 812 */ 813 static int brcm_avs_prepare_init(struct platform_device *pdev) 814 { 815 struct private_data *priv; 816 struct device *dev; 817 int host_irq, ret; 818 819 dev = &pdev->dev; 820 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 821 if (!priv) 822 return -ENOMEM; 823 824 priv->dev = dev; 825 sema_init(&priv->sem, 1); 826 init_completion(&priv->done); 827 platform_set_drvdata(pdev, priv); 828 829 priv->base = __map_region(BRCM_AVS_CPU_DATA); 830 if (!priv->base) { 831 dev_err(dev, "Couldn't find property %s in device tree.\n", 832 BRCM_AVS_CPU_DATA); 833 return -ENOENT; 834 } 835 836 priv->avs_intr_base = __map_region(BRCM_AVS_CPU_INTR); 837 if (!priv->avs_intr_base) { 838 dev_err(dev, "Couldn't find property %s in device tree.\n", 839 BRCM_AVS_CPU_INTR); 840 ret = -ENOENT; 841 goto unmap_base; 842 } 843 844 host_irq = platform_get_irq_byname(pdev, BRCM_AVS_HOST_INTR); 845 if (host_irq < 0) { 846 dev_err(dev, "Couldn't find interrupt %s -- %d\n", 847 BRCM_AVS_HOST_INTR, host_irq); 848 ret = host_irq; 849 goto unmap_intr_base; 850 } 851 852 ret = devm_request_irq(dev, host_irq, irq_handler, IRQF_TRIGGER_RISING, 853 BRCM_AVS_HOST_INTR, priv); 854 if (ret) { 855 dev_err(dev, "IRQ request failed: %s (%d) -- %d\n", 856 BRCM_AVS_HOST_INTR, host_irq, ret); 857 goto unmap_intr_base; 858 } 859 860 if (brcm_avs_is_firmware_loaded(priv)) 861 return 0; 862 863 dev_err(dev, "AVS firmware is not loaded or doesn't support DVFS\n"); 864 ret = -ENODEV; 865 866 unmap_intr_base: 867 iounmap(priv->avs_intr_base); 868 unmap_base: 869 iounmap(priv->base); 870 platform_set_drvdata(pdev, NULL); 871 872 return ret; 873 } 874 875 static int brcm_avs_cpufreq_init(struct cpufreq_policy *policy) 876 { 877 struct cpufreq_frequency_table *freq_table; 878 struct platform_device *pdev; 879 struct private_data *priv; 880 struct device *dev; 881 int ret; 882 883 pdev = cpufreq_get_driver_data(); 884 priv = platform_get_drvdata(pdev); 885 policy->driver_data = priv; 886 dev = &pdev->dev; 887 888 freq_table = brcm_avs_get_freq_table(dev, priv); 889 if (IS_ERR(freq_table)) { 890 ret = PTR_ERR(freq_table); 891 dev_err(dev, "Couldn't determine frequency table (%d).\n", ret); 892 return ret; 893 } 894 895 ret = cpufreq_table_validate_and_show(policy, freq_table); 896 if (ret) { 897 dev_err(dev, "invalid frequency table: %d\n", ret); 898 return ret; 899 } 900 901 /* All cores share the same clock and thus the same policy. */ 902 cpumask_setall(policy->cpus); 903 904 ret = __issue_avs_command(priv, AVS_CMD_ENABLE, false, NULL); 905 if (!ret) { 906 unsigned int pstate; 907 908 ret = brcm_avs_get_pstate(priv, &pstate); 909 if (!ret) { 910 policy->cur = freq_table[pstate].frequency; 911 dev_info(dev, "registered\n"); 912 return 0; 913 } 914 } 915 916 dev_err(dev, "couldn't initialize driver (%d)\n", ret); 917 918 return ret; 919 } 920 921 static ssize_t show_brcm_avs_pstate(struct cpufreq_policy *policy, char *buf) 922 { 923 struct private_data *priv = policy->driver_data; 924 unsigned int pstate; 925 926 if (brcm_avs_get_pstate(priv, &pstate)) 927 return sprintf(buf, "<unknown>\n"); 928 929 return sprintf(buf, "%u\n", pstate); 930 } 931 932 static ssize_t show_brcm_avs_mode(struct cpufreq_policy *policy, char *buf) 933 { 934 struct private_data *priv = policy->driver_data; 935 struct pmap pmap; 936 937 if (brcm_avs_get_pmap(priv, &pmap)) 938 return sprintf(buf, "<unknown>\n"); 939 940 return sprintf(buf, "%s %u\n", brcm_avs_mode_to_string(pmap.mode), 941 pmap.mode); 942 } 943 944 static ssize_t show_brcm_avs_pmap(struct cpufreq_policy *policy, char *buf) 945 { 946 unsigned int mdiv_p0, mdiv_p1, mdiv_p2, mdiv_p3, mdiv_p4; 947 struct private_data *priv = policy->driver_data; 948 unsigned int ndiv, pdiv; 949 struct pmap pmap; 950 951 if (brcm_avs_get_pmap(priv, &pmap)) 952 return sprintf(buf, "<unknown>\n"); 953 954 brcm_avs_parse_p1(pmap.p1, &mdiv_p0, &pdiv, &ndiv); 955 brcm_avs_parse_p2(pmap.p2, &mdiv_p1, &mdiv_p2, &mdiv_p3, &mdiv_p4); 956 957 return sprintf(buf, "0x%08x 0x%08x %u %u %u %u %u %u %u\n", 958 pmap.p1, pmap.p2, ndiv, pdiv, mdiv_p0, mdiv_p1, mdiv_p2, 959 mdiv_p3, mdiv_p4); 960 } 961 962 static ssize_t show_brcm_avs_voltage(struct cpufreq_policy *policy, char *buf) 963 { 964 struct private_data *priv = policy->driver_data; 965 966 return sprintf(buf, "0x%08lx\n", brcm_avs_get_voltage(priv->base)); 967 } 968 969 static ssize_t show_brcm_avs_frequency(struct cpufreq_policy *policy, char *buf) 970 { 971 struct private_data *priv = policy->driver_data; 972 973 return sprintf(buf, "0x%08lx\n", brcm_avs_get_frequency(priv->base)); 974 } 975 976 cpufreq_freq_attr_ro(brcm_avs_pstate); 977 cpufreq_freq_attr_ro(brcm_avs_mode); 978 cpufreq_freq_attr_ro(brcm_avs_pmap); 979 cpufreq_freq_attr_ro(brcm_avs_voltage); 980 cpufreq_freq_attr_ro(brcm_avs_frequency); 981 982 static struct freq_attr *brcm_avs_cpufreq_attr[] = { 983 &cpufreq_freq_attr_scaling_available_freqs, 984 &brcm_avs_pstate, 985 &brcm_avs_mode, 986 &brcm_avs_pmap, 987 &brcm_avs_voltage, 988 &brcm_avs_frequency, 989 NULL 990 }; 991 992 static struct cpufreq_driver brcm_avs_driver = { 993 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, 994 .verify = cpufreq_generic_frequency_table_verify, 995 .target_index = brcm_avs_target_index, 996 .get = brcm_avs_cpufreq_get, 997 .suspend = brcm_avs_suspend, 998 .resume = brcm_avs_resume, 999 .init = brcm_avs_cpufreq_init, 1000 .attr = brcm_avs_cpufreq_attr, 1001 .name = BRCM_AVS_CPUFREQ_PREFIX, 1002 }; 1003 1004 static int brcm_avs_cpufreq_probe(struct platform_device *pdev) 1005 { 1006 int ret; 1007 1008 ret = brcm_avs_prepare_init(pdev); 1009 if (ret) 1010 return ret; 1011 1012 brcm_avs_driver.driver_data = pdev; 1013 ret = cpufreq_register_driver(&brcm_avs_driver); 1014 if (!ret) 1015 brcm_avs_cpufreq_debug_init(pdev); 1016 1017 return ret; 1018 } 1019 1020 static int brcm_avs_cpufreq_remove(struct platform_device *pdev) 1021 { 1022 struct private_data *priv; 1023 int ret; 1024 1025 ret = cpufreq_unregister_driver(&brcm_avs_driver); 1026 if (ret) 1027 return ret; 1028 1029 brcm_avs_cpufreq_debug_exit(pdev); 1030 1031 priv = platform_get_drvdata(pdev); 1032 iounmap(priv->base); 1033 iounmap(priv->avs_intr_base); 1034 platform_set_drvdata(pdev, NULL); 1035 1036 return 0; 1037 } 1038 1039 static const struct of_device_id brcm_avs_cpufreq_match[] = { 1040 { .compatible = BRCM_AVS_CPU_DATA }, 1041 { } 1042 }; 1043 MODULE_DEVICE_TABLE(of, brcm_avs_cpufreq_match); 1044 1045 static struct platform_driver brcm_avs_cpufreq_platdrv = { 1046 .driver = { 1047 .name = BRCM_AVS_CPUFREQ_NAME, 1048 .of_match_table = brcm_avs_cpufreq_match, 1049 }, 1050 .probe = brcm_avs_cpufreq_probe, 1051 .remove = brcm_avs_cpufreq_remove, 1052 }; 1053 module_platform_driver(brcm_avs_cpufreq_platdrv); 1054 1055 MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>"); 1056 MODULE_DESCRIPTION("CPUfreq driver for Broadcom STB AVS"); 1057 MODULE_LICENSE("GPL"); 1058