1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * amd-pstate.c - AMD Processor P-state Frequency Driver 4 * 5 * Copyright (C) 2021 Advanced Micro Devices, Inc. All Rights Reserved. 6 * 7 * Author: Huang Rui <ray.huang@amd.com> 8 * 9 * AMD P-State introduces a new CPU performance scaling design for AMD 10 * processors using the ACPI Collaborative Performance and Power Control (CPPC) 11 * feature which works with the AMD SMU firmware providing a finer grained 12 * frequency control range. It is to replace the legacy ACPI P-States control, 13 * allows a flexible, low-latency interface for the Linux kernel to directly 14 * communicate the performance hints to hardware. 15 * 16 * AMD P-State is supported on recent AMD Zen base CPU series include some of 17 * Zen2 and Zen3 processors. _CPC needs to be present in the ACPI tables of AMD 18 * P-State supported system. And there are two types of hardware implementations 19 * for AMD P-State: 1) Full MSR Solution and 2) Shared Memory Solution. 20 * X86_FEATURE_CPPC CPU feature flag is used to distinguish the different types. 21 */ 22 23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 24 25 #include <linux/bitfield.h> 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/init.h> 29 #include <linux/smp.h> 30 #include <linux/sched.h> 31 #include <linux/cpufreq.h> 32 #include <linux/compiler.h> 33 #include <linux/dmi.h> 34 #include <linux/slab.h> 35 #include <linux/acpi.h> 36 #include <linux/io.h> 37 #include <linux/delay.h> 38 #include <linux/uaccess.h> 39 #include <linux/static_call.h> 40 #include <linux/topology.h> 41 42 #include <acpi/processor.h> 43 #include <acpi/cppc_acpi.h> 44 45 #include <asm/msr.h> 46 #include <asm/processor.h> 47 #include <asm/cpufeature.h> 48 #include <asm/cpu_device_id.h> 49 50 #include "amd-pstate.h" 51 #include "amd-pstate-trace.h" 52 53 #define AMD_PSTATE_TRANSITION_LATENCY 20000 54 #define AMD_PSTATE_TRANSITION_DELAY 1000 55 #define AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY 600 56 57 #define AMD_CPPC_EPP_PERFORMANCE 0x00 58 #define AMD_CPPC_EPP_BALANCE_PERFORMANCE 0x80 59 #define AMD_CPPC_EPP_BALANCE_POWERSAVE 0xBF 60 #define AMD_CPPC_EPP_POWERSAVE 0xFF 61 62 static const char * const amd_pstate_mode_string[] = { 63 [AMD_PSTATE_UNDEFINED] = "undefined", 64 [AMD_PSTATE_DISABLE] = "disable", 65 [AMD_PSTATE_PASSIVE] = "passive", 66 [AMD_PSTATE_ACTIVE] = "active", 67 [AMD_PSTATE_GUIDED] = "guided", 68 NULL, 69 }; 70 71 const char *amd_pstate_get_mode_string(enum amd_pstate_mode mode) 72 { 73 if (mode < 0 || mode >= AMD_PSTATE_MAX) 74 return NULL; 75 return amd_pstate_mode_string[mode]; 76 } 77 EXPORT_SYMBOL_GPL(amd_pstate_get_mode_string); 78 79 struct quirk_entry { 80 u32 nominal_freq; 81 u32 lowest_freq; 82 }; 83 84 static struct cpufreq_driver *current_pstate_driver; 85 static struct cpufreq_driver amd_pstate_driver; 86 static struct cpufreq_driver amd_pstate_epp_driver; 87 static int cppc_state = AMD_PSTATE_UNDEFINED; 88 static bool amd_pstate_prefcore = true; 89 static struct quirk_entry *quirks; 90 91 /* 92 * AMD Energy Preference Performance (EPP) 93 * The EPP is used in the CCLK DPM controller to drive 94 * the frequency that a core is going to operate during 95 * short periods of activity. EPP values will be utilized for 96 * different OS profiles (balanced, performance, power savings) 97 * display strings corresponding to EPP index in the 98 * energy_perf_strings[] 99 * index String 100 *------------------------------------- 101 * 0 default 102 * 1 performance 103 * 2 balance_performance 104 * 3 balance_power 105 * 4 power 106 */ 107 enum energy_perf_value_index { 108 EPP_INDEX_DEFAULT = 0, 109 EPP_INDEX_PERFORMANCE, 110 EPP_INDEX_BALANCE_PERFORMANCE, 111 EPP_INDEX_BALANCE_POWERSAVE, 112 EPP_INDEX_POWERSAVE, 113 }; 114 115 static const char * const energy_perf_strings[] = { 116 [EPP_INDEX_DEFAULT] = "default", 117 [EPP_INDEX_PERFORMANCE] = "performance", 118 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", 119 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", 120 [EPP_INDEX_POWERSAVE] = "power", 121 NULL 122 }; 123 124 static unsigned int epp_values[] = { 125 [EPP_INDEX_DEFAULT] = 0, 126 [EPP_INDEX_PERFORMANCE] = AMD_CPPC_EPP_PERFORMANCE, 127 [EPP_INDEX_BALANCE_PERFORMANCE] = AMD_CPPC_EPP_BALANCE_PERFORMANCE, 128 [EPP_INDEX_BALANCE_POWERSAVE] = AMD_CPPC_EPP_BALANCE_POWERSAVE, 129 [EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_POWERSAVE, 130 }; 131 132 typedef int (*cppc_mode_transition_fn)(int); 133 134 static struct quirk_entry quirk_amd_7k62 = { 135 .nominal_freq = 2600, 136 .lowest_freq = 550, 137 }; 138 139 static inline u8 freq_to_perf(union perf_cached perf, u32 nominal_freq, unsigned int freq_val) 140 { 141 u32 perf_val = DIV_ROUND_UP_ULL((u64)freq_val * perf.nominal_perf, nominal_freq); 142 143 return (u8)clamp(perf_val, perf.lowest_perf, perf.highest_perf); 144 } 145 146 static inline u32 perf_to_freq(union perf_cached perf, u32 nominal_freq, u8 perf_val) 147 { 148 return DIV_ROUND_UP_ULL((u64)nominal_freq * perf_val, 149 perf.nominal_perf); 150 } 151 152 static int __init dmi_matched_7k62_bios_bug(const struct dmi_system_id *dmi) 153 { 154 /** 155 * match the broken bios for family 17h processor support CPPC V2 156 * broken BIOS lack of nominal_freq and lowest_freq capabilities 157 * definition in ACPI tables 158 */ 159 if (cpu_feature_enabled(X86_FEATURE_ZEN2)) { 160 quirks = dmi->driver_data; 161 pr_info("Overriding nominal and lowest frequencies for %s\n", dmi->ident); 162 return 1; 163 } 164 165 return 0; 166 } 167 168 static const struct dmi_system_id amd_pstate_quirks_table[] __initconst = { 169 { 170 .callback = dmi_matched_7k62_bios_bug, 171 .ident = "AMD EPYC 7K62", 172 .matches = { 173 DMI_MATCH(DMI_BIOS_VERSION, "5.14"), 174 DMI_MATCH(DMI_BIOS_RELEASE, "12/12/2019"), 175 }, 176 .driver_data = &quirk_amd_7k62, 177 }, 178 {} 179 }; 180 MODULE_DEVICE_TABLE(dmi, amd_pstate_quirks_table); 181 182 static inline int get_mode_idx_from_str(const char *str, size_t size) 183 { 184 int i; 185 186 for (i=0; i < AMD_PSTATE_MAX; i++) { 187 if (!strncmp(str, amd_pstate_mode_string[i], size)) 188 return i; 189 } 190 return -EINVAL; 191 } 192 193 static DEFINE_MUTEX(amd_pstate_driver_lock); 194 195 static u8 msr_get_epp(struct amd_cpudata *cpudata) 196 { 197 u64 value; 198 int ret; 199 200 ret = rdmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); 201 if (ret < 0) { 202 pr_debug("Could not retrieve energy perf value (%d)\n", ret); 203 return ret; 204 } 205 206 return FIELD_GET(AMD_CPPC_EPP_PERF_MASK, value); 207 } 208 209 DEFINE_STATIC_CALL(amd_pstate_get_epp, msr_get_epp); 210 211 static inline s16 amd_pstate_get_epp(struct amd_cpudata *cpudata) 212 { 213 return static_call(amd_pstate_get_epp)(cpudata); 214 } 215 216 static u8 shmem_get_epp(struct amd_cpudata *cpudata) 217 { 218 u64 epp; 219 int ret; 220 221 ret = cppc_get_epp_perf(cpudata->cpu, &epp); 222 if (ret < 0) { 223 pr_debug("Could not retrieve energy perf value (%d)\n", ret); 224 return ret; 225 } 226 227 return FIELD_GET(AMD_CPPC_EPP_PERF_MASK, epp); 228 } 229 230 static int msr_update_perf(struct cpufreq_policy *policy, u8 min_perf, 231 u8 des_perf, u8 max_perf, u8 epp, bool fast_switch) 232 { 233 struct amd_cpudata *cpudata = policy->driver_data; 234 u64 value, prev; 235 236 value = prev = READ_ONCE(cpudata->cppc_req_cached); 237 238 value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | 239 AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK); 240 value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); 241 value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf); 242 value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); 243 value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); 244 245 if (trace_amd_pstate_epp_perf_enabled()) { 246 union perf_cached perf = READ_ONCE(cpudata->perf); 247 248 trace_amd_pstate_epp_perf(cpudata->cpu, 249 perf.highest_perf, 250 epp, 251 min_perf, 252 max_perf, 253 policy->boost_enabled, 254 value != prev); 255 } 256 257 if (value == prev) 258 return 0; 259 260 if (fast_switch) { 261 wrmsrq(MSR_AMD_CPPC_REQ, value); 262 return 0; 263 } else { 264 int ret = wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); 265 266 if (ret) 267 return ret; 268 } 269 270 WRITE_ONCE(cpudata->cppc_req_cached, value); 271 272 return 0; 273 } 274 275 DEFINE_STATIC_CALL(amd_pstate_update_perf, msr_update_perf); 276 277 static inline int amd_pstate_update_perf(struct cpufreq_policy *policy, 278 u8 min_perf, u8 des_perf, 279 u8 max_perf, u8 epp, 280 bool fast_switch) 281 { 282 return static_call(amd_pstate_update_perf)(policy, min_perf, des_perf, 283 max_perf, epp, fast_switch); 284 } 285 286 static int msr_set_epp(struct cpufreq_policy *policy, u8 epp) 287 { 288 struct amd_cpudata *cpudata = policy->driver_data; 289 u64 value, prev; 290 int ret; 291 292 value = prev = READ_ONCE(cpudata->cppc_req_cached); 293 value &= ~AMD_CPPC_EPP_PERF_MASK; 294 value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); 295 296 if (trace_amd_pstate_epp_perf_enabled()) { 297 union perf_cached perf = cpudata->perf; 298 299 trace_amd_pstate_epp_perf(cpudata->cpu, perf.highest_perf, 300 epp, 301 FIELD_GET(AMD_CPPC_MIN_PERF_MASK, 302 cpudata->cppc_req_cached), 303 FIELD_GET(AMD_CPPC_MAX_PERF_MASK, 304 cpudata->cppc_req_cached), 305 policy->boost_enabled, 306 value != prev); 307 } 308 309 if (value == prev) 310 return 0; 311 312 ret = wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); 313 if (ret) { 314 pr_err("failed to set energy perf value (%d)\n", ret); 315 return ret; 316 } 317 318 /* update both so that msr_update_perf() can effectively check */ 319 WRITE_ONCE(cpudata->cppc_req_cached, value); 320 321 return ret; 322 } 323 324 DEFINE_STATIC_CALL(amd_pstate_set_epp, msr_set_epp); 325 326 static inline int amd_pstate_set_epp(struct cpufreq_policy *policy, u8 epp) 327 { 328 return static_call(amd_pstate_set_epp)(policy, epp); 329 } 330 331 static int shmem_set_epp(struct cpufreq_policy *policy, u8 epp) 332 { 333 struct amd_cpudata *cpudata = policy->driver_data; 334 struct cppc_perf_ctrls perf_ctrls; 335 u8 epp_cached; 336 u64 value; 337 int ret; 338 339 340 epp_cached = FIELD_GET(AMD_CPPC_EPP_PERF_MASK, cpudata->cppc_req_cached); 341 if (trace_amd_pstate_epp_perf_enabled()) { 342 union perf_cached perf = cpudata->perf; 343 344 trace_amd_pstate_epp_perf(cpudata->cpu, perf.highest_perf, 345 epp, 346 FIELD_GET(AMD_CPPC_MIN_PERF_MASK, 347 cpudata->cppc_req_cached), 348 FIELD_GET(AMD_CPPC_MAX_PERF_MASK, 349 cpudata->cppc_req_cached), 350 policy->boost_enabled, 351 epp != epp_cached); 352 } 353 354 if (epp == epp_cached) 355 return 0; 356 357 perf_ctrls.energy_perf = epp; 358 ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); 359 if (ret) { 360 pr_debug("failed to set energy perf value (%d)\n", ret); 361 return ret; 362 } 363 364 value = READ_ONCE(cpudata->cppc_req_cached); 365 value &= ~AMD_CPPC_EPP_PERF_MASK; 366 value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); 367 WRITE_ONCE(cpudata->cppc_req_cached, value); 368 369 return ret; 370 } 371 372 static inline int msr_cppc_enable(struct cpufreq_policy *policy) 373 { 374 return wrmsrq_safe_on_cpu(policy->cpu, MSR_AMD_CPPC_ENABLE, 1); 375 } 376 377 static int shmem_cppc_enable(struct cpufreq_policy *policy) 378 { 379 return cppc_set_enable(policy->cpu, 1); 380 } 381 382 DEFINE_STATIC_CALL(amd_pstate_cppc_enable, msr_cppc_enable); 383 384 static inline int amd_pstate_cppc_enable(struct cpufreq_policy *policy) 385 { 386 return static_call(amd_pstate_cppc_enable)(policy); 387 } 388 389 static int msr_init_perf(struct amd_cpudata *cpudata) 390 { 391 union perf_cached perf = READ_ONCE(cpudata->perf); 392 u64 cap1, numerator; 393 394 int ret = rdmsrq_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, 395 &cap1); 396 if (ret) 397 return ret; 398 399 ret = amd_get_boost_ratio_numerator(cpudata->cpu, &numerator); 400 if (ret) 401 return ret; 402 403 perf.highest_perf = numerator; 404 perf.max_limit_perf = numerator; 405 perf.min_limit_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1); 406 perf.nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1); 407 perf.lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1); 408 perf.lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1); 409 WRITE_ONCE(cpudata->perf, perf); 410 WRITE_ONCE(cpudata->prefcore_ranking, FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1)); 411 412 return 0; 413 } 414 415 static int shmem_init_perf(struct amd_cpudata *cpudata) 416 { 417 struct cppc_perf_caps cppc_perf; 418 union perf_cached perf = READ_ONCE(cpudata->perf); 419 u64 numerator; 420 421 int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); 422 if (ret) 423 return ret; 424 425 ret = amd_get_boost_ratio_numerator(cpudata->cpu, &numerator); 426 if (ret) 427 return ret; 428 429 perf.highest_perf = numerator; 430 perf.max_limit_perf = numerator; 431 perf.min_limit_perf = cppc_perf.lowest_perf; 432 perf.nominal_perf = cppc_perf.nominal_perf; 433 perf.lowest_nonlinear_perf = cppc_perf.lowest_nonlinear_perf; 434 perf.lowest_perf = cppc_perf.lowest_perf; 435 WRITE_ONCE(cpudata->perf, perf); 436 WRITE_ONCE(cpudata->prefcore_ranking, cppc_perf.highest_perf); 437 438 if (cppc_state == AMD_PSTATE_ACTIVE) 439 return 0; 440 441 ret = cppc_get_auto_sel_caps(cpudata->cpu, &cppc_perf); 442 if (ret) { 443 pr_warn("failed to get auto_sel, ret: %d\n", ret); 444 return 0; 445 } 446 447 ret = cppc_set_auto_sel(cpudata->cpu, 448 (cppc_state == AMD_PSTATE_PASSIVE) ? 0 : 1); 449 450 if (ret) 451 pr_warn("failed to set auto_sel, ret: %d\n", ret); 452 453 return ret; 454 } 455 456 DEFINE_STATIC_CALL(amd_pstate_init_perf, msr_init_perf); 457 458 static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata) 459 { 460 return static_call(amd_pstate_init_perf)(cpudata); 461 } 462 463 static int shmem_update_perf(struct cpufreq_policy *policy, u8 min_perf, 464 u8 des_perf, u8 max_perf, u8 epp, bool fast_switch) 465 { 466 struct amd_cpudata *cpudata = policy->driver_data; 467 struct cppc_perf_ctrls perf_ctrls; 468 u64 value, prev; 469 int ret; 470 471 if (cppc_state == AMD_PSTATE_ACTIVE) { 472 int ret = shmem_set_epp(policy, epp); 473 474 if (ret) 475 return ret; 476 } 477 478 value = prev = READ_ONCE(cpudata->cppc_req_cached); 479 480 value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | 481 AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK); 482 value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); 483 value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf); 484 value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); 485 value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); 486 487 if (trace_amd_pstate_epp_perf_enabled()) { 488 union perf_cached perf = READ_ONCE(cpudata->perf); 489 490 trace_amd_pstate_epp_perf(cpudata->cpu, 491 perf.highest_perf, 492 epp, 493 min_perf, 494 max_perf, 495 policy->boost_enabled, 496 value != prev); 497 } 498 499 if (value == prev) 500 return 0; 501 502 perf_ctrls.max_perf = max_perf; 503 perf_ctrls.min_perf = min_perf; 504 perf_ctrls.desired_perf = des_perf; 505 506 ret = cppc_set_perf(cpudata->cpu, &perf_ctrls); 507 if (ret) 508 return ret; 509 510 WRITE_ONCE(cpudata->cppc_req_cached, value); 511 512 return 0; 513 } 514 515 static inline bool amd_pstate_sample(struct amd_cpudata *cpudata) 516 { 517 u64 aperf, mperf, tsc; 518 unsigned long flags; 519 520 local_irq_save(flags); 521 rdmsrq(MSR_IA32_APERF, aperf); 522 rdmsrq(MSR_IA32_MPERF, mperf); 523 tsc = rdtsc(); 524 525 if (cpudata->prev.mperf == mperf || cpudata->prev.tsc == tsc) { 526 local_irq_restore(flags); 527 return false; 528 } 529 530 local_irq_restore(flags); 531 532 cpudata->cur.aperf = aperf; 533 cpudata->cur.mperf = mperf; 534 cpudata->cur.tsc = tsc; 535 cpudata->cur.aperf -= cpudata->prev.aperf; 536 cpudata->cur.mperf -= cpudata->prev.mperf; 537 cpudata->cur.tsc -= cpudata->prev.tsc; 538 539 cpudata->prev.aperf = aperf; 540 cpudata->prev.mperf = mperf; 541 cpudata->prev.tsc = tsc; 542 543 cpudata->freq = div64_u64((cpudata->cur.aperf * cpu_khz), cpudata->cur.mperf); 544 545 return true; 546 } 547 548 static void amd_pstate_update(struct amd_cpudata *cpudata, u8 min_perf, 549 u8 des_perf, u8 max_perf, bool fast_switch, int gov_flags) 550 { 551 struct cpufreq_policy *policy __free(put_cpufreq_policy) = cpufreq_cpu_get(cpudata->cpu); 552 union perf_cached perf = READ_ONCE(cpudata->perf); 553 554 if (!policy) 555 return; 556 557 des_perf = clamp_t(u8, des_perf, min_perf, max_perf); 558 559 policy->cur = perf_to_freq(perf, cpudata->nominal_freq, des_perf); 560 561 if ((cppc_state == AMD_PSTATE_GUIDED) && (gov_flags & CPUFREQ_GOV_DYNAMIC_SWITCHING)) { 562 min_perf = des_perf; 563 des_perf = 0; 564 } 565 566 /* limit the max perf when core performance boost feature is disabled */ 567 if (!cpudata->boost_supported) 568 max_perf = min_t(u8, perf.nominal_perf, max_perf); 569 570 if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) { 571 trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq, 572 cpudata->cur.mperf, cpudata->cur.aperf, cpudata->cur.tsc, 573 cpudata->cpu, fast_switch); 574 } 575 576 amd_pstate_update_perf(policy, min_perf, des_perf, max_perf, 0, fast_switch); 577 } 578 579 static int amd_pstate_verify(struct cpufreq_policy_data *policy_data) 580 { 581 /* 582 * Initialize lower frequency limit (i.e.policy->min) with 583 * lowest_nonlinear_frequency which is the most energy efficient 584 * frequency. Override the initial value set by cpufreq core and 585 * amd-pstate qos_requests. 586 */ 587 if (policy_data->min == FREQ_QOS_MIN_DEFAULT_VALUE) { 588 struct cpufreq_policy *policy __free(put_cpufreq_policy) = 589 cpufreq_cpu_get(policy_data->cpu); 590 struct amd_cpudata *cpudata; 591 592 if (!policy) 593 return -EINVAL; 594 595 cpudata = policy->driver_data; 596 policy_data->min = cpudata->lowest_nonlinear_freq; 597 } 598 599 cpufreq_verify_within_cpu_limits(policy_data); 600 601 return 0; 602 } 603 604 static void amd_pstate_update_min_max_limit(struct cpufreq_policy *policy) 605 { 606 struct amd_cpudata *cpudata = policy->driver_data; 607 union perf_cached perf = READ_ONCE(cpudata->perf); 608 609 perf.max_limit_perf = freq_to_perf(perf, cpudata->nominal_freq, policy->max); 610 WRITE_ONCE(cpudata->max_limit_freq, policy->max); 611 612 if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) { 613 perf.min_limit_perf = min(perf.nominal_perf, perf.max_limit_perf); 614 WRITE_ONCE(cpudata->min_limit_freq, min(cpudata->nominal_freq, cpudata->max_limit_freq)); 615 } else { 616 perf.min_limit_perf = freq_to_perf(perf, cpudata->nominal_freq, policy->min); 617 WRITE_ONCE(cpudata->min_limit_freq, policy->min); 618 } 619 620 WRITE_ONCE(cpudata->perf, perf); 621 } 622 623 static int amd_pstate_update_freq(struct cpufreq_policy *policy, 624 unsigned int target_freq, bool fast_switch) 625 { 626 struct cpufreq_freqs freqs; 627 struct amd_cpudata *cpudata; 628 union perf_cached perf; 629 u8 des_perf; 630 631 cpudata = policy->driver_data; 632 633 if (policy->min != cpudata->min_limit_freq || policy->max != cpudata->max_limit_freq) 634 amd_pstate_update_min_max_limit(policy); 635 636 perf = READ_ONCE(cpudata->perf); 637 638 freqs.old = policy->cur; 639 freqs.new = target_freq; 640 641 des_perf = freq_to_perf(perf, cpudata->nominal_freq, target_freq); 642 643 WARN_ON(fast_switch && !policy->fast_switch_enabled); 644 /* 645 * If fast_switch is desired, then there aren't any registered 646 * transition notifiers. See comment for 647 * cpufreq_enable_fast_switch(). 648 */ 649 if (!fast_switch) 650 cpufreq_freq_transition_begin(policy, &freqs); 651 652 amd_pstate_update(cpudata, perf.min_limit_perf, des_perf, 653 perf.max_limit_perf, fast_switch, 654 policy->governor->flags); 655 656 if (!fast_switch) 657 cpufreq_freq_transition_end(policy, &freqs, false); 658 659 return 0; 660 } 661 662 static int amd_pstate_target(struct cpufreq_policy *policy, 663 unsigned int target_freq, 664 unsigned int relation) 665 { 666 return amd_pstate_update_freq(policy, target_freq, false); 667 } 668 669 static unsigned int amd_pstate_fast_switch(struct cpufreq_policy *policy, 670 unsigned int target_freq) 671 { 672 if (!amd_pstate_update_freq(policy, target_freq, true)) 673 return target_freq; 674 return policy->cur; 675 } 676 677 static void amd_pstate_adjust_perf(unsigned int cpu, 678 unsigned long _min_perf, 679 unsigned long target_perf, 680 unsigned long capacity) 681 { 682 u8 max_perf, min_perf, des_perf, cap_perf; 683 struct cpufreq_policy *policy __free(put_cpufreq_policy) = cpufreq_cpu_get(cpu); 684 struct amd_cpudata *cpudata; 685 union perf_cached perf; 686 687 if (!policy) 688 return; 689 690 cpudata = policy->driver_data; 691 692 if (policy->min != cpudata->min_limit_freq || policy->max != cpudata->max_limit_freq) 693 amd_pstate_update_min_max_limit(policy); 694 695 perf = READ_ONCE(cpudata->perf); 696 cap_perf = perf.highest_perf; 697 698 des_perf = cap_perf; 699 if (target_perf < capacity) 700 des_perf = DIV_ROUND_UP(cap_perf * target_perf, capacity); 701 702 if (_min_perf < capacity) 703 min_perf = DIV_ROUND_UP(cap_perf * _min_perf, capacity); 704 else 705 min_perf = cap_perf; 706 707 if (min_perf < perf.min_limit_perf) 708 min_perf = perf.min_limit_perf; 709 710 max_perf = perf.max_limit_perf; 711 if (max_perf < min_perf) 712 max_perf = min_perf; 713 714 amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true, 715 policy->governor->flags); 716 } 717 718 static int amd_pstate_cpu_boost_update(struct cpufreq_policy *policy, bool on) 719 { 720 struct amd_cpudata *cpudata = policy->driver_data; 721 union perf_cached perf = READ_ONCE(cpudata->perf); 722 u32 nominal_freq, max_freq; 723 int ret = 0; 724 725 nominal_freq = READ_ONCE(cpudata->nominal_freq); 726 max_freq = perf_to_freq(perf, cpudata->nominal_freq, perf.highest_perf); 727 728 if (on) 729 policy->cpuinfo.max_freq = max_freq; 730 else if (policy->cpuinfo.max_freq > nominal_freq) 731 policy->cpuinfo.max_freq = nominal_freq; 732 733 policy->max = policy->cpuinfo.max_freq; 734 735 if (cppc_state == AMD_PSTATE_PASSIVE) { 736 ret = freq_qos_update_request(&cpudata->req[1], policy->cpuinfo.max_freq); 737 if (ret < 0) 738 pr_debug("Failed to update freq constraint: CPU%d\n", cpudata->cpu); 739 } 740 741 return ret < 0 ? ret : 0; 742 } 743 744 static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) 745 { 746 struct amd_cpudata *cpudata = policy->driver_data; 747 int ret; 748 749 if (!cpudata->boost_supported) { 750 pr_err("Boost mode is not supported by this processor or SBIOS\n"); 751 return -EOPNOTSUPP; 752 } 753 754 ret = amd_pstate_cpu_boost_update(policy, state); 755 refresh_frequency_limits(policy); 756 757 return ret; 758 } 759 760 static int amd_pstate_init_boost_support(struct amd_cpudata *cpudata) 761 { 762 u64 boost_val; 763 int ret = -1; 764 765 /* 766 * If platform has no CPB support or disable it, initialize current driver 767 * boost_enabled state to be false, it is not an error for cpufreq core to handle. 768 */ 769 if (!cpu_feature_enabled(X86_FEATURE_CPB)) { 770 pr_debug_once("Boost CPB capabilities not present in the processor\n"); 771 ret = 0; 772 goto exit_err; 773 } 774 775 ret = rdmsrq_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); 776 if (ret) { 777 pr_err_once("failed to read initial CPU boost state!\n"); 778 ret = -EIO; 779 goto exit_err; 780 } 781 782 if (!(boost_val & MSR_K7_HWCR_CPB_DIS)) 783 cpudata->boost_supported = true; 784 785 return 0; 786 787 exit_err: 788 cpudata->boost_supported = false; 789 return ret; 790 } 791 792 static void amd_perf_ctl_reset(unsigned int cpu) 793 { 794 wrmsrq_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); 795 } 796 797 #define CPPC_MAX_PERF U8_MAX 798 799 static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) 800 { 801 /* user disabled or not detected */ 802 if (!amd_pstate_prefcore) 803 return; 804 805 cpudata->hw_prefcore = true; 806 807 /* Priorities must be initialized before ITMT support can be toggled on. */ 808 sched_set_itmt_core_prio((int)READ_ONCE(cpudata->prefcore_ranking), cpudata->cpu); 809 } 810 811 static void amd_pstate_update_limits(unsigned int cpu) 812 { 813 struct cpufreq_policy *policy __free(put_cpufreq_policy) = cpufreq_cpu_get(cpu); 814 struct amd_cpudata *cpudata; 815 u32 prev_high = 0, cur_high = 0; 816 bool highest_perf_changed = false; 817 818 if (!amd_pstate_prefcore) 819 return; 820 821 if (!policy) 822 return; 823 824 if (amd_get_highest_perf(cpu, &cur_high)) 825 return; 826 827 cpudata = policy->driver_data; 828 829 prev_high = READ_ONCE(cpudata->prefcore_ranking); 830 highest_perf_changed = (prev_high != cur_high); 831 if (highest_perf_changed) { 832 WRITE_ONCE(cpudata->prefcore_ranking, cur_high); 833 834 if (cur_high < CPPC_MAX_PERF) { 835 sched_set_itmt_core_prio((int)cur_high, cpu); 836 sched_update_asym_prefer_cpu(cpu, prev_high, cur_high); 837 } 838 } 839 } 840 841 /* 842 * Get pstate transition delay time from ACPI tables that firmware set 843 * instead of using hardcode value directly. 844 */ 845 static u32 amd_pstate_get_transition_delay_us(unsigned int cpu) 846 { 847 u32 transition_delay_ns; 848 849 transition_delay_ns = cppc_get_transition_latency(cpu); 850 if (transition_delay_ns == CPUFREQ_ETERNAL) { 851 if (cpu_feature_enabled(X86_FEATURE_AMD_FAST_CPPC)) 852 return AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY; 853 else 854 return AMD_PSTATE_TRANSITION_DELAY; 855 } 856 857 return transition_delay_ns / NSEC_PER_USEC; 858 } 859 860 /* 861 * Get pstate transition latency value from ACPI tables that firmware 862 * set instead of using hardcode value directly. 863 */ 864 static u32 amd_pstate_get_transition_latency(unsigned int cpu) 865 { 866 u32 transition_latency; 867 868 transition_latency = cppc_get_transition_latency(cpu); 869 if (transition_latency == CPUFREQ_ETERNAL) 870 return AMD_PSTATE_TRANSITION_LATENCY; 871 872 return transition_latency; 873 } 874 875 /* 876 * amd_pstate_init_freq: Initialize the nominal_freq and lowest_nonlinear_freq 877 * for the @cpudata object. 878 * 879 * Requires: all perf members of @cpudata to be initialized. 880 * 881 * Returns 0 on success, non-zero value on failure. 882 */ 883 static int amd_pstate_init_freq(struct amd_cpudata *cpudata) 884 { 885 u32 min_freq, max_freq, nominal_freq, lowest_nonlinear_freq; 886 struct cppc_perf_caps cppc_perf; 887 union perf_cached perf; 888 int ret; 889 890 ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); 891 if (ret) 892 return ret; 893 perf = READ_ONCE(cpudata->perf); 894 895 if (quirks && quirks->nominal_freq) 896 nominal_freq = quirks->nominal_freq; 897 else 898 nominal_freq = cppc_perf.nominal_freq; 899 nominal_freq *= 1000; 900 901 if (quirks && quirks->lowest_freq) { 902 min_freq = quirks->lowest_freq; 903 perf.lowest_perf = freq_to_perf(perf, nominal_freq, min_freq); 904 WRITE_ONCE(cpudata->perf, perf); 905 } else 906 min_freq = cppc_perf.lowest_freq; 907 908 min_freq *= 1000; 909 910 WRITE_ONCE(cpudata->nominal_freq, nominal_freq); 911 912 max_freq = perf_to_freq(perf, nominal_freq, perf.highest_perf); 913 lowest_nonlinear_freq = perf_to_freq(perf, nominal_freq, perf.lowest_nonlinear_perf); 914 WRITE_ONCE(cpudata->lowest_nonlinear_freq, lowest_nonlinear_freq); 915 916 /** 917 * Below values need to be initialized correctly, otherwise driver will fail to load 918 * max_freq is calculated according to (nominal_freq * highest_perf)/nominal_perf 919 * lowest_nonlinear_freq is a value between [min_freq, nominal_freq] 920 * Check _CPC in ACPI table objects if any values are incorrect 921 */ 922 if (min_freq <= 0 || max_freq <= 0 || nominal_freq <= 0 || min_freq > max_freq) { 923 pr_err("min_freq(%d) or max_freq(%d) or nominal_freq(%d) value is incorrect\n", 924 min_freq, max_freq, nominal_freq); 925 return -EINVAL; 926 } 927 928 if (lowest_nonlinear_freq <= min_freq || lowest_nonlinear_freq > nominal_freq) { 929 pr_err("lowest_nonlinear_freq(%d) value is out of range [min_freq(%d), nominal_freq(%d)]\n", 930 lowest_nonlinear_freq, min_freq, nominal_freq); 931 return -EINVAL; 932 } 933 934 return 0; 935 } 936 937 static int amd_pstate_cpu_init(struct cpufreq_policy *policy) 938 { 939 struct amd_cpudata *cpudata; 940 union perf_cached perf; 941 struct device *dev; 942 int ret; 943 944 /* 945 * Resetting PERF_CTL_MSR will put the CPU in P0 frequency, 946 * which is ideal for initialization process. 947 */ 948 amd_perf_ctl_reset(policy->cpu); 949 dev = get_cpu_device(policy->cpu); 950 if (!dev) 951 return -ENODEV; 952 953 cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL); 954 if (!cpudata) 955 return -ENOMEM; 956 957 cpudata->cpu = policy->cpu; 958 959 ret = amd_pstate_init_perf(cpudata); 960 if (ret) 961 goto free_cpudata1; 962 963 amd_pstate_init_prefcore(cpudata); 964 965 ret = amd_pstate_init_freq(cpudata); 966 if (ret) 967 goto free_cpudata1; 968 969 ret = amd_pstate_init_boost_support(cpudata); 970 if (ret) 971 goto free_cpudata1; 972 973 policy->cpuinfo.transition_latency = amd_pstate_get_transition_latency(policy->cpu); 974 policy->transition_delay_us = amd_pstate_get_transition_delay_us(policy->cpu); 975 976 perf = READ_ONCE(cpudata->perf); 977 978 policy->cpuinfo.min_freq = policy->min = perf_to_freq(perf, 979 cpudata->nominal_freq, 980 perf.lowest_perf); 981 policy->cpuinfo.max_freq = policy->max = perf_to_freq(perf, 982 cpudata->nominal_freq, 983 perf.highest_perf); 984 985 ret = amd_pstate_cppc_enable(policy); 986 if (ret) 987 goto free_cpudata1; 988 989 policy->boost_supported = READ_ONCE(cpudata->boost_supported); 990 991 /* It will be updated by governor */ 992 policy->cur = policy->cpuinfo.min_freq; 993 994 if (cpu_feature_enabled(X86_FEATURE_CPPC)) 995 policy->fast_switch_possible = true; 996 997 ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], 998 FREQ_QOS_MIN, FREQ_QOS_MIN_DEFAULT_VALUE); 999 if (ret < 0) { 1000 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret); 1001 goto free_cpudata1; 1002 } 1003 1004 ret = freq_qos_add_request(&policy->constraints, &cpudata->req[1], 1005 FREQ_QOS_MAX, policy->cpuinfo.max_freq); 1006 if (ret < 0) { 1007 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret); 1008 goto free_cpudata2; 1009 } 1010 1011 policy->driver_data = cpudata; 1012 1013 if (!current_pstate_driver->adjust_perf) 1014 current_pstate_driver->adjust_perf = amd_pstate_adjust_perf; 1015 1016 return 0; 1017 1018 free_cpudata2: 1019 freq_qos_remove_request(&cpudata->req[0]); 1020 free_cpudata1: 1021 pr_warn("Failed to initialize CPU %d: %d\n", policy->cpu, ret); 1022 kfree(cpudata); 1023 return ret; 1024 } 1025 1026 static void amd_pstate_cpu_exit(struct cpufreq_policy *policy) 1027 { 1028 struct amd_cpudata *cpudata = policy->driver_data; 1029 1030 freq_qos_remove_request(&cpudata->req[1]); 1031 freq_qos_remove_request(&cpudata->req[0]); 1032 policy->fast_switch_possible = false; 1033 kfree(cpudata); 1034 } 1035 1036 /* Sysfs attributes */ 1037 1038 /* 1039 * This frequency is to indicate the maximum hardware frequency. 1040 * If boost is not active but supported, the frequency will be larger than the 1041 * one in cpuinfo. 1042 */ 1043 static ssize_t show_amd_pstate_max_freq(struct cpufreq_policy *policy, 1044 char *buf) 1045 { 1046 struct amd_cpudata *cpudata; 1047 union perf_cached perf; 1048 1049 cpudata = policy->driver_data; 1050 perf = READ_ONCE(cpudata->perf); 1051 1052 return sysfs_emit(buf, "%u\n", 1053 perf_to_freq(perf, cpudata->nominal_freq, perf.highest_perf)); 1054 } 1055 1056 static ssize_t show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *policy, 1057 char *buf) 1058 { 1059 struct amd_cpudata *cpudata; 1060 union perf_cached perf; 1061 1062 cpudata = policy->driver_data; 1063 perf = READ_ONCE(cpudata->perf); 1064 1065 return sysfs_emit(buf, "%u\n", 1066 perf_to_freq(perf, cpudata->nominal_freq, perf.lowest_nonlinear_perf)); 1067 } 1068 1069 /* 1070 * In some of ASICs, the highest_perf is not the one in the _CPC table, so we 1071 * need to expose it to sysfs. 1072 */ 1073 static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, 1074 char *buf) 1075 { 1076 struct amd_cpudata *cpudata; 1077 1078 cpudata = policy->driver_data; 1079 1080 return sysfs_emit(buf, "%u\n", cpudata->perf.highest_perf); 1081 } 1082 1083 static ssize_t show_amd_pstate_prefcore_ranking(struct cpufreq_policy *policy, 1084 char *buf) 1085 { 1086 u8 perf; 1087 struct amd_cpudata *cpudata = policy->driver_data; 1088 1089 perf = READ_ONCE(cpudata->prefcore_ranking); 1090 1091 return sysfs_emit(buf, "%u\n", perf); 1092 } 1093 1094 static ssize_t show_amd_pstate_hw_prefcore(struct cpufreq_policy *policy, 1095 char *buf) 1096 { 1097 bool hw_prefcore; 1098 struct amd_cpudata *cpudata = policy->driver_data; 1099 1100 hw_prefcore = READ_ONCE(cpudata->hw_prefcore); 1101 1102 return sysfs_emit(buf, "%s\n", str_enabled_disabled(hw_prefcore)); 1103 } 1104 1105 static ssize_t show_energy_performance_available_preferences( 1106 struct cpufreq_policy *policy, char *buf) 1107 { 1108 int i = 0; 1109 int offset = 0; 1110 struct amd_cpudata *cpudata = policy->driver_data; 1111 1112 if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) 1113 return sysfs_emit_at(buf, offset, "%s\n", 1114 energy_perf_strings[EPP_INDEX_PERFORMANCE]); 1115 1116 while (energy_perf_strings[i] != NULL) 1117 offset += sysfs_emit_at(buf, offset, "%s ", energy_perf_strings[i++]); 1118 1119 offset += sysfs_emit_at(buf, offset, "\n"); 1120 1121 return offset; 1122 } 1123 1124 static ssize_t store_energy_performance_preference( 1125 struct cpufreq_policy *policy, const char *buf, size_t count) 1126 { 1127 struct amd_cpudata *cpudata = policy->driver_data; 1128 char str_preference[21]; 1129 ssize_t ret; 1130 u8 epp; 1131 1132 ret = sscanf(buf, "%20s", str_preference); 1133 if (ret != 1) 1134 return -EINVAL; 1135 1136 ret = match_string(energy_perf_strings, -1, str_preference); 1137 if (ret < 0) 1138 return -EINVAL; 1139 1140 if (!ret) 1141 epp = cpudata->epp_default; 1142 else 1143 epp = epp_values[ret]; 1144 1145 if (epp > 0 && policy->policy == CPUFREQ_POLICY_PERFORMANCE) { 1146 pr_debug("EPP cannot be set under performance policy\n"); 1147 return -EBUSY; 1148 } 1149 1150 ret = amd_pstate_set_epp(policy, epp); 1151 1152 return ret ? ret : count; 1153 } 1154 1155 static ssize_t show_energy_performance_preference( 1156 struct cpufreq_policy *policy, char *buf) 1157 { 1158 struct amd_cpudata *cpudata = policy->driver_data; 1159 u8 preference, epp; 1160 1161 epp = FIELD_GET(AMD_CPPC_EPP_PERF_MASK, cpudata->cppc_req_cached); 1162 1163 switch (epp) { 1164 case AMD_CPPC_EPP_PERFORMANCE: 1165 preference = EPP_INDEX_PERFORMANCE; 1166 break; 1167 case AMD_CPPC_EPP_BALANCE_PERFORMANCE: 1168 preference = EPP_INDEX_BALANCE_PERFORMANCE; 1169 break; 1170 case AMD_CPPC_EPP_BALANCE_POWERSAVE: 1171 preference = EPP_INDEX_BALANCE_POWERSAVE; 1172 break; 1173 case AMD_CPPC_EPP_POWERSAVE: 1174 preference = EPP_INDEX_POWERSAVE; 1175 break; 1176 default: 1177 return -EINVAL; 1178 } 1179 1180 return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); 1181 } 1182 1183 static void amd_pstate_driver_cleanup(void) 1184 { 1185 if (amd_pstate_prefcore) 1186 sched_clear_itmt_support(); 1187 1188 cppc_state = AMD_PSTATE_DISABLE; 1189 current_pstate_driver = NULL; 1190 } 1191 1192 static int amd_pstate_set_driver(int mode_idx) 1193 { 1194 if (mode_idx >= AMD_PSTATE_DISABLE && mode_idx < AMD_PSTATE_MAX) { 1195 cppc_state = mode_idx; 1196 if (cppc_state == AMD_PSTATE_DISABLE) 1197 pr_info("driver is explicitly disabled\n"); 1198 1199 if (cppc_state == AMD_PSTATE_ACTIVE) 1200 current_pstate_driver = &amd_pstate_epp_driver; 1201 1202 if (cppc_state == AMD_PSTATE_PASSIVE || cppc_state == AMD_PSTATE_GUIDED) 1203 current_pstate_driver = &amd_pstate_driver; 1204 1205 return 0; 1206 } 1207 1208 return -EINVAL; 1209 } 1210 1211 static int amd_pstate_register_driver(int mode) 1212 { 1213 int ret; 1214 1215 ret = amd_pstate_set_driver(mode); 1216 if (ret) 1217 return ret; 1218 1219 cppc_state = mode; 1220 1221 /* at least one CPU supports CPB */ 1222 current_pstate_driver->boost_enabled = cpu_feature_enabled(X86_FEATURE_CPB); 1223 1224 ret = cpufreq_register_driver(current_pstate_driver); 1225 if (ret) { 1226 amd_pstate_driver_cleanup(); 1227 return ret; 1228 } 1229 1230 /* Enable ITMT support once all CPUs have initialized their asym priorities. */ 1231 if (amd_pstate_prefcore) 1232 sched_set_itmt_support(); 1233 1234 return 0; 1235 } 1236 1237 static int amd_pstate_unregister_driver(int dummy) 1238 { 1239 cpufreq_unregister_driver(current_pstate_driver); 1240 amd_pstate_driver_cleanup(); 1241 return 0; 1242 } 1243 1244 static int amd_pstate_change_mode_without_dvr_change(int mode) 1245 { 1246 int cpu = 0; 1247 1248 cppc_state = mode; 1249 1250 if (cpu_feature_enabled(X86_FEATURE_CPPC) || cppc_state == AMD_PSTATE_ACTIVE) 1251 return 0; 1252 1253 for_each_present_cpu(cpu) { 1254 cppc_set_auto_sel(cpu, (cppc_state == AMD_PSTATE_PASSIVE) ? 0 : 1); 1255 } 1256 1257 return 0; 1258 } 1259 1260 static int amd_pstate_change_driver_mode(int mode) 1261 { 1262 int ret; 1263 1264 ret = amd_pstate_unregister_driver(0); 1265 if (ret) 1266 return ret; 1267 1268 ret = amd_pstate_register_driver(mode); 1269 if (ret) 1270 return ret; 1271 1272 return 0; 1273 } 1274 1275 static cppc_mode_transition_fn mode_state_machine[AMD_PSTATE_MAX][AMD_PSTATE_MAX] = { 1276 [AMD_PSTATE_DISABLE] = { 1277 [AMD_PSTATE_DISABLE] = NULL, 1278 [AMD_PSTATE_PASSIVE] = amd_pstate_register_driver, 1279 [AMD_PSTATE_ACTIVE] = amd_pstate_register_driver, 1280 [AMD_PSTATE_GUIDED] = amd_pstate_register_driver, 1281 }, 1282 [AMD_PSTATE_PASSIVE] = { 1283 [AMD_PSTATE_DISABLE] = amd_pstate_unregister_driver, 1284 [AMD_PSTATE_PASSIVE] = NULL, 1285 [AMD_PSTATE_ACTIVE] = amd_pstate_change_driver_mode, 1286 [AMD_PSTATE_GUIDED] = amd_pstate_change_mode_without_dvr_change, 1287 }, 1288 [AMD_PSTATE_ACTIVE] = { 1289 [AMD_PSTATE_DISABLE] = amd_pstate_unregister_driver, 1290 [AMD_PSTATE_PASSIVE] = amd_pstate_change_driver_mode, 1291 [AMD_PSTATE_ACTIVE] = NULL, 1292 [AMD_PSTATE_GUIDED] = amd_pstate_change_driver_mode, 1293 }, 1294 [AMD_PSTATE_GUIDED] = { 1295 [AMD_PSTATE_DISABLE] = amd_pstate_unregister_driver, 1296 [AMD_PSTATE_PASSIVE] = amd_pstate_change_mode_without_dvr_change, 1297 [AMD_PSTATE_ACTIVE] = amd_pstate_change_driver_mode, 1298 [AMD_PSTATE_GUIDED] = NULL, 1299 }, 1300 }; 1301 1302 static ssize_t amd_pstate_show_status(char *buf) 1303 { 1304 if (!current_pstate_driver) 1305 return sysfs_emit(buf, "disable\n"); 1306 1307 return sysfs_emit(buf, "%s\n", amd_pstate_mode_string[cppc_state]); 1308 } 1309 1310 int amd_pstate_update_status(const char *buf, size_t size) 1311 { 1312 int mode_idx; 1313 1314 if (size > strlen("passive") || size < strlen("active")) 1315 return -EINVAL; 1316 1317 mode_idx = get_mode_idx_from_str(buf, size); 1318 1319 if (mode_idx < 0 || mode_idx >= AMD_PSTATE_MAX) 1320 return -EINVAL; 1321 1322 if (mode_state_machine[cppc_state][mode_idx]) { 1323 guard(mutex)(&amd_pstate_driver_lock); 1324 return mode_state_machine[cppc_state][mode_idx](mode_idx); 1325 } 1326 1327 return 0; 1328 } 1329 EXPORT_SYMBOL_GPL(amd_pstate_update_status); 1330 1331 static ssize_t status_show(struct device *dev, 1332 struct device_attribute *attr, char *buf) 1333 { 1334 1335 guard(mutex)(&amd_pstate_driver_lock); 1336 1337 return amd_pstate_show_status(buf); 1338 } 1339 1340 static ssize_t status_store(struct device *a, struct device_attribute *b, 1341 const char *buf, size_t count) 1342 { 1343 char *p = memchr(buf, '\n', count); 1344 int ret; 1345 1346 ret = amd_pstate_update_status(buf, p ? p - buf : count); 1347 1348 return ret < 0 ? ret : count; 1349 } 1350 1351 static ssize_t prefcore_show(struct device *dev, 1352 struct device_attribute *attr, char *buf) 1353 { 1354 return sysfs_emit(buf, "%s\n", str_enabled_disabled(amd_pstate_prefcore)); 1355 } 1356 1357 cpufreq_freq_attr_ro(amd_pstate_max_freq); 1358 cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); 1359 1360 cpufreq_freq_attr_ro(amd_pstate_highest_perf); 1361 cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking); 1362 cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); 1363 cpufreq_freq_attr_rw(energy_performance_preference); 1364 cpufreq_freq_attr_ro(energy_performance_available_preferences); 1365 static DEVICE_ATTR_RW(status); 1366 static DEVICE_ATTR_RO(prefcore); 1367 1368 static struct freq_attr *amd_pstate_attr[] = { 1369 &amd_pstate_max_freq, 1370 &amd_pstate_lowest_nonlinear_freq, 1371 &amd_pstate_highest_perf, 1372 &amd_pstate_prefcore_ranking, 1373 &amd_pstate_hw_prefcore, 1374 NULL, 1375 }; 1376 1377 static struct freq_attr *amd_pstate_epp_attr[] = { 1378 &amd_pstate_max_freq, 1379 &amd_pstate_lowest_nonlinear_freq, 1380 &amd_pstate_highest_perf, 1381 &amd_pstate_prefcore_ranking, 1382 &amd_pstate_hw_prefcore, 1383 &energy_performance_preference, 1384 &energy_performance_available_preferences, 1385 NULL, 1386 }; 1387 1388 static struct attribute *pstate_global_attributes[] = { 1389 &dev_attr_status.attr, 1390 &dev_attr_prefcore.attr, 1391 NULL 1392 }; 1393 1394 static const struct attribute_group amd_pstate_global_attr_group = { 1395 .name = "amd_pstate", 1396 .attrs = pstate_global_attributes, 1397 }; 1398 1399 static bool amd_pstate_acpi_pm_profile_server(void) 1400 { 1401 switch (acpi_gbl_FADT.preferred_profile) { 1402 case PM_ENTERPRISE_SERVER: 1403 case PM_SOHO_SERVER: 1404 case PM_PERFORMANCE_SERVER: 1405 return true; 1406 } 1407 return false; 1408 } 1409 1410 static bool amd_pstate_acpi_pm_profile_undefined(void) 1411 { 1412 if (acpi_gbl_FADT.preferred_profile == PM_UNSPECIFIED) 1413 return true; 1414 if (acpi_gbl_FADT.preferred_profile >= NR_PM_PROFILES) 1415 return true; 1416 return false; 1417 } 1418 1419 static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) 1420 { 1421 struct amd_cpudata *cpudata; 1422 union perf_cached perf; 1423 struct device *dev; 1424 u64 value; 1425 int ret; 1426 1427 /* 1428 * Resetting PERF_CTL_MSR will put the CPU in P0 frequency, 1429 * which is ideal for initialization process. 1430 */ 1431 amd_perf_ctl_reset(policy->cpu); 1432 dev = get_cpu_device(policy->cpu); 1433 if (!dev) 1434 return -ENODEV; 1435 1436 cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL); 1437 if (!cpudata) 1438 return -ENOMEM; 1439 1440 cpudata->cpu = policy->cpu; 1441 1442 ret = amd_pstate_init_perf(cpudata); 1443 if (ret) 1444 goto free_cpudata1; 1445 1446 amd_pstate_init_prefcore(cpudata); 1447 1448 ret = amd_pstate_init_freq(cpudata); 1449 if (ret) 1450 goto free_cpudata1; 1451 1452 ret = amd_pstate_init_boost_support(cpudata); 1453 if (ret) 1454 goto free_cpudata1; 1455 1456 perf = READ_ONCE(cpudata->perf); 1457 1458 policy->cpuinfo.min_freq = policy->min = perf_to_freq(perf, 1459 cpudata->nominal_freq, 1460 perf.lowest_perf); 1461 policy->cpuinfo.max_freq = policy->max = perf_to_freq(perf, 1462 cpudata->nominal_freq, 1463 perf.highest_perf); 1464 policy->driver_data = cpudata; 1465 1466 ret = amd_pstate_cppc_enable(policy); 1467 if (ret) 1468 goto free_cpudata1; 1469 1470 /* It will be updated by governor */ 1471 policy->cur = policy->cpuinfo.min_freq; 1472 1473 1474 policy->boost_supported = READ_ONCE(cpudata->boost_supported); 1475 1476 /* 1477 * Set the policy to provide a valid fallback value in case 1478 * the default cpufreq governor is neither powersave nor performance. 1479 */ 1480 if (amd_pstate_acpi_pm_profile_server() || 1481 amd_pstate_acpi_pm_profile_undefined()) { 1482 policy->policy = CPUFREQ_POLICY_PERFORMANCE; 1483 cpudata->epp_default = amd_pstate_get_epp(cpudata); 1484 } else { 1485 policy->policy = CPUFREQ_POLICY_POWERSAVE; 1486 cpudata->epp_default = AMD_CPPC_EPP_BALANCE_PERFORMANCE; 1487 } 1488 1489 if (cpu_feature_enabled(X86_FEATURE_CPPC)) { 1490 ret = rdmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); 1491 if (ret) 1492 return ret; 1493 WRITE_ONCE(cpudata->cppc_req_cached, value); 1494 } 1495 ret = amd_pstate_set_epp(policy, cpudata->epp_default); 1496 if (ret) 1497 return ret; 1498 1499 current_pstate_driver->adjust_perf = NULL; 1500 1501 return 0; 1502 1503 free_cpudata1: 1504 pr_warn("Failed to initialize CPU %d: %d\n", policy->cpu, ret); 1505 kfree(cpudata); 1506 return ret; 1507 } 1508 1509 static void amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy) 1510 { 1511 struct amd_cpudata *cpudata = policy->driver_data; 1512 1513 if (cpudata) { 1514 kfree(cpudata); 1515 policy->driver_data = NULL; 1516 } 1517 1518 pr_debug("CPU %d exiting\n", policy->cpu); 1519 } 1520 1521 static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) 1522 { 1523 struct amd_cpudata *cpudata = policy->driver_data; 1524 union perf_cached perf; 1525 u8 epp; 1526 1527 if (policy->min != cpudata->min_limit_freq || policy->max != cpudata->max_limit_freq) 1528 amd_pstate_update_min_max_limit(policy); 1529 1530 if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) 1531 epp = 0; 1532 else 1533 epp = FIELD_GET(AMD_CPPC_EPP_PERF_MASK, cpudata->cppc_req_cached); 1534 1535 perf = READ_ONCE(cpudata->perf); 1536 1537 return amd_pstate_update_perf(policy, perf.min_limit_perf, 0U, 1538 perf.max_limit_perf, epp, false); 1539 } 1540 1541 static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) 1542 { 1543 struct amd_cpudata *cpudata = policy->driver_data; 1544 int ret; 1545 1546 if (!policy->cpuinfo.max_freq) 1547 return -ENODEV; 1548 1549 cpudata->policy = policy->policy; 1550 1551 ret = amd_pstate_epp_update_limit(policy); 1552 if (ret) 1553 return ret; 1554 1555 /* 1556 * policy->cur is never updated with the amd_pstate_epp driver, but it 1557 * is used as a stale frequency value. So, keep it within limits. 1558 */ 1559 policy->cur = policy->min; 1560 1561 return 0; 1562 } 1563 1564 static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy) 1565 { 1566 pr_debug("AMD CPU Core %d going online\n", policy->cpu); 1567 1568 return amd_pstate_cppc_enable(policy); 1569 } 1570 1571 static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy) 1572 { 1573 return 0; 1574 } 1575 1576 static int amd_pstate_epp_suspend(struct cpufreq_policy *policy) 1577 { 1578 struct amd_cpudata *cpudata = policy->driver_data; 1579 1580 /* invalidate to ensure it's rewritten during resume */ 1581 cpudata->cppc_req_cached = 0; 1582 1583 /* set this flag to avoid setting core offline*/ 1584 cpudata->suspended = true; 1585 1586 return 0; 1587 } 1588 1589 static int amd_pstate_epp_resume(struct cpufreq_policy *policy) 1590 { 1591 struct amd_cpudata *cpudata = policy->driver_data; 1592 1593 if (cpudata->suspended) { 1594 int ret; 1595 1596 /* enable amd pstate from suspend state*/ 1597 ret = amd_pstate_epp_update_limit(policy); 1598 if (ret) 1599 return ret; 1600 1601 cpudata->suspended = false; 1602 } 1603 1604 return 0; 1605 } 1606 1607 static struct cpufreq_driver amd_pstate_driver = { 1608 .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, 1609 .verify = amd_pstate_verify, 1610 .target = amd_pstate_target, 1611 .fast_switch = amd_pstate_fast_switch, 1612 .init = amd_pstate_cpu_init, 1613 .exit = amd_pstate_cpu_exit, 1614 .set_boost = amd_pstate_set_boost, 1615 .update_limits = amd_pstate_update_limits, 1616 .name = "amd-pstate", 1617 .attr = amd_pstate_attr, 1618 }; 1619 1620 static struct cpufreq_driver amd_pstate_epp_driver = { 1621 .flags = CPUFREQ_CONST_LOOPS, 1622 .verify = amd_pstate_verify, 1623 .setpolicy = amd_pstate_epp_set_policy, 1624 .init = amd_pstate_epp_cpu_init, 1625 .exit = amd_pstate_epp_cpu_exit, 1626 .offline = amd_pstate_epp_cpu_offline, 1627 .online = amd_pstate_epp_cpu_online, 1628 .suspend = amd_pstate_epp_suspend, 1629 .resume = amd_pstate_epp_resume, 1630 .update_limits = amd_pstate_update_limits, 1631 .set_boost = amd_pstate_set_boost, 1632 .name = "amd-pstate-epp", 1633 .attr = amd_pstate_epp_attr, 1634 }; 1635 1636 /* 1637 * CPPC function is not supported for family ID 17H with model_ID ranging from 0x10 to 0x2F. 1638 * show the debug message that helps to check if the CPU has CPPC support for loading issue. 1639 */ 1640 static bool amd_cppc_supported(void) 1641 { 1642 struct cpuinfo_x86 *c = &cpu_data(0); 1643 bool warn = false; 1644 1645 if ((boot_cpu_data.x86 == 0x17) && (boot_cpu_data.x86_model < 0x30)) { 1646 pr_debug_once("CPPC feature is not supported by the processor\n"); 1647 return false; 1648 } 1649 1650 /* 1651 * If the CPPC feature is disabled in the BIOS for processors 1652 * that support MSR-based CPPC, the AMD Pstate driver may not 1653 * function correctly. 1654 * 1655 * For such processors, check the CPPC flag and display a 1656 * warning message if the platform supports CPPC. 1657 * 1658 * Note: The code check below will not abort the driver 1659 * registration process because of the code is added for 1660 * debugging purposes. Besides, it may still be possible for 1661 * the driver to work using the shared-memory mechanism. 1662 */ 1663 if (!cpu_feature_enabled(X86_FEATURE_CPPC)) { 1664 if (cpu_feature_enabled(X86_FEATURE_ZEN2)) { 1665 switch (c->x86_model) { 1666 case 0x60 ... 0x6F: 1667 case 0x80 ... 0xAF: 1668 warn = true; 1669 break; 1670 } 1671 } else if (cpu_feature_enabled(X86_FEATURE_ZEN3) || 1672 cpu_feature_enabled(X86_FEATURE_ZEN4)) { 1673 switch (c->x86_model) { 1674 case 0x10 ... 0x1F: 1675 case 0x40 ... 0xAF: 1676 warn = true; 1677 break; 1678 } 1679 } else if (cpu_feature_enabled(X86_FEATURE_ZEN5)) { 1680 warn = true; 1681 } 1682 } 1683 1684 if (warn) 1685 pr_warn_once("The CPPC feature is supported but currently disabled by the BIOS.\n" 1686 "Please enable it if your BIOS has the CPPC option.\n"); 1687 return true; 1688 } 1689 1690 static int __init amd_pstate_init(void) 1691 { 1692 struct device *dev_root; 1693 int ret; 1694 1695 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) 1696 return -ENODEV; 1697 1698 /* show debug message only if CPPC is not supported */ 1699 if (!amd_cppc_supported()) 1700 return -EOPNOTSUPP; 1701 1702 /* show warning message when BIOS broken or ACPI disabled */ 1703 if (!acpi_cpc_valid()) { 1704 pr_warn_once("the _CPC object is not present in SBIOS or ACPI disabled\n"); 1705 return -ENODEV; 1706 } 1707 1708 /* don't keep reloading if cpufreq_driver exists */ 1709 if (cpufreq_get_current_driver()) 1710 return -EEXIST; 1711 1712 quirks = NULL; 1713 1714 /* check if this machine need CPPC quirks */ 1715 dmi_check_system(amd_pstate_quirks_table); 1716 1717 /* 1718 * determine the driver mode from the command line or kernel config. 1719 * If no command line input is provided, cppc_state will be AMD_PSTATE_UNDEFINED. 1720 * command line options will override the kernel config settings. 1721 */ 1722 1723 if (cppc_state == AMD_PSTATE_UNDEFINED) { 1724 /* Disable on the following configs by default: 1725 * 1. Undefined platforms 1726 * 2. Server platforms with CPUs older than Family 0x1A. 1727 */ 1728 if (amd_pstate_acpi_pm_profile_undefined() || 1729 (amd_pstate_acpi_pm_profile_server() && boot_cpu_data.x86 < 0x1A)) { 1730 pr_info("driver load is disabled, boot with specific mode to enable this\n"); 1731 return -ENODEV; 1732 } 1733 /* get driver mode from kernel config option [1:4] */ 1734 cppc_state = CONFIG_X86_AMD_PSTATE_DEFAULT_MODE; 1735 } 1736 1737 if (cppc_state == AMD_PSTATE_DISABLE) { 1738 pr_info("driver load is disabled, boot with specific mode to enable this\n"); 1739 return -ENODEV; 1740 } 1741 1742 /* capability check */ 1743 if (cpu_feature_enabled(X86_FEATURE_CPPC)) { 1744 pr_debug("AMD CPPC MSR based functionality is supported\n"); 1745 } else { 1746 pr_debug("AMD CPPC shared memory based functionality is supported\n"); 1747 static_call_update(amd_pstate_cppc_enable, shmem_cppc_enable); 1748 static_call_update(amd_pstate_init_perf, shmem_init_perf); 1749 static_call_update(amd_pstate_update_perf, shmem_update_perf); 1750 static_call_update(amd_pstate_get_epp, shmem_get_epp); 1751 static_call_update(amd_pstate_set_epp, shmem_set_epp); 1752 } 1753 1754 if (amd_pstate_prefcore) { 1755 ret = amd_detect_prefcore(&amd_pstate_prefcore); 1756 if (ret) 1757 return ret; 1758 } 1759 1760 ret = amd_pstate_register_driver(cppc_state); 1761 if (ret) { 1762 pr_err("failed to register with return %d\n", ret); 1763 return ret; 1764 } 1765 1766 dev_root = bus_get_dev_root(&cpu_subsys); 1767 if (dev_root) { 1768 ret = sysfs_create_group(&dev_root->kobj, &amd_pstate_global_attr_group); 1769 put_device(dev_root); 1770 if (ret) { 1771 pr_err("sysfs attribute export failed with error %d.\n", ret); 1772 goto global_attr_free; 1773 } 1774 } 1775 1776 return ret; 1777 1778 global_attr_free: 1779 cpufreq_unregister_driver(current_pstate_driver); 1780 return ret; 1781 } 1782 device_initcall(amd_pstate_init); 1783 1784 static int __init amd_pstate_param(char *str) 1785 { 1786 size_t size; 1787 int mode_idx; 1788 1789 if (!str) 1790 return -EINVAL; 1791 1792 size = strlen(str); 1793 mode_idx = get_mode_idx_from_str(str, size); 1794 1795 return amd_pstate_set_driver(mode_idx); 1796 } 1797 1798 static int __init amd_prefcore_param(char *str) 1799 { 1800 if (!strcmp(str, "disable")) 1801 amd_pstate_prefcore = false; 1802 1803 return 0; 1804 } 1805 1806 early_param("amd_pstate", amd_pstate_param); 1807 early_param("amd_prefcore", amd_prefcore_param); 1808 1809 MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>"); 1810 MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); 1811