1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2019 David Lechner <david@lechnology.com> 4 * 5 * Counter driver for Texas Instruments Enhanced Quadrature Encoder Pulse (eQEP) 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/counter.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/types.h> 18 19 /* 32-bit registers */ 20 #define QPOSCNT 0x0 21 #define QPOSINIT 0x4 22 #define QPOSMAX 0x8 23 #define QPOSCMP 0xc 24 #define QPOSILAT 0x10 25 #define QPOSSLAT 0x14 26 #define QPOSLAT 0x18 27 #define QUTMR 0x1c 28 #define QUPRD 0x20 29 30 /* 16-bit registers */ 31 #define QWDTMR 0x0 /* 0x24 */ 32 #define QWDPRD 0x2 /* 0x26 */ 33 #define QDECCTL 0x4 /* 0x28 */ 34 #define QEPCTL 0x6 /* 0x2a */ 35 #define QCAPCTL 0x8 /* 0x2c */ 36 #define QPOSCTL 0xa /* 0x2e */ 37 #define QEINT 0xc /* 0x30 */ 38 #define QFLG 0xe /* 0x32 */ 39 #define QCLR 0x10 /* 0x34 */ 40 #define QFRC 0x12 /* 0x36 */ 41 #define QEPSTS 0x14 /* 0x38 */ 42 #define QCTMR 0x16 /* 0x3a */ 43 #define QCPRD 0x18 /* 0x3c */ 44 #define QCTMRLAT 0x1a /* 0x3e */ 45 #define QCPRDLAT 0x1c /* 0x40 */ 46 47 #define QDECCTL_QSRC_SHIFT 14 48 #define QDECCTL_QSRC GENMASK(15, 14) 49 #define QDECCTL_SOEN BIT(13) 50 #define QDECCTL_SPSEL BIT(12) 51 #define QDECCTL_XCR BIT(11) 52 #define QDECCTL_SWAP BIT(10) 53 #define QDECCTL_IGATE BIT(9) 54 #define QDECCTL_QAP BIT(8) 55 #define QDECCTL_QBP BIT(7) 56 #define QDECCTL_QIP BIT(6) 57 #define QDECCTL_QSP BIT(5) 58 59 #define QEPCTL_FREE_SOFT GENMASK(15, 14) 60 #define QEPCTL_PCRM GENMASK(13, 12) 61 #define QEPCTL_SEI GENMASK(11, 10) 62 #define QEPCTL_IEI GENMASK(9, 8) 63 #define QEPCTL_SWI BIT(7) 64 #define QEPCTL_SEL BIT(6) 65 #define QEPCTL_IEL GENMASK(5, 4) 66 #define QEPCTL_PHEN BIT(3) 67 #define QEPCTL_QCLM BIT(2) 68 #define QEPCTL_UTE BIT(1) 69 #define QEPCTL_WDE BIT(0) 70 71 #define QEINT_UTO BIT(11) 72 #define QEINT_IEL BIT(10) 73 #define QEINT_SEL BIT(9) 74 #define QEINT_PCM BIT(8) 75 #define QEINT_PCR BIT(7) 76 #define QEINT_PCO BIT(6) 77 #define QEINT_PCU BIT(5) 78 #define QEINT_WTO BIT(4) 79 #define QEINT_QDC BIT(3) 80 #define QEINT_PHE BIT(2) 81 #define QEINT_PCE BIT(1) 82 83 #define QFLG_UTO BIT(11) 84 #define QFLG_IEL BIT(10) 85 #define QFLG_SEL BIT(9) 86 #define QFLG_PCM BIT(8) 87 #define QFLG_PCR BIT(7) 88 #define QFLG_PCO BIT(6) 89 #define QFLG_PCU BIT(5) 90 #define QFLG_WTO BIT(4) 91 #define QFLG_QDC BIT(3) 92 #define QFLG_PHE BIT(2) 93 #define QFLG_PCE BIT(1) 94 #define QFLG_INT BIT(0) 95 96 #define QCLR_UTO BIT(11) 97 #define QCLR_IEL BIT(10) 98 #define QCLR_SEL BIT(9) 99 #define QCLR_PCM BIT(8) 100 #define QCLR_PCR BIT(7) 101 #define QCLR_PCO BIT(6) 102 #define QCLR_PCU BIT(5) 103 #define QCLR_WTO BIT(4) 104 #define QCLR_QDC BIT(3) 105 #define QCLR_PHE BIT(2) 106 #define QCLR_PCE BIT(1) 107 #define QCLR_INT BIT(0) 108 109 #define QEPSTS_UPEVNT BIT(7) 110 #define QEPSTS_FDF BIT(6) 111 #define QEPSTS_QDF BIT(5) 112 #define QEPSTS_QDLF BIT(4) 113 #define QEPSTS_COEF BIT(3) 114 #define QEPSTS_CDEF BIT(2) 115 #define QEPSTS_FIMF BIT(1) 116 #define QEPSTS_PCEF BIT(0) 117 118 /* EQEP Inputs */ 119 enum { 120 TI_EQEP_SIGNAL_QEPA, /* QEPA/XCLK */ 121 TI_EQEP_SIGNAL_QEPB, /* QEPB/XDIR */ 122 }; 123 124 /* Position Counter Input Modes */ 125 enum ti_eqep_count_func { 126 TI_EQEP_COUNT_FUNC_QUAD_COUNT, 127 TI_EQEP_COUNT_FUNC_DIR_COUNT, 128 TI_EQEP_COUNT_FUNC_UP_COUNT, 129 TI_EQEP_COUNT_FUNC_DOWN_COUNT, 130 }; 131 132 struct ti_eqep_cnt { 133 struct regmap *regmap32; 134 struct regmap *regmap16; 135 }; 136 137 static int ti_eqep_count_read(struct counter_device *counter, 138 struct counter_count *count, u64 *val) 139 { 140 struct ti_eqep_cnt *priv = counter_priv(counter); 141 u32 cnt; 142 143 regmap_read(priv->regmap32, QPOSCNT, &cnt); 144 *val = cnt; 145 146 return 0; 147 } 148 149 static int ti_eqep_count_write(struct counter_device *counter, 150 struct counter_count *count, u64 val) 151 { 152 struct ti_eqep_cnt *priv = counter_priv(counter); 153 u32 max; 154 155 regmap_read(priv->regmap32, QPOSMAX, &max); 156 if (val > max) 157 return -EINVAL; 158 159 return regmap_write(priv->regmap32, QPOSCNT, val); 160 } 161 162 static int ti_eqep_function_read(struct counter_device *counter, 163 struct counter_count *count, 164 enum counter_function *function) 165 { 166 struct ti_eqep_cnt *priv = counter_priv(counter); 167 u32 qdecctl; 168 169 regmap_read(priv->regmap16, QDECCTL, &qdecctl); 170 171 switch ((qdecctl & QDECCTL_QSRC) >> QDECCTL_QSRC_SHIFT) { 172 case TI_EQEP_COUNT_FUNC_QUAD_COUNT: 173 *function = COUNTER_FUNCTION_QUADRATURE_X4; 174 break; 175 case TI_EQEP_COUNT_FUNC_DIR_COUNT: 176 *function = COUNTER_FUNCTION_PULSE_DIRECTION; 177 break; 178 case TI_EQEP_COUNT_FUNC_UP_COUNT: 179 *function = COUNTER_FUNCTION_INCREASE; 180 break; 181 case TI_EQEP_COUNT_FUNC_DOWN_COUNT: 182 *function = COUNTER_FUNCTION_DECREASE; 183 break; 184 } 185 186 return 0; 187 } 188 189 static int ti_eqep_function_write(struct counter_device *counter, 190 struct counter_count *count, 191 enum counter_function function) 192 { 193 struct ti_eqep_cnt *priv = counter_priv(counter); 194 enum ti_eqep_count_func qsrc; 195 196 switch (function) { 197 case COUNTER_FUNCTION_QUADRATURE_X4: 198 qsrc = TI_EQEP_COUNT_FUNC_QUAD_COUNT; 199 break; 200 case COUNTER_FUNCTION_PULSE_DIRECTION: 201 qsrc = TI_EQEP_COUNT_FUNC_DIR_COUNT; 202 break; 203 case COUNTER_FUNCTION_INCREASE: 204 qsrc = TI_EQEP_COUNT_FUNC_UP_COUNT; 205 break; 206 case COUNTER_FUNCTION_DECREASE: 207 qsrc = TI_EQEP_COUNT_FUNC_DOWN_COUNT; 208 break; 209 default: 210 /* should never reach this path */ 211 return -EINVAL; 212 } 213 214 return regmap_write_bits(priv->regmap16, QDECCTL, QDECCTL_QSRC, 215 qsrc << QDECCTL_QSRC_SHIFT); 216 } 217 218 static int ti_eqep_action_read(struct counter_device *counter, 219 struct counter_count *count, 220 struct counter_synapse *synapse, 221 enum counter_synapse_action *action) 222 { 223 struct ti_eqep_cnt *priv = counter_priv(counter); 224 enum counter_function function; 225 u32 qdecctl; 226 int err; 227 228 err = ti_eqep_function_read(counter, count, &function); 229 if (err) 230 return err; 231 232 switch (function) { 233 case COUNTER_FUNCTION_QUADRATURE_X4: 234 /* In quadrature mode, the rising and falling edge of both 235 * QEPA and QEPB trigger QCLK. 236 */ 237 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; 238 return 0; 239 case COUNTER_FUNCTION_PULSE_DIRECTION: 240 /* In direction-count mode only rising edge of QEPA is counted 241 * and QEPB gives direction. 242 */ 243 switch (synapse->signal->id) { 244 case TI_EQEP_SIGNAL_QEPA: 245 *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE; 246 return 0; 247 case TI_EQEP_SIGNAL_QEPB: 248 *action = COUNTER_SYNAPSE_ACTION_NONE; 249 return 0; 250 default: 251 /* should never reach this path */ 252 return -EINVAL; 253 } 254 case COUNTER_FUNCTION_INCREASE: 255 case COUNTER_FUNCTION_DECREASE: 256 /* In up/down-count modes only QEPA is counted and QEPB is not 257 * used. 258 */ 259 switch (synapse->signal->id) { 260 case TI_EQEP_SIGNAL_QEPA: 261 err = regmap_read(priv->regmap16, QDECCTL, &qdecctl); 262 if (err) 263 return err; 264 265 if (qdecctl & QDECCTL_XCR) 266 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; 267 else 268 *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE; 269 return 0; 270 case TI_EQEP_SIGNAL_QEPB: 271 *action = COUNTER_SYNAPSE_ACTION_NONE; 272 return 0; 273 default: 274 /* should never reach this path */ 275 return -EINVAL; 276 } 277 default: 278 /* should never reach this path */ 279 return -EINVAL; 280 } 281 } 282 283 static int ti_eqep_events_configure(struct counter_device *counter) 284 { 285 struct ti_eqep_cnt *priv = counter_priv(counter); 286 struct counter_event_node *event_node; 287 u32 qeint = 0; 288 289 list_for_each_entry(event_node, &counter->events_list, l) { 290 switch (event_node->event) { 291 case COUNTER_EVENT_OVERFLOW: 292 qeint |= QEINT_PCO; 293 break; 294 case COUNTER_EVENT_UNDERFLOW: 295 qeint |= QEINT_PCU; 296 break; 297 case COUNTER_EVENT_DIRECTION_CHANGE: 298 qeint |= QEINT_QDC; 299 break; 300 } 301 } 302 303 return regmap_write(priv->regmap16, QEINT, qeint); 304 } 305 306 static int ti_eqep_watch_validate(struct counter_device *counter, 307 const struct counter_watch *watch) 308 { 309 switch (watch->event) { 310 case COUNTER_EVENT_OVERFLOW: 311 case COUNTER_EVENT_UNDERFLOW: 312 case COUNTER_EVENT_DIRECTION_CHANGE: 313 if (watch->channel != 0) 314 return -EINVAL; 315 316 return 0; 317 default: 318 return -EINVAL; 319 } 320 } 321 322 static const struct counter_ops ti_eqep_counter_ops = { 323 .count_read = ti_eqep_count_read, 324 .count_write = ti_eqep_count_write, 325 .function_read = ti_eqep_function_read, 326 .function_write = ti_eqep_function_write, 327 .action_read = ti_eqep_action_read, 328 .events_configure = ti_eqep_events_configure, 329 .watch_validate = ti_eqep_watch_validate, 330 }; 331 332 static int ti_eqep_position_ceiling_read(struct counter_device *counter, 333 struct counter_count *count, 334 u64 *ceiling) 335 { 336 struct ti_eqep_cnt *priv = counter_priv(counter); 337 u32 qposmax; 338 339 regmap_read(priv->regmap32, QPOSMAX, &qposmax); 340 341 *ceiling = qposmax; 342 343 return 0; 344 } 345 346 static int ti_eqep_position_ceiling_write(struct counter_device *counter, 347 struct counter_count *count, 348 u64 ceiling) 349 { 350 struct ti_eqep_cnt *priv = counter_priv(counter); 351 352 if (ceiling != (u32)ceiling) 353 return -ERANGE; 354 355 regmap_write(priv->regmap32, QPOSMAX, ceiling); 356 357 return 0; 358 } 359 360 static int ti_eqep_position_enable_read(struct counter_device *counter, 361 struct counter_count *count, u8 *enable) 362 { 363 struct ti_eqep_cnt *priv = counter_priv(counter); 364 u32 qepctl; 365 366 regmap_read(priv->regmap16, QEPCTL, &qepctl); 367 368 *enable = !!(qepctl & QEPCTL_PHEN); 369 370 return 0; 371 } 372 373 static int ti_eqep_position_enable_write(struct counter_device *counter, 374 struct counter_count *count, u8 enable) 375 { 376 struct ti_eqep_cnt *priv = counter_priv(counter); 377 378 regmap_write_bits(priv->regmap16, QEPCTL, QEPCTL_PHEN, enable ? -1 : 0); 379 380 return 0; 381 } 382 383 static int ti_eqep_direction_read(struct counter_device *counter, 384 struct counter_count *count, 385 enum counter_count_direction *direction) 386 { 387 struct ti_eqep_cnt *priv = counter_priv(counter); 388 u32 qepsts; 389 390 regmap_read(priv->regmap16, QEPSTS, &qepsts); 391 392 *direction = (qepsts & QEPSTS_QDF) ? COUNTER_COUNT_DIRECTION_FORWARD 393 : COUNTER_COUNT_DIRECTION_BACKWARD; 394 395 return 0; 396 } 397 398 static struct counter_comp ti_eqep_position_ext[] = { 399 COUNTER_COMP_CEILING(ti_eqep_position_ceiling_read, 400 ti_eqep_position_ceiling_write), 401 COUNTER_COMP_ENABLE(ti_eqep_position_enable_read, 402 ti_eqep_position_enable_write), 403 COUNTER_COMP_DIRECTION(ti_eqep_direction_read), 404 }; 405 406 static struct counter_signal ti_eqep_signals[] = { 407 [TI_EQEP_SIGNAL_QEPA] = { 408 .id = TI_EQEP_SIGNAL_QEPA, 409 .name = "QEPA" 410 }, 411 [TI_EQEP_SIGNAL_QEPB] = { 412 .id = TI_EQEP_SIGNAL_QEPB, 413 .name = "QEPB" 414 }, 415 }; 416 417 static const enum counter_function ti_eqep_position_functions[] = { 418 COUNTER_FUNCTION_QUADRATURE_X4, 419 COUNTER_FUNCTION_PULSE_DIRECTION, 420 COUNTER_FUNCTION_INCREASE, 421 COUNTER_FUNCTION_DECREASE, 422 }; 423 424 static const enum counter_synapse_action ti_eqep_position_synapse_actions[] = { 425 COUNTER_SYNAPSE_ACTION_BOTH_EDGES, 426 COUNTER_SYNAPSE_ACTION_RISING_EDGE, 427 COUNTER_SYNAPSE_ACTION_NONE, 428 }; 429 430 static struct counter_synapse ti_eqep_position_synapses[] = { 431 { 432 .actions_list = ti_eqep_position_synapse_actions, 433 .num_actions = ARRAY_SIZE(ti_eqep_position_synapse_actions), 434 .signal = &ti_eqep_signals[TI_EQEP_SIGNAL_QEPA], 435 }, 436 { 437 .actions_list = ti_eqep_position_synapse_actions, 438 .num_actions = ARRAY_SIZE(ti_eqep_position_synapse_actions), 439 .signal = &ti_eqep_signals[TI_EQEP_SIGNAL_QEPB], 440 }, 441 }; 442 443 static struct counter_count ti_eqep_counts[] = { 444 { 445 .id = 0, 446 .name = "QPOSCNT", 447 .functions_list = ti_eqep_position_functions, 448 .num_functions = ARRAY_SIZE(ti_eqep_position_functions), 449 .synapses = ti_eqep_position_synapses, 450 .num_synapses = ARRAY_SIZE(ti_eqep_position_synapses), 451 .ext = ti_eqep_position_ext, 452 .num_ext = ARRAY_SIZE(ti_eqep_position_ext), 453 }, 454 }; 455 456 static irqreturn_t ti_eqep_irq_handler(int irq, void *dev_id) 457 { 458 struct counter_device *counter = dev_id; 459 struct ti_eqep_cnt *priv = counter_priv(counter); 460 u32 qflg; 461 462 regmap_read(priv->regmap16, QFLG, &qflg); 463 464 if (qflg & QFLG_PCO) 465 counter_push_event(counter, COUNTER_EVENT_OVERFLOW, 0); 466 467 if (qflg & QFLG_PCU) 468 counter_push_event(counter, COUNTER_EVENT_UNDERFLOW, 0); 469 470 if (qflg & QFLG_QDC) 471 counter_push_event(counter, COUNTER_EVENT_DIRECTION_CHANGE, 0); 472 473 regmap_write(priv->regmap16, QCLR, qflg); 474 475 return IRQ_HANDLED; 476 } 477 478 static const struct regmap_config ti_eqep_regmap32_config = { 479 .name = "32-bit", 480 .reg_bits = 32, 481 .val_bits = 32, 482 .reg_stride = 4, 483 .max_register = QUPRD, 484 }; 485 486 static const struct regmap_config ti_eqep_regmap16_config = { 487 .name = "16-bit", 488 .reg_bits = 16, 489 .val_bits = 16, 490 .reg_stride = 2, 491 .max_register = QCPRDLAT, 492 }; 493 494 static int ti_eqep_probe(struct platform_device *pdev) 495 { 496 struct device *dev = &pdev->dev; 497 struct counter_device *counter; 498 struct ti_eqep_cnt *priv; 499 void __iomem *base; 500 struct clk *clk; 501 int err, irq; 502 503 counter = devm_counter_alloc(dev, sizeof(*priv)); 504 if (!counter) 505 return -ENOMEM; 506 priv = counter_priv(counter); 507 508 base = devm_platform_ioremap_resource(pdev, 0); 509 if (IS_ERR(base)) 510 return PTR_ERR(base); 511 512 priv->regmap32 = devm_regmap_init_mmio(dev, base, 513 &ti_eqep_regmap32_config); 514 if (IS_ERR(priv->regmap32)) 515 return PTR_ERR(priv->regmap32); 516 517 priv->regmap16 = devm_regmap_init_mmio(dev, base + 0x24, 518 &ti_eqep_regmap16_config); 519 if (IS_ERR(priv->regmap16)) 520 return PTR_ERR(priv->regmap16); 521 522 irq = platform_get_irq(pdev, 0); 523 if (irq < 0) 524 return irq; 525 526 err = devm_request_threaded_irq(dev, irq, NULL, ti_eqep_irq_handler, 527 IRQF_ONESHOT, dev_name(dev), counter); 528 if (err < 0) 529 return dev_err_probe(dev, err, "failed to request IRQ\n"); 530 531 counter->name = dev_name(dev); 532 counter->parent = dev; 533 counter->ops = &ti_eqep_counter_ops; 534 counter->counts = ti_eqep_counts; 535 counter->num_counts = ARRAY_SIZE(ti_eqep_counts); 536 counter->signals = ti_eqep_signals; 537 counter->num_signals = ARRAY_SIZE(ti_eqep_signals); 538 539 platform_set_drvdata(pdev, counter); 540 541 /* 542 * Need to make sure power is turned on. On AM33xx, this comes from the 543 * parent PWMSS bus driver. On AM17xx, this comes from the PSC power 544 * domain. 545 */ 546 pm_runtime_enable(dev); 547 pm_runtime_get_sync(dev); 548 549 clk = devm_clk_get_enabled(dev, NULL); 550 if (IS_ERR(clk)) 551 return dev_err_probe(dev, PTR_ERR(clk), "failed to enable clock\n"); 552 553 err = counter_add(counter); 554 if (err < 0) { 555 pm_runtime_put_sync(dev); 556 pm_runtime_disable(dev); 557 return err; 558 } 559 560 return 0; 561 } 562 563 static void ti_eqep_remove(struct platform_device *pdev) 564 { 565 struct counter_device *counter = platform_get_drvdata(pdev); 566 struct device *dev = &pdev->dev; 567 568 counter_unregister(counter); 569 pm_runtime_put_sync(dev); 570 pm_runtime_disable(dev); 571 } 572 573 static const struct of_device_id ti_eqep_of_match[] = { 574 { .compatible = "ti,am3352-eqep", }, 575 { .compatible = "ti,am62-eqep", }, 576 { }, 577 }; 578 MODULE_DEVICE_TABLE(of, ti_eqep_of_match); 579 580 static struct platform_driver ti_eqep_driver = { 581 .probe = ti_eqep_probe, 582 .remove = ti_eqep_remove, 583 .driver = { 584 .name = "ti-eqep-cnt", 585 .of_match_table = ti_eqep_of_match, 586 }, 587 }; 588 module_platform_driver(ti_eqep_driver); 589 590 MODULE_AUTHOR("David Lechner <david@lechnology.com>"); 591 MODULE_DESCRIPTION("TI eQEP counter driver"); 592 MODULE_LICENSE("GPL v2"); 593 MODULE_IMPORT_NS("COUNTER"); 594