1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ECAP Capture driver 4 * 5 * Copyright (C) 2022 Julien Panis <jpanis@baylibre.com> 6 */ 7 8 #include <linux/atomic.h> 9 #include <linux/clk.h> 10 #include <linux/counter.h> 11 #include <linux/err.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 20 #define ECAP_DRV_NAME "ecap" 21 22 /* ECAP event IDs */ 23 #define ECAP_CEVT1 0 24 #define ECAP_CEVT2 1 25 #define ECAP_CEVT3 2 26 #define ECAP_CEVT4 3 27 #define ECAP_CNTOVF 4 28 29 #define ECAP_CEVT_LAST ECAP_CEVT4 30 #define ECAP_NB_CEVT (ECAP_CEVT_LAST + 1) 31 32 #define ECAP_EVT_LAST ECAP_CNTOVF 33 #define ECAP_NB_EVT (ECAP_EVT_LAST + 1) 34 35 /* Registers */ 36 #define ECAP_TSCNT_REG 0x00 37 38 #define ECAP_CAP_REG(i) (((i) << 2) + 0x08) 39 40 #define ECAP_ECCTL_REG 0x28 41 #define ECAP_CAPPOL_BIT(i) BIT((i) << 1) 42 #define ECAP_EV_MODE_MASK GENMASK(7, 0) 43 #define ECAP_CAPLDEN_BIT BIT(8) 44 #define ECAP_CONT_ONESHT_BIT BIT(16) 45 #define ECAP_STOPVALUE_MASK GENMASK(18, 17) 46 #define ECAP_TSCNTSTP_BIT BIT(20) 47 #define ECAP_SYNCO_DIS_MASK GENMASK(23, 22) 48 #define ECAP_CAP_APWM_BIT BIT(25) 49 #define ECAP_ECCTL_EN_MASK (ECAP_CAPLDEN_BIT | ECAP_TSCNTSTP_BIT) 50 #define ECAP_ECCTL_CFG_MASK (ECAP_SYNCO_DIS_MASK | ECAP_STOPVALUE_MASK \ 51 | ECAP_ECCTL_EN_MASK | ECAP_CAP_APWM_BIT \ 52 | ECAP_CONT_ONESHT_BIT) 53 54 #define ECAP_ECINT_EN_FLG_REG 0x2c 55 #define ECAP_EVT_EN_MASK GENMASK(ECAP_NB_EVT, ECAP_NB_CEVT) 56 #define ECAP_EVT_FLG_BIT(i) BIT((i) + 17) 57 58 #define ECAP_ECINT_CLR_FRC_REG 0x30 59 #define ECAP_INT_CLR_BIT BIT(0) 60 #define ECAP_EVT_CLR_BIT(i) BIT((i) + 1) 61 #define ECAP_EVT_CLR_MASK GENMASK(ECAP_NB_EVT, 0) 62 63 #define ECAP_PID_REG 0x5c 64 65 /* ECAP signals */ 66 #define ECAP_CLOCK_SIG 0 67 #define ECAP_INPUT_SIG 1 68 69 static const struct regmap_config ecap_cnt_regmap_config = { 70 .reg_bits = 32, 71 .reg_stride = 4, 72 .val_bits = 32, 73 .max_register = ECAP_PID_REG, 74 }; 75 76 /** 77 * struct ecap_cnt_dev - device private data structure 78 * @enabled: device state 79 * @lock: synchronization lock to prevent I/O race conditions 80 * @clk: device clock 81 * @regmap: device register map 82 * @nb_ovf: number of overflows since capture start 83 * @pm_ctx: device context for PM operations 84 * @pm_ctx.ev_mode: event mode bits 85 * @pm_ctx.time_cntr: timestamp counter value 86 */ 87 struct ecap_cnt_dev { 88 bool enabled; 89 struct mutex lock; 90 struct clk *clk; 91 struct regmap *regmap; 92 atomic_t nb_ovf; 93 struct { 94 u8 ev_mode; 95 u32 time_cntr; 96 } pm_ctx; 97 }; 98 99 static u8 ecap_cnt_capture_get_evmode(struct counter_device *counter) 100 { 101 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 102 unsigned int regval; 103 104 pm_runtime_get_sync(counter->parent); 105 regmap_read(ecap_dev->regmap, ECAP_ECCTL_REG, ®val); 106 pm_runtime_put_sync(counter->parent); 107 108 return regval; 109 } 110 111 static void ecap_cnt_capture_set_evmode(struct counter_device *counter, u8 ev_mode) 112 { 113 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 114 115 pm_runtime_get_sync(counter->parent); 116 regmap_update_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_EV_MODE_MASK, ev_mode); 117 pm_runtime_put_sync(counter->parent); 118 } 119 120 static void ecap_cnt_capture_enable(struct counter_device *counter) 121 { 122 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 123 124 pm_runtime_get_sync(counter->parent); 125 126 /* Enable interrupts on events */ 127 regmap_update_bits(ecap_dev->regmap, ECAP_ECINT_EN_FLG_REG, 128 ECAP_EVT_EN_MASK, ECAP_EVT_EN_MASK); 129 130 /* Run counter */ 131 regmap_update_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_ECCTL_CFG_MASK, 132 ECAP_SYNCO_DIS_MASK | ECAP_STOPVALUE_MASK | ECAP_ECCTL_EN_MASK); 133 } 134 135 static void ecap_cnt_capture_disable(struct counter_device *counter) 136 { 137 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 138 139 /* Stop counter */ 140 regmap_update_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_ECCTL_EN_MASK, 0); 141 142 /* Disable interrupts on events */ 143 regmap_update_bits(ecap_dev->regmap, ECAP_ECINT_EN_FLG_REG, ECAP_EVT_EN_MASK, 0); 144 145 pm_runtime_put_sync(counter->parent); 146 } 147 148 static u32 ecap_cnt_count_get_val(struct counter_device *counter, unsigned int reg) 149 { 150 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 151 unsigned int regval; 152 153 pm_runtime_get_sync(counter->parent); 154 regmap_read(ecap_dev->regmap, reg, ®val); 155 pm_runtime_put_sync(counter->parent); 156 157 return regval; 158 } 159 160 static void ecap_cnt_count_set_val(struct counter_device *counter, unsigned int reg, u32 val) 161 { 162 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 163 164 pm_runtime_get_sync(counter->parent); 165 regmap_write(ecap_dev->regmap, reg, val); 166 pm_runtime_put_sync(counter->parent); 167 } 168 169 static int ecap_cnt_count_read(struct counter_device *counter, 170 struct counter_count *count, u64 *val) 171 { 172 *val = ecap_cnt_count_get_val(counter, ECAP_TSCNT_REG); 173 174 return 0; 175 } 176 177 static int ecap_cnt_count_write(struct counter_device *counter, 178 struct counter_count *count, u64 val) 179 { 180 if (val > U32_MAX) 181 return -ERANGE; 182 183 ecap_cnt_count_set_val(counter, ECAP_TSCNT_REG, val); 184 185 return 0; 186 } 187 188 static int ecap_cnt_function_read(struct counter_device *counter, 189 struct counter_count *count, 190 enum counter_function *function) 191 { 192 *function = COUNTER_FUNCTION_INCREASE; 193 194 return 0; 195 } 196 197 static int ecap_cnt_action_read(struct counter_device *counter, 198 struct counter_count *count, 199 struct counter_synapse *synapse, 200 enum counter_synapse_action *action) 201 { 202 *action = (synapse->signal->id == ECAP_CLOCK_SIG) ? 203 COUNTER_SYNAPSE_ACTION_RISING_EDGE : 204 COUNTER_SYNAPSE_ACTION_NONE; 205 206 return 0; 207 } 208 209 static int ecap_cnt_watch_validate(struct counter_device *counter, 210 const struct counter_watch *watch) 211 { 212 if (watch->channel > ECAP_CEVT_LAST) 213 return -EINVAL; 214 215 switch (watch->event) { 216 case COUNTER_EVENT_CAPTURE: 217 case COUNTER_EVENT_OVERFLOW: 218 return 0; 219 default: 220 return -EINVAL; 221 } 222 } 223 224 static int ecap_cnt_clk_get_freq(struct counter_device *counter, 225 struct counter_signal *signal, u64 *freq) 226 { 227 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 228 229 *freq = clk_get_rate(ecap_dev->clk); 230 231 return 0; 232 } 233 234 static int ecap_cnt_pol_read(struct counter_device *counter, 235 struct counter_signal *signal, 236 size_t idx, enum counter_signal_polarity *pol) 237 { 238 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 239 int bitval; 240 241 pm_runtime_get_sync(counter->parent); 242 bitval = regmap_test_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_CAPPOL_BIT(idx)); 243 pm_runtime_put_sync(counter->parent); 244 245 *pol = bitval ? COUNTER_SIGNAL_POLARITY_NEGATIVE : COUNTER_SIGNAL_POLARITY_POSITIVE; 246 247 return 0; 248 } 249 250 static int ecap_cnt_pol_write(struct counter_device *counter, 251 struct counter_signal *signal, 252 size_t idx, enum counter_signal_polarity pol) 253 { 254 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 255 256 pm_runtime_get_sync(counter->parent); 257 if (pol == COUNTER_SIGNAL_POLARITY_NEGATIVE) 258 regmap_set_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_CAPPOL_BIT(idx)); 259 else 260 regmap_clear_bits(ecap_dev->regmap, ECAP_ECCTL_REG, ECAP_CAPPOL_BIT(idx)); 261 pm_runtime_put_sync(counter->parent); 262 263 return 0; 264 } 265 266 static int ecap_cnt_cap_read(struct counter_device *counter, 267 struct counter_count *count, 268 size_t idx, u64 *cap) 269 { 270 *cap = ecap_cnt_count_get_val(counter, ECAP_CAP_REG(idx)); 271 272 return 0; 273 } 274 275 static int ecap_cnt_cap_write(struct counter_device *counter, 276 struct counter_count *count, 277 size_t idx, u64 cap) 278 { 279 if (cap > U32_MAX) 280 return -ERANGE; 281 282 ecap_cnt_count_set_val(counter, ECAP_CAP_REG(idx), cap); 283 284 return 0; 285 } 286 287 static int ecap_cnt_nb_ovf_read(struct counter_device *counter, 288 struct counter_count *count, u64 *val) 289 { 290 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 291 292 *val = atomic_read(&ecap_dev->nb_ovf); 293 294 return 0; 295 } 296 297 static int ecap_cnt_nb_ovf_write(struct counter_device *counter, 298 struct counter_count *count, u64 val) 299 { 300 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 301 302 if (val > U32_MAX) 303 return -ERANGE; 304 305 atomic_set(&ecap_dev->nb_ovf, val); 306 307 return 0; 308 } 309 310 static int ecap_cnt_ceiling_read(struct counter_device *counter, 311 struct counter_count *count, u64 *val) 312 { 313 *val = U32_MAX; 314 315 return 0; 316 } 317 318 static int ecap_cnt_enable_read(struct counter_device *counter, 319 struct counter_count *count, u8 *enable) 320 { 321 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 322 323 *enable = ecap_dev->enabled; 324 325 return 0; 326 } 327 328 static int ecap_cnt_enable_write(struct counter_device *counter, 329 struct counter_count *count, u8 enable) 330 { 331 struct ecap_cnt_dev *ecap_dev = counter_priv(counter); 332 333 mutex_lock(&ecap_dev->lock); 334 335 if (enable == ecap_dev->enabled) 336 goto out; 337 338 if (enable) 339 ecap_cnt_capture_enable(counter); 340 else 341 ecap_cnt_capture_disable(counter); 342 ecap_dev->enabled = enable; 343 344 out: 345 mutex_unlock(&ecap_dev->lock); 346 347 return 0; 348 } 349 350 static const struct counter_ops ecap_cnt_ops = { 351 .count_read = ecap_cnt_count_read, 352 .count_write = ecap_cnt_count_write, 353 .function_read = ecap_cnt_function_read, 354 .action_read = ecap_cnt_action_read, 355 .watch_validate = ecap_cnt_watch_validate, 356 }; 357 358 static const enum counter_function ecap_cnt_functions[] = { 359 COUNTER_FUNCTION_INCREASE, 360 }; 361 362 static const enum counter_synapse_action ecap_cnt_clock_actions[] = { 363 COUNTER_SYNAPSE_ACTION_RISING_EDGE, 364 }; 365 366 static const enum counter_synapse_action ecap_cnt_input_actions[] = { 367 COUNTER_SYNAPSE_ACTION_NONE, 368 }; 369 370 static struct counter_comp ecap_cnt_clock_ext[] = { 371 COUNTER_COMP_FREQUENCY(ecap_cnt_clk_get_freq), 372 }; 373 374 static const enum counter_signal_polarity ecap_cnt_pol_avail[] = { 375 COUNTER_SIGNAL_POLARITY_POSITIVE, 376 COUNTER_SIGNAL_POLARITY_NEGATIVE, 377 }; 378 379 static DEFINE_COUNTER_AVAILABLE(ecap_cnt_pol_available, ecap_cnt_pol_avail); 380 static DEFINE_COUNTER_ARRAY_POLARITY(ecap_cnt_pol_array, ecap_cnt_pol_available, ECAP_NB_CEVT); 381 382 static struct counter_comp ecap_cnt_signal_ext[] = { 383 COUNTER_COMP_ARRAY_POLARITY(ecap_cnt_pol_read, ecap_cnt_pol_write, ecap_cnt_pol_array), 384 }; 385 386 static struct counter_signal ecap_cnt_signals[] = { 387 { 388 .id = ECAP_CLOCK_SIG, 389 .name = "Clock Signal", 390 .ext = ecap_cnt_clock_ext, 391 .num_ext = ARRAY_SIZE(ecap_cnt_clock_ext), 392 }, 393 { 394 .id = ECAP_INPUT_SIG, 395 .name = "Input Signal", 396 .ext = ecap_cnt_signal_ext, 397 .num_ext = ARRAY_SIZE(ecap_cnt_signal_ext), 398 }, 399 }; 400 401 static struct counter_synapse ecap_cnt_synapses[] = { 402 { 403 .actions_list = ecap_cnt_clock_actions, 404 .num_actions = ARRAY_SIZE(ecap_cnt_clock_actions), 405 .signal = &ecap_cnt_signals[ECAP_CLOCK_SIG], 406 }, 407 { 408 .actions_list = ecap_cnt_input_actions, 409 .num_actions = ARRAY_SIZE(ecap_cnt_input_actions), 410 .signal = &ecap_cnt_signals[ECAP_INPUT_SIG], 411 }, 412 }; 413 414 static DEFINE_COUNTER_ARRAY_CAPTURE(ecap_cnt_cap_array, ECAP_NB_CEVT); 415 416 static struct counter_comp ecap_cnt_count_ext[] = { 417 COUNTER_COMP_ARRAY_CAPTURE(ecap_cnt_cap_read, ecap_cnt_cap_write, ecap_cnt_cap_array), 418 COUNTER_COMP_COUNT_U64("num_overflows", ecap_cnt_nb_ovf_read, ecap_cnt_nb_ovf_write), 419 COUNTER_COMP_CEILING(ecap_cnt_ceiling_read, NULL), 420 COUNTER_COMP_ENABLE(ecap_cnt_enable_read, ecap_cnt_enable_write), 421 }; 422 423 static struct counter_count ecap_cnt_counts[] = { 424 { 425 .name = "Timestamp Counter", 426 .functions_list = ecap_cnt_functions, 427 .num_functions = ARRAY_SIZE(ecap_cnt_functions), 428 .synapses = ecap_cnt_synapses, 429 .num_synapses = ARRAY_SIZE(ecap_cnt_synapses), 430 .ext = ecap_cnt_count_ext, 431 .num_ext = ARRAY_SIZE(ecap_cnt_count_ext), 432 }, 433 }; 434 435 static irqreturn_t ecap_cnt_isr(int irq, void *dev_id) 436 { 437 struct counter_device *counter_dev = dev_id; 438 struct ecap_cnt_dev *ecap_dev = counter_priv(counter_dev); 439 unsigned int clr = 0; 440 unsigned int flg; 441 int i; 442 443 regmap_read(ecap_dev->regmap, ECAP_ECINT_EN_FLG_REG, &flg); 444 445 /* Check capture events */ 446 for (i = 0 ; i < ECAP_NB_CEVT ; i++) { 447 if (flg & ECAP_EVT_FLG_BIT(i)) { 448 counter_push_event(counter_dev, COUNTER_EVENT_CAPTURE, i); 449 clr |= ECAP_EVT_CLR_BIT(i); 450 } 451 } 452 453 /* Check counter overflow */ 454 if (flg & ECAP_EVT_FLG_BIT(ECAP_CNTOVF)) { 455 atomic_inc(&ecap_dev->nb_ovf); 456 for (i = 0 ; i < ECAP_NB_CEVT ; i++) 457 counter_push_event(counter_dev, COUNTER_EVENT_OVERFLOW, i); 458 clr |= ECAP_EVT_CLR_BIT(ECAP_CNTOVF); 459 } 460 461 clr |= ECAP_INT_CLR_BIT; 462 regmap_update_bits(ecap_dev->regmap, ECAP_ECINT_CLR_FRC_REG, ECAP_EVT_CLR_MASK, clr); 463 464 return IRQ_HANDLED; 465 } 466 467 static int ecap_cnt_probe(struct platform_device *pdev) 468 { 469 struct device *dev = &pdev->dev; 470 struct ecap_cnt_dev *ecap_dev; 471 struct counter_device *counter_dev; 472 void __iomem *mmio_base; 473 unsigned long clk_rate; 474 int ret; 475 476 counter_dev = devm_counter_alloc(dev, sizeof(*ecap_dev)); 477 if (!counter_dev) 478 return -ENOMEM; 479 480 counter_dev->name = ECAP_DRV_NAME; 481 counter_dev->parent = dev; 482 counter_dev->ops = &ecap_cnt_ops; 483 counter_dev->signals = ecap_cnt_signals; 484 counter_dev->num_signals = ARRAY_SIZE(ecap_cnt_signals); 485 counter_dev->counts = ecap_cnt_counts; 486 counter_dev->num_counts = ARRAY_SIZE(ecap_cnt_counts); 487 488 ecap_dev = counter_priv(counter_dev); 489 490 mutex_init(&ecap_dev->lock); 491 492 ecap_dev->clk = devm_clk_get_enabled(dev, "fck"); 493 if (IS_ERR(ecap_dev->clk)) 494 return dev_err_probe(dev, PTR_ERR(ecap_dev->clk), "failed to get clock\n"); 495 496 clk_rate = clk_get_rate(ecap_dev->clk); 497 if (!clk_rate) { 498 dev_err(dev, "failed to get clock rate\n"); 499 return -EINVAL; 500 } 501 502 mmio_base = devm_platform_ioremap_resource(pdev, 0); 503 if (IS_ERR(mmio_base)) 504 return PTR_ERR(mmio_base); 505 506 ecap_dev->regmap = devm_regmap_init_mmio(dev, mmio_base, &ecap_cnt_regmap_config); 507 if (IS_ERR(ecap_dev->regmap)) 508 return dev_err_probe(dev, PTR_ERR(ecap_dev->regmap), "failed to init regmap\n"); 509 510 ret = platform_get_irq(pdev, 0); 511 if (ret < 0) 512 return dev_err_probe(dev, ret, "failed to get irq\n"); 513 514 ret = devm_request_irq(dev, ret, ecap_cnt_isr, 0, pdev->name, counter_dev); 515 if (ret) 516 return ret; 517 518 platform_set_drvdata(pdev, counter_dev); 519 520 ret = devm_pm_runtime_enable(dev); 521 if (ret) 522 return ret; 523 524 ret = devm_counter_add(dev, counter_dev); 525 if (ret) 526 return dev_err_probe(dev, ret, "failed to add counter\n"); 527 528 return 0; 529 } 530 531 static void ecap_cnt_remove(struct platform_device *pdev) 532 { 533 struct counter_device *counter_dev = platform_get_drvdata(pdev); 534 struct ecap_cnt_dev *ecap_dev = counter_priv(counter_dev); 535 536 if (ecap_dev->enabled) 537 ecap_cnt_capture_disable(counter_dev); 538 } 539 540 static int ecap_cnt_suspend(struct device *dev) 541 { 542 struct counter_device *counter_dev = dev_get_drvdata(dev); 543 struct ecap_cnt_dev *ecap_dev = counter_priv(counter_dev); 544 545 /* If eCAP is running, stop capture then save timestamp counter */ 546 if (ecap_dev->enabled) { 547 /* 548 * Disabling capture has the following effects: 549 * - interrupts are disabled 550 * - loading of capture registers is disabled 551 * - timebase counter is stopped 552 */ 553 ecap_cnt_capture_disable(counter_dev); 554 ecap_dev->pm_ctx.time_cntr = ecap_cnt_count_get_val(counter_dev, ECAP_TSCNT_REG); 555 } 556 557 ecap_dev->pm_ctx.ev_mode = ecap_cnt_capture_get_evmode(counter_dev); 558 559 clk_disable(ecap_dev->clk); 560 561 return 0; 562 } 563 564 static int ecap_cnt_resume(struct device *dev) 565 { 566 struct counter_device *counter_dev = dev_get_drvdata(dev); 567 struct ecap_cnt_dev *ecap_dev = counter_priv(counter_dev); 568 int ret; 569 570 ret = clk_enable(ecap_dev->clk); 571 if (ret) { 572 dev_err(dev, "Cannot enable clock %d\n", ret); 573 return ret; 574 } 575 576 ecap_cnt_capture_set_evmode(counter_dev, ecap_dev->pm_ctx.ev_mode); 577 578 /* If eCAP was running, restore timestamp counter then run capture */ 579 if (ecap_dev->enabled) { 580 ecap_cnt_count_set_val(counter_dev, ECAP_TSCNT_REG, ecap_dev->pm_ctx.time_cntr); 581 ecap_cnt_capture_enable(counter_dev); 582 } 583 584 return 0; 585 } 586 587 static DEFINE_SIMPLE_DEV_PM_OPS(ecap_cnt_pm_ops, ecap_cnt_suspend, ecap_cnt_resume); 588 589 static const struct of_device_id ecap_cnt_of_match[] = { 590 { .compatible = "ti,am62-ecap-capture" }, 591 {}, 592 }; 593 MODULE_DEVICE_TABLE(of, ecap_cnt_of_match); 594 595 static struct platform_driver ecap_cnt_driver = { 596 .probe = ecap_cnt_probe, 597 .remove = ecap_cnt_remove, 598 .driver = { 599 .name = "ecap-capture", 600 .of_match_table = ecap_cnt_of_match, 601 .pm = pm_sleep_ptr(&ecap_cnt_pm_ops), 602 }, 603 }; 604 module_platform_driver(ecap_cnt_driver); 605 606 MODULE_DESCRIPTION("ECAP Capture driver"); 607 MODULE_AUTHOR("Julien Panis <jpanis@baylibre.com>"); 608 MODULE_LICENSE("GPL"); 609 MODULE_IMPORT_NS("COUNTER"); 610