1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * STM32 Timer Encoder and Counter driver 4 * 5 * Copyright (C) STMicroelectronics 2018 6 * 7 * Author: Benjamin Gaignard <benjamin.gaignard@st.com> 8 * 9 */ 10 #include <linux/counter.h> 11 #include <linux/interrupt.h> 12 #include <linux/mfd/stm32-timers.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/platform_device.h> 17 #include <linux/types.h> 18 19 #define TIM_CCMR_CCXS (BIT(8) | BIT(0)) 20 #define TIM_CCMR_MASK (TIM_CCMR_CC1S | TIM_CCMR_CC2S | \ 21 TIM_CCMR_IC1F | TIM_CCMR_IC2F) 22 #define TIM_CCER_MASK (TIM_CCER_CC1P | TIM_CCER_CC1NP | \ 23 TIM_CCER_CC2P | TIM_CCER_CC2NP) 24 25 #define STM32_CH1_SIG 0 26 #define STM32_CH2_SIG 1 27 #define STM32_CLOCK_SIG 2 28 #define STM32_CH3_SIG 3 29 #define STM32_CH4_SIG 4 30 31 struct stm32_timer_regs { 32 u32 cr1; 33 u32 cnt; 34 u32 smcr; 35 u32 arr; 36 }; 37 38 struct stm32_timer_cnt { 39 struct regmap *regmap; 40 struct clk *clk; 41 u32 max_arr; 42 bool enabled; 43 struct stm32_timer_regs bak; 44 bool has_encoder; 45 unsigned int nchannels; 46 unsigned int nr_irqs; 47 spinlock_t lock; /* protects nb_ovf */ 48 u64 nb_ovf; 49 }; 50 51 static const enum counter_function stm32_count_functions[] = { 52 COUNTER_FUNCTION_INCREASE, 53 COUNTER_FUNCTION_QUADRATURE_X2_A, 54 COUNTER_FUNCTION_QUADRATURE_X2_B, 55 COUNTER_FUNCTION_QUADRATURE_X4, 56 }; 57 58 static int stm32_count_read(struct counter_device *counter, 59 struct counter_count *count, u64 *val) 60 { 61 struct stm32_timer_cnt *const priv = counter_priv(counter); 62 u32 cnt; 63 64 regmap_read(priv->regmap, TIM_CNT, &cnt); 65 *val = cnt; 66 67 return 0; 68 } 69 70 static int stm32_count_write(struct counter_device *counter, 71 struct counter_count *count, const u64 val) 72 { 73 struct stm32_timer_cnt *const priv = counter_priv(counter); 74 u32 ceiling; 75 76 regmap_read(priv->regmap, TIM_ARR, &ceiling); 77 if (val > ceiling) 78 return -EINVAL; 79 80 return regmap_write(priv->regmap, TIM_CNT, val); 81 } 82 83 static int stm32_count_function_read(struct counter_device *counter, 84 struct counter_count *count, 85 enum counter_function *function) 86 { 87 struct stm32_timer_cnt *const priv = counter_priv(counter); 88 u32 smcr; 89 90 regmap_read(priv->regmap, TIM_SMCR, &smcr); 91 92 switch (smcr & TIM_SMCR_SMS) { 93 case TIM_SMCR_SMS_SLAVE_MODE_DISABLED: 94 *function = COUNTER_FUNCTION_INCREASE; 95 return 0; 96 case TIM_SMCR_SMS_ENCODER_MODE_1: 97 *function = COUNTER_FUNCTION_QUADRATURE_X2_A; 98 return 0; 99 case TIM_SMCR_SMS_ENCODER_MODE_2: 100 *function = COUNTER_FUNCTION_QUADRATURE_X2_B; 101 return 0; 102 case TIM_SMCR_SMS_ENCODER_MODE_3: 103 *function = COUNTER_FUNCTION_QUADRATURE_X4; 104 return 0; 105 default: 106 return -EINVAL; 107 } 108 } 109 110 static int stm32_count_function_write(struct counter_device *counter, 111 struct counter_count *count, 112 enum counter_function function) 113 { 114 struct stm32_timer_cnt *const priv = counter_priv(counter); 115 u32 cr1, sms; 116 117 switch (function) { 118 case COUNTER_FUNCTION_INCREASE: 119 sms = TIM_SMCR_SMS_SLAVE_MODE_DISABLED; 120 break; 121 case COUNTER_FUNCTION_QUADRATURE_X2_A: 122 if (!priv->has_encoder) 123 return -EOPNOTSUPP; 124 sms = TIM_SMCR_SMS_ENCODER_MODE_1; 125 break; 126 case COUNTER_FUNCTION_QUADRATURE_X2_B: 127 if (!priv->has_encoder) 128 return -EOPNOTSUPP; 129 sms = TIM_SMCR_SMS_ENCODER_MODE_2; 130 break; 131 case COUNTER_FUNCTION_QUADRATURE_X4: 132 if (!priv->has_encoder) 133 return -EOPNOTSUPP; 134 sms = TIM_SMCR_SMS_ENCODER_MODE_3; 135 break; 136 default: 137 return -EINVAL; 138 } 139 140 /* Store enable status */ 141 regmap_read(priv->regmap, TIM_CR1, &cr1); 142 143 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); 144 145 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms); 146 147 /* Make sure that registers are updated */ 148 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); 149 150 /* Restore the enable status */ 151 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1); 152 153 return 0; 154 } 155 156 static int stm32_count_direction_read(struct counter_device *counter, 157 struct counter_count *count, 158 enum counter_count_direction *direction) 159 { 160 struct stm32_timer_cnt *const priv = counter_priv(counter); 161 u32 cr1; 162 163 regmap_read(priv->regmap, TIM_CR1, &cr1); 164 *direction = (cr1 & TIM_CR1_DIR) ? COUNTER_COUNT_DIRECTION_BACKWARD : 165 COUNTER_COUNT_DIRECTION_FORWARD; 166 167 return 0; 168 } 169 170 static int stm32_count_ceiling_read(struct counter_device *counter, 171 struct counter_count *count, u64 *ceiling) 172 { 173 struct stm32_timer_cnt *const priv = counter_priv(counter); 174 u32 arr; 175 176 regmap_read(priv->regmap, TIM_ARR, &arr); 177 178 *ceiling = arr; 179 180 return 0; 181 } 182 183 static int stm32_count_ceiling_write(struct counter_device *counter, 184 struct counter_count *count, u64 ceiling) 185 { 186 struct stm32_timer_cnt *const priv = counter_priv(counter); 187 188 if (ceiling > priv->max_arr) 189 return -ERANGE; 190 191 /* TIMx_ARR register shouldn't be buffered (ARPE=0) */ 192 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0); 193 regmap_write(priv->regmap, TIM_ARR, ceiling); 194 195 return 0; 196 } 197 198 static int stm32_count_enable_read(struct counter_device *counter, 199 struct counter_count *count, u8 *enable) 200 { 201 struct stm32_timer_cnt *const priv = counter_priv(counter); 202 u32 cr1; 203 204 regmap_read(priv->regmap, TIM_CR1, &cr1); 205 206 *enable = cr1 & TIM_CR1_CEN; 207 208 return 0; 209 } 210 211 static int stm32_count_enable_write(struct counter_device *counter, 212 struct counter_count *count, u8 enable) 213 { 214 struct stm32_timer_cnt *const priv = counter_priv(counter); 215 u32 cr1; 216 int ret; 217 218 if (enable) { 219 regmap_read(priv->regmap, TIM_CR1, &cr1); 220 if (!(cr1 & TIM_CR1_CEN)) { 221 ret = clk_enable(priv->clk); 222 if (ret) { 223 dev_err(counter->parent, "Cannot enable clock %d\n", ret); 224 return ret; 225 } 226 } 227 228 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 229 TIM_CR1_CEN); 230 } else { 231 regmap_read(priv->regmap, TIM_CR1, &cr1); 232 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); 233 if (cr1 & TIM_CR1_CEN) 234 clk_disable(priv->clk); 235 } 236 237 /* Keep enabled state to properly handle low power states */ 238 priv->enabled = enable; 239 240 return 0; 241 } 242 243 static int stm32_count_prescaler_read(struct counter_device *counter, 244 struct counter_count *count, u64 *prescaler) 245 { 246 struct stm32_timer_cnt *const priv = counter_priv(counter); 247 u32 psc; 248 249 regmap_read(priv->regmap, TIM_PSC, &psc); 250 251 *prescaler = psc + 1; 252 253 return 0; 254 } 255 256 static int stm32_count_prescaler_write(struct counter_device *counter, 257 struct counter_count *count, u64 prescaler) 258 { 259 struct stm32_timer_cnt *const priv = counter_priv(counter); 260 u32 psc; 261 262 if (!prescaler || prescaler > MAX_TIM_PSC + 1) 263 return -ERANGE; 264 265 psc = prescaler - 1; 266 267 return regmap_write(priv->regmap, TIM_PSC, psc); 268 } 269 270 static int stm32_count_cap_read(struct counter_device *counter, 271 struct counter_count *count, 272 size_t ch, u64 *cap) 273 { 274 struct stm32_timer_cnt *const priv = counter_priv(counter); 275 u32 ccrx; 276 277 if (ch >= priv->nchannels) 278 return -EOPNOTSUPP; 279 280 switch (ch) { 281 case 0: 282 regmap_read(priv->regmap, TIM_CCR1, &ccrx); 283 break; 284 case 1: 285 regmap_read(priv->regmap, TIM_CCR2, &ccrx); 286 break; 287 case 2: 288 regmap_read(priv->regmap, TIM_CCR3, &ccrx); 289 break; 290 case 3: 291 regmap_read(priv->regmap, TIM_CCR4, &ccrx); 292 break; 293 default: 294 return -EINVAL; 295 } 296 297 dev_dbg(counter->parent, "CCR%zu: 0x%08x\n", ch + 1, ccrx); 298 299 *cap = ccrx; 300 301 return 0; 302 } 303 304 static int stm32_count_nb_ovf_read(struct counter_device *counter, 305 struct counter_count *count, u64 *val) 306 { 307 struct stm32_timer_cnt *const priv = counter_priv(counter); 308 unsigned long irqflags; 309 310 spin_lock_irqsave(&priv->lock, irqflags); 311 *val = priv->nb_ovf; 312 spin_unlock_irqrestore(&priv->lock, irqflags); 313 314 return 0; 315 } 316 317 static int stm32_count_nb_ovf_write(struct counter_device *counter, 318 struct counter_count *count, u64 val) 319 { 320 struct stm32_timer_cnt *const priv = counter_priv(counter); 321 unsigned long irqflags; 322 323 spin_lock_irqsave(&priv->lock, irqflags); 324 priv->nb_ovf = val; 325 spin_unlock_irqrestore(&priv->lock, irqflags); 326 327 return 0; 328 } 329 330 static DEFINE_COUNTER_ARRAY_CAPTURE(stm32_count_cap_array, 4); 331 332 static struct counter_comp stm32_count_ext[] = { 333 COUNTER_COMP_DIRECTION(stm32_count_direction_read), 334 COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write), 335 COUNTER_COMP_CEILING(stm32_count_ceiling_read, 336 stm32_count_ceiling_write), 337 COUNTER_COMP_COUNT_U64("prescaler", stm32_count_prescaler_read, 338 stm32_count_prescaler_write), 339 COUNTER_COMP_ARRAY_CAPTURE(stm32_count_cap_read, NULL, stm32_count_cap_array), 340 COUNTER_COMP_COUNT_U64("num_overflows", stm32_count_nb_ovf_read, stm32_count_nb_ovf_write), 341 }; 342 343 static const enum counter_synapse_action stm32_clock_synapse_actions[] = { 344 COUNTER_SYNAPSE_ACTION_RISING_EDGE, 345 }; 346 347 static const enum counter_synapse_action stm32_synapse_actions[] = { 348 COUNTER_SYNAPSE_ACTION_NONE, 349 COUNTER_SYNAPSE_ACTION_BOTH_EDGES 350 }; 351 352 static int stm32_action_read(struct counter_device *counter, 353 struct counter_count *count, 354 struct counter_synapse *synapse, 355 enum counter_synapse_action *action) 356 { 357 enum counter_function function; 358 int err; 359 360 err = stm32_count_function_read(counter, count, &function); 361 if (err) 362 return err; 363 364 switch (function) { 365 case COUNTER_FUNCTION_INCREASE: 366 /* counts on internal clock when CEN=1 */ 367 if (synapse->signal->id == STM32_CLOCK_SIG) 368 *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE; 369 else 370 *action = COUNTER_SYNAPSE_ACTION_NONE; 371 return 0; 372 case COUNTER_FUNCTION_QUADRATURE_X2_A: 373 /* counts up/down on TI1FP1 edge depending on TI2FP2 level */ 374 if (synapse->signal->id == STM32_CH1_SIG) 375 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; 376 else 377 *action = COUNTER_SYNAPSE_ACTION_NONE; 378 return 0; 379 case COUNTER_FUNCTION_QUADRATURE_X2_B: 380 /* counts up/down on TI2FP2 edge depending on TI1FP1 level */ 381 if (synapse->signal->id == STM32_CH2_SIG) 382 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; 383 else 384 *action = COUNTER_SYNAPSE_ACTION_NONE; 385 return 0; 386 case COUNTER_FUNCTION_QUADRATURE_X4: 387 /* counts up/down on both TI1FP1 and TI2FP2 edges */ 388 if (synapse->signal->id == STM32_CH1_SIG || synapse->signal->id == STM32_CH2_SIG) 389 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; 390 else 391 *action = COUNTER_SYNAPSE_ACTION_NONE; 392 return 0; 393 default: 394 return -EINVAL; 395 } 396 } 397 398 struct stm32_count_cc_regs { 399 u32 ccmr_reg; 400 u32 ccmr_mask; 401 u32 ccmr_bits; 402 u32 ccer_bits; 403 }; 404 405 static const struct stm32_count_cc_regs stm32_cc[] = { 406 { TIM_CCMR1, TIM_CCMR_CC1S, TIM_CCMR_CC1S_TI1, 407 TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC1NP }, 408 { TIM_CCMR1, TIM_CCMR_CC2S, TIM_CCMR_CC2S_TI2, 409 TIM_CCER_CC2E | TIM_CCER_CC2P | TIM_CCER_CC2NP }, 410 { TIM_CCMR2, TIM_CCMR_CC3S, TIM_CCMR_CC3S_TI3, 411 TIM_CCER_CC3E | TIM_CCER_CC3P | TIM_CCER_CC3NP }, 412 { TIM_CCMR2, TIM_CCMR_CC4S, TIM_CCMR_CC4S_TI4, 413 TIM_CCER_CC4E | TIM_CCER_CC4P | TIM_CCER_CC4NP }, 414 }; 415 416 static int stm32_count_capture_configure(struct counter_device *counter, unsigned int ch, 417 bool enable) 418 { 419 struct stm32_timer_cnt *const priv = counter_priv(counter); 420 const struct stm32_count_cc_regs *cc; 421 u32 ccmr, ccer; 422 423 if (ch >= ARRAY_SIZE(stm32_cc) || ch >= priv->nchannels) { 424 dev_err(counter->parent, "invalid ch: %d\n", ch); 425 return -EINVAL; 426 } 427 428 cc = &stm32_cc[ch]; 429 430 /* 431 * configure channel in input capture mode, map channel 1 on TI1, channel2 on TI2... 432 * Select both edges / non-inverted to trigger a capture. 433 */ 434 if (enable) { 435 /* first clear possibly latched capture flag upon enabling */ 436 if (!regmap_test_bits(priv->regmap, TIM_CCER, cc->ccer_bits)) 437 regmap_write(priv->regmap, TIM_SR, ~TIM_SR_CC_IF(ch)); 438 regmap_update_bits(priv->regmap, cc->ccmr_reg, cc->ccmr_mask, 439 cc->ccmr_bits); 440 regmap_set_bits(priv->regmap, TIM_CCER, cc->ccer_bits); 441 } else { 442 regmap_clear_bits(priv->regmap, TIM_CCER, cc->ccer_bits); 443 regmap_clear_bits(priv->regmap, cc->ccmr_reg, cc->ccmr_mask); 444 } 445 446 regmap_read(priv->regmap, cc->ccmr_reg, &ccmr); 447 regmap_read(priv->regmap, TIM_CCER, &ccer); 448 dev_dbg(counter->parent, "%s(%s) ch%d 0x%08x 0x%08x\n", __func__, enable ? "ena" : "dis", 449 ch, ccmr, ccer); 450 451 return 0; 452 } 453 454 static int stm32_count_events_configure(struct counter_device *counter) 455 { 456 struct stm32_timer_cnt *const priv = counter_priv(counter); 457 struct counter_event_node *event_node; 458 u32 dier = 0; 459 int i, ret; 460 461 list_for_each_entry(event_node, &counter->events_list, l) { 462 switch (event_node->event) { 463 case COUNTER_EVENT_OVERFLOW_UNDERFLOW: 464 /* first clear possibly latched UIF before enabling */ 465 if (!regmap_test_bits(priv->regmap, TIM_DIER, TIM_DIER_UIE)) 466 regmap_write(priv->regmap, TIM_SR, (u32)~TIM_SR_UIF); 467 dier |= TIM_DIER_UIE; 468 break; 469 case COUNTER_EVENT_CAPTURE: 470 ret = stm32_count_capture_configure(counter, event_node->channel, true); 471 if (ret) 472 return ret; 473 dier |= TIM_DIER_CCxIE(event_node->channel + 1); 474 break; 475 default: 476 /* should never reach this path */ 477 return -EINVAL; 478 } 479 } 480 481 /* Enable / disable all events at once, from events_list, so write all DIER bits */ 482 regmap_write(priv->regmap, TIM_DIER, dier); 483 484 /* check for disabled capture events */ 485 for (i = 0 ; i < priv->nchannels; i++) { 486 if (!(dier & TIM_DIER_CCxIE(i + 1))) { 487 ret = stm32_count_capture_configure(counter, i, false); 488 if (ret) 489 return ret; 490 } 491 } 492 493 return 0; 494 } 495 496 static int stm32_count_watch_validate(struct counter_device *counter, 497 const struct counter_watch *watch) 498 { 499 struct stm32_timer_cnt *const priv = counter_priv(counter); 500 501 /* Interrupts are optional */ 502 if (!priv->nr_irqs) 503 return -EOPNOTSUPP; 504 505 switch (watch->event) { 506 case COUNTER_EVENT_CAPTURE: 507 if (watch->channel >= priv->nchannels) { 508 dev_err(counter->parent, "Invalid channel %d\n", watch->channel); 509 return -EINVAL; 510 } 511 return 0; 512 case COUNTER_EVENT_OVERFLOW_UNDERFLOW: 513 return 0; 514 default: 515 return -EINVAL; 516 } 517 } 518 519 static const struct counter_ops stm32_timer_cnt_ops = { 520 .count_read = stm32_count_read, 521 .count_write = stm32_count_write, 522 .function_read = stm32_count_function_read, 523 .function_write = stm32_count_function_write, 524 .action_read = stm32_action_read, 525 .events_configure = stm32_count_events_configure, 526 .watch_validate = stm32_count_watch_validate, 527 }; 528 529 static int stm32_count_clk_get_freq(struct counter_device *counter, 530 struct counter_signal *signal, u64 *freq) 531 { 532 struct stm32_timer_cnt *const priv = counter_priv(counter); 533 534 *freq = clk_get_rate(priv->clk); 535 536 return 0; 537 } 538 539 static struct counter_comp stm32_count_clock_ext[] = { 540 COUNTER_COMP_FREQUENCY(stm32_count_clk_get_freq), 541 }; 542 543 static struct counter_signal stm32_signals[] = { 544 /* 545 * Need to declare all the signals as a static array, and keep the signals order here, 546 * even if they're unused or unexisting on some timer instances. It's an abstraction, 547 * e.g. high level view of the counter features. 548 * 549 * Userspace programs may rely on signal0 to be "Channel 1", signal1 to be "Channel 2", 550 * and so on. When a signal is unexisting, the COUNTER_SYNAPSE_ACTION_NONE can be used, 551 * to indicate that a signal doesn't affect the counter. 552 */ 553 { 554 .id = STM32_CH1_SIG, 555 .name = "Channel 1" 556 }, 557 { 558 .id = STM32_CH2_SIG, 559 .name = "Channel 2" 560 }, 561 { 562 .id = STM32_CLOCK_SIG, 563 .name = "Clock", 564 .ext = stm32_count_clock_ext, 565 .num_ext = ARRAY_SIZE(stm32_count_clock_ext), 566 }, 567 { 568 .id = STM32_CH3_SIG, 569 .name = "Channel 3" 570 }, 571 { 572 .id = STM32_CH4_SIG, 573 .name = "Channel 4" 574 }, 575 }; 576 577 static struct counter_synapse stm32_count_synapses[] = { 578 { 579 .actions_list = stm32_synapse_actions, 580 .num_actions = ARRAY_SIZE(stm32_synapse_actions), 581 .signal = &stm32_signals[STM32_CH1_SIG] 582 }, 583 { 584 .actions_list = stm32_synapse_actions, 585 .num_actions = ARRAY_SIZE(stm32_synapse_actions), 586 .signal = &stm32_signals[STM32_CH2_SIG] 587 }, 588 { 589 .actions_list = stm32_clock_synapse_actions, 590 .num_actions = ARRAY_SIZE(stm32_clock_synapse_actions), 591 .signal = &stm32_signals[STM32_CLOCK_SIG] 592 }, 593 { 594 .actions_list = stm32_synapse_actions, 595 .num_actions = ARRAY_SIZE(stm32_synapse_actions), 596 .signal = &stm32_signals[STM32_CH3_SIG] 597 }, 598 { 599 .actions_list = stm32_synapse_actions, 600 .num_actions = ARRAY_SIZE(stm32_synapse_actions), 601 .signal = &stm32_signals[STM32_CH4_SIG] 602 }, 603 }; 604 605 static struct counter_count stm32_counts = { 606 .id = 0, 607 .name = "STM32 Timer Counter", 608 .functions_list = stm32_count_functions, 609 .num_functions = ARRAY_SIZE(stm32_count_functions), 610 .synapses = stm32_count_synapses, 611 .num_synapses = ARRAY_SIZE(stm32_count_synapses), 612 .ext = stm32_count_ext, 613 .num_ext = ARRAY_SIZE(stm32_count_ext) 614 }; 615 616 static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr) 617 { 618 struct counter_device *counter = ptr; 619 struct stm32_timer_cnt *const priv = counter_priv(counter); 620 u32 clr = GENMASK(31, 0); /* SR flags can be cleared by writing 0 (wr 1 has no effect) */ 621 u32 sr, dier; 622 int i; 623 624 regmap_read(priv->regmap, TIM_SR, &sr); 625 regmap_read(priv->regmap, TIM_DIER, &dier); 626 /* 627 * Some status bits in SR don't match with the enable bits in DIER. Only take care of 628 * the possibly enabled bits in DIER (that matches in between SR and DIER). 629 */ 630 dier &= (TIM_DIER_UIE | TIM_DIER_CC1IE | TIM_DIER_CC2IE | TIM_DIER_CC3IE | TIM_DIER_CC4IE); 631 sr &= dier; 632 633 if (sr & TIM_SR_UIF) { 634 spin_lock(&priv->lock); 635 priv->nb_ovf++; 636 spin_unlock(&priv->lock); 637 counter_push_event(counter, COUNTER_EVENT_OVERFLOW_UNDERFLOW, 0); 638 dev_dbg(counter->parent, "COUNTER_EVENT_OVERFLOW_UNDERFLOW\n"); 639 /* SR flags can be cleared by writing 0, only clear relevant flag */ 640 clr &= ~TIM_SR_UIF; 641 } 642 643 /* Check capture events */ 644 for (i = 0 ; i < priv->nchannels; i++) { 645 if (sr & TIM_SR_CC_IF(i)) { 646 counter_push_event(counter, COUNTER_EVENT_CAPTURE, i); 647 clr &= ~TIM_SR_CC_IF(i); 648 dev_dbg(counter->parent, "COUNTER_EVENT_CAPTURE, %d\n", i); 649 } 650 } 651 652 regmap_write(priv->regmap, TIM_SR, clr); 653 654 return IRQ_HANDLED; 655 }; 656 657 static void stm32_timer_cnt_detect_channels(struct device *dev, 658 struct stm32_timer_cnt *priv) 659 { 660 u32 ccer, ccer_backup; 661 662 regmap_read(priv->regmap, TIM_CCER, &ccer_backup); 663 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE); 664 regmap_read(priv->regmap, TIM_CCER, &ccer); 665 regmap_write(priv->regmap, TIM_CCER, ccer_backup); 666 priv->nchannels = hweight32(ccer & TIM_CCER_CCXE); 667 668 dev_dbg(dev, "has %d cc channels\n", priv->nchannels); 669 } 670 671 /* encoder supported on TIM1 TIM2 TIM3 TIM4 TIM5 TIM8 TIM20 */ 672 #define STM32_TIM_ENCODER_SUPPORTED (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(7) | \ 673 BIT(19)) 674 675 static const char * const stm32_timer_trigger_compat[] = { 676 "st,stm32-timer-trigger", 677 "st,stm32h7-timer-trigger", 678 "st,stm32mp25-timer-trigger", 679 }; 680 681 static int stm32_timer_cnt_probe_encoder(struct device *dev, 682 struct stm32_timer_cnt *priv) 683 { 684 struct device *parent = dev->parent; 685 struct device_node *tnode = NULL, *pnode = parent->of_node; 686 int i, ret; 687 u32 idx; 688 689 /* 690 * Need to retrieve the trigger node index from DT, to be able 691 * to determine if the counter supports encoder mode. It also 692 * enforce backward compatibility, and allow to support other 693 * counter modes in this driver (when the timer doesn't support 694 * encoder). 695 */ 696 for (i = 0; i < ARRAY_SIZE(stm32_timer_trigger_compat) && !tnode; i++) 697 tnode = of_get_compatible_child(pnode, stm32_timer_trigger_compat[i]); 698 if (!tnode) { 699 dev_err(dev, "Can't find trigger node\n"); 700 return -ENODATA; 701 } 702 703 ret = of_property_read_u32(tnode, "reg", &idx); 704 of_node_put(tnode); 705 if (ret) { 706 dev_err(dev, "Can't get index (%d)\n", ret); 707 return ret; 708 } 709 710 priv->has_encoder = !!(STM32_TIM_ENCODER_SUPPORTED & BIT(idx)); 711 712 dev_dbg(dev, "encoder support: %s\n", priv->has_encoder ? "yes" : "no"); 713 714 return 0; 715 } 716 717 static int stm32_timer_cnt_probe(struct platform_device *pdev) 718 { 719 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); 720 struct device *dev = &pdev->dev; 721 struct stm32_timer_cnt *priv; 722 struct counter_device *counter; 723 int i, ret; 724 725 if (IS_ERR_OR_NULL(ddata)) 726 return -EINVAL; 727 728 counter = devm_counter_alloc(dev, sizeof(*priv)); 729 if (!counter) 730 return -ENOMEM; 731 732 priv = counter_priv(counter); 733 734 priv->regmap = ddata->regmap; 735 priv->clk = ddata->clk; 736 priv->max_arr = ddata->max_arr; 737 priv->nr_irqs = ddata->nr_irqs; 738 739 ret = stm32_timer_cnt_probe_encoder(dev, priv); 740 if (ret) 741 return ret; 742 743 stm32_timer_cnt_detect_channels(dev, priv); 744 745 counter->name = dev_name(dev); 746 counter->parent = dev; 747 counter->ops = &stm32_timer_cnt_ops; 748 counter->counts = &stm32_counts; 749 counter->num_counts = 1; 750 counter->signals = stm32_signals; 751 counter->num_signals = ARRAY_SIZE(stm32_signals); 752 753 spin_lock_init(&priv->lock); 754 755 platform_set_drvdata(pdev, priv); 756 757 /* STM32 Timers can have either 1 global, or 4 dedicated interrupts (optional) */ 758 if (priv->nr_irqs == 1) { 759 /* All events reported through the global interrupt */ 760 ret = devm_request_irq(&pdev->dev, ddata->irq[0], stm32_timer_cnt_isr, 761 0, dev_name(dev), counter); 762 if (ret) { 763 dev_err(dev, "Failed to request irq %d (err %d)\n", 764 ddata->irq[0], ret); 765 return ret; 766 } 767 } else { 768 for (i = 0; i < priv->nr_irqs; i++) { 769 /* 770 * Only take care of update IRQ for overflow events, and cc for 771 * capture events. 772 */ 773 if (i != STM32_TIMERS_IRQ_UP && i != STM32_TIMERS_IRQ_CC) 774 continue; 775 776 ret = devm_request_irq(&pdev->dev, ddata->irq[i], stm32_timer_cnt_isr, 777 0, dev_name(dev), counter); 778 if (ret) { 779 dev_err(dev, "Failed to request irq %d (err %d)\n", 780 ddata->irq[i], ret); 781 return ret; 782 } 783 } 784 } 785 786 /* Reset input selector to its default input */ 787 regmap_write(priv->regmap, TIM_TISEL, 0x0); 788 789 /* Register Counter device */ 790 ret = devm_counter_add(dev, counter); 791 if (ret < 0) 792 dev_err_probe(dev, ret, "Failed to add counter\n"); 793 794 return ret; 795 } 796 797 static int __maybe_unused stm32_timer_cnt_suspend(struct device *dev) 798 { 799 struct stm32_timer_cnt *priv = dev_get_drvdata(dev); 800 801 /* Only take care of enabled counter: don't disturb other MFD child */ 802 if (priv->enabled) { 803 /* Backup registers that may get lost in low power mode */ 804 regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr); 805 regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr); 806 regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt); 807 regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1); 808 809 /* Disable the counter */ 810 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); 811 clk_disable(priv->clk); 812 } 813 814 return pinctrl_pm_select_sleep_state(dev); 815 } 816 817 static int __maybe_unused stm32_timer_cnt_resume(struct device *dev) 818 { 819 struct stm32_timer_cnt *priv = dev_get_drvdata(dev); 820 int ret; 821 822 ret = pinctrl_pm_select_default_state(dev); 823 if (ret) 824 return ret; 825 826 if (priv->enabled) { 827 ret = clk_enable(priv->clk); 828 if (ret) { 829 dev_err(dev, "Cannot enable clock %d\n", ret); 830 return ret; 831 } 832 833 /* Restore registers that may have been lost */ 834 regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr); 835 regmap_write(priv->regmap, TIM_ARR, priv->bak.arr); 836 regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt); 837 838 /* Also re-enables the counter */ 839 regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1); 840 } 841 842 return 0; 843 } 844 845 static SIMPLE_DEV_PM_OPS(stm32_timer_cnt_pm_ops, stm32_timer_cnt_suspend, 846 stm32_timer_cnt_resume); 847 848 static const struct of_device_id stm32_timer_cnt_of_match[] = { 849 { .compatible = "st,stm32-timer-counter", }, 850 { .compatible = "st,stm32mp25-timer-counter", }, 851 {}, 852 }; 853 MODULE_DEVICE_TABLE(of, stm32_timer_cnt_of_match); 854 855 static struct platform_driver stm32_timer_cnt_driver = { 856 .probe = stm32_timer_cnt_probe, 857 .driver = { 858 .name = "stm32-timer-counter", 859 .of_match_table = stm32_timer_cnt_of_match, 860 .pm = &stm32_timer_cnt_pm_ops, 861 }, 862 }; 863 module_platform_driver(stm32_timer_cnt_driver); 864 865 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); 866 MODULE_ALIAS("platform:stm32-timer-counter"); 867 MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver"); 868 MODULE_LICENSE("GPL v2"); 869 MODULE_IMPORT_NS("COUNTER"); 870