xref: /linux/drivers/counter/104-quad-8.c (revision fc6dfd5547794b0bf10790576a9d97443d975439)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Counter driver for the ACCES 104-QUAD-8
4  * Copyright (C) 2016 William Breathitt Gray
5  *
6  * This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4.
7  */
8 #include <linux/bitops.h>
9 #include <linux/counter.h>
10 #include <linux/device.h>
11 #include <linux/errno.h>
12 #include <linux/io.h>
13 #include <linux/ioport.h>
14 #include <linux/interrupt.h>
15 #include <linux/isa.h>
16 #include <linux/kernel.h>
17 #include <linux/list.h>
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/types.h>
21 #include <linux/spinlock.h>
22 
23 #define QUAD8_EXTENT 32
24 
25 static unsigned int base[max_num_isa_dev(QUAD8_EXTENT)];
26 static unsigned int num_quad8;
27 module_param_hw_array(base, uint, ioport, &num_quad8, 0);
28 MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
29 
30 static unsigned int irq[max_num_isa_dev(QUAD8_EXTENT)];
31 static unsigned int num_irq;
32 module_param_hw_array(irq, uint, irq, &num_irq, 0);
33 MODULE_PARM_DESC(irq, "ACCES 104-QUAD-8 interrupt line numbers");
34 
35 #define QUAD8_NUM_COUNTERS 8
36 
37 /**
38  * struct channel_reg - channel register structure
39  * @data:	Count data
40  * @control:	Channel flags and control
41  */
42 struct channel_reg {
43 	u8 data;
44 	u8 control;
45 };
46 
47 /**
48  * struct quad8_reg - device register structure
49  * @channel:		quadrature counter data and control
50  * @interrupt_status:	channel interrupt status
51  * @channel_oper:	enable/reset counters and interrupt functions
52  * @index_interrupt:	enable channel interrupts
53  * @reserved:		reserved for Factory Use
54  * @index_input_levels:	index signal logical input level
55  * @cable_status:	differential encoder cable status
56  */
57 struct quad8_reg {
58 	struct channel_reg channel[QUAD8_NUM_COUNTERS];
59 	u8 interrupt_status;
60 	u8 channel_oper;
61 	u8 index_interrupt;
62 	u8 reserved[3];
63 	u8 index_input_levels;
64 	u8 cable_status;
65 };
66 
67 /**
68  * struct quad8 - device private data structure
69  * @lock:		lock to prevent clobbering device states during R/W ops
70  * @counter:		instance of the counter_device
71  * @fck_prescaler:	array of filter clock prescaler configurations
72  * @preset:		array of preset values
73  * @count_mode:		array of count mode configurations
74  * @quadrature_mode:	array of quadrature mode configurations
75  * @quadrature_scale:	array of quadrature mode scale configurations
76  * @ab_enable:		array of A and B inputs enable configurations
77  * @preset_enable:	array of set_to_preset_on_index attribute configurations
78  * @irq_trigger:	array of current IRQ trigger function configurations
79  * @synchronous_mode:	array of index function synchronous mode configurations
80  * @index_polarity:	array of index function polarity configurations
81  * @cable_fault_enable:	differential encoder cable status enable configurations
82  * @reg:		I/O address offset for the device registers
83  */
84 struct quad8 {
85 	spinlock_t lock;
86 	unsigned int fck_prescaler[QUAD8_NUM_COUNTERS];
87 	unsigned int preset[QUAD8_NUM_COUNTERS];
88 	unsigned int count_mode[QUAD8_NUM_COUNTERS];
89 	unsigned int quadrature_mode[QUAD8_NUM_COUNTERS];
90 	unsigned int quadrature_scale[QUAD8_NUM_COUNTERS];
91 	unsigned int ab_enable[QUAD8_NUM_COUNTERS];
92 	unsigned int preset_enable[QUAD8_NUM_COUNTERS];
93 	unsigned int irq_trigger[QUAD8_NUM_COUNTERS];
94 	unsigned int synchronous_mode[QUAD8_NUM_COUNTERS];
95 	unsigned int index_polarity[QUAD8_NUM_COUNTERS];
96 	unsigned int cable_fault_enable;
97 	struct quad8_reg __iomem *reg;
98 };
99 
100 /* Borrow Toggle flip-flop */
101 #define QUAD8_FLAG_BT BIT(0)
102 /* Carry Toggle flip-flop */
103 #define QUAD8_FLAG_CT BIT(1)
104 /* Error flag */
105 #define QUAD8_FLAG_E BIT(4)
106 /* Up/Down flag */
107 #define QUAD8_FLAG_UD BIT(5)
108 /* Reset and Load Signal Decoders */
109 #define QUAD8_CTR_RLD 0x00
110 /* Counter Mode Register */
111 #define QUAD8_CTR_CMR 0x20
112 /* Input / Output Control Register */
113 #define QUAD8_CTR_IOR 0x40
114 /* Index Control Register */
115 #define QUAD8_CTR_IDR 0x60
116 /* Reset Byte Pointer (three byte data pointer) */
117 #define QUAD8_RLD_RESET_BP 0x01
118 /* Reset Counter */
119 #define QUAD8_RLD_RESET_CNTR 0x02
120 /* Reset Borrow Toggle, Carry Toggle, Compare Toggle, and Sign flags */
121 #define QUAD8_RLD_RESET_FLAGS 0x04
122 /* Reset Error flag */
123 #define QUAD8_RLD_RESET_E 0x06
124 /* Preset Register to Counter */
125 #define QUAD8_RLD_PRESET_CNTR 0x08
126 /* Transfer Counter to Output Latch */
127 #define QUAD8_RLD_CNTR_OUT 0x10
128 /* Transfer Preset Register LSB to FCK Prescaler */
129 #define QUAD8_RLD_PRESET_PSC 0x18
130 #define QUAD8_CHAN_OP_RESET_COUNTERS 0x01
131 #define QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC 0x04
132 #define QUAD8_CMR_QUADRATURE_X1 0x08
133 #define QUAD8_CMR_QUADRATURE_X2 0x10
134 #define QUAD8_CMR_QUADRATURE_X4 0x18
135 
136 static int quad8_signal_read(struct counter_device *counter,
137 			     struct counter_signal *signal,
138 			     enum counter_signal_level *level)
139 {
140 	const struct quad8 *const priv = counter_priv(counter);
141 	unsigned int state;
142 
143 	/* Only Index signal levels can be read */
144 	if (signal->id < 16)
145 		return -EINVAL;
146 
147 	state = ioread8(&priv->reg->index_input_levels) & BIT(signal->id - 16);
148 
149 	*level = (state) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;
150 
151 	return 0;
152 }
153 
154 static int quad8_count_read(struct counter_device *counter,
155 			    struct counter_count *count, u64 *val)
156 {
157 	struct quad8 *const priv = counter_priv(counter);
158 	struct channel_reg __iomem *const chan = priv->reg->channel + count->id;
159 	unsigned int flags;
160 	unsigned int borrow;
161 	unsigned int carry;
162 	unsigned long irqflags;
163 	int i;
164 
165 	flags = ioread8(&chan->control);
166 	borrow = flags & QUAD8_FLAG_BT;
167 	carry = !!(flags & QUAD8_FLAG_CT);
168 
169 	/* Borrow XOR Carry effectively doubles count range */
170 	*val = (unsigned long)(borrow ^ carry) << 24;
171 
172 	spin_lock_irqsave(&priv->lock, irqflags);
173 
174 	/* Reset Byte Pointer; transfer Counter to Output Latch */
175 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
176 		 &chan->control);
177 
178 	for (i = 0; i < 3; i++)
179 		*val |= (unsigned long)ioread8(&chan->data) << (8 * i);
180 
181 	spin_unlock_irqrestore(&priv->lock, irqflags);
182 
183 	return 0;
184 }
185 
186 static int quad8_count_write(struct counter_device *counter,
187 			     struct counter_count *count, u64 val)
188 {
189 	struct quad8 *const priv = counter_priv(counter);
190 	struct channel_reg __iomem *const chan = priv->reg->channel + count->id;
191 	unsigned long irqflags;
192 	int i;
193 
194 	/* Only 24-bit values are supported */
195 	if (val > 0xFFFFFF)
196 		return -ERANGE;
197 
198 	spin_lock_irqsave(&priv->lock, irqflags);
199 
200 	/* Reset Byte Pointer */
201 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
202 
203 	/* Counter can only be set via Preset Register */
204 	for (i = 0; i < 3; i++)
205 		iowrite8(val >> (8 * i), &chan->data);
206 
207 	/* Transfer Preset Register to Counter */
208 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, &chan->control);
209 
210 	/* Reset Byte Pointer */
211 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
212 
213 	/* Set Preset Register back to original value */
214 	val = priv->preset[count->id];
215 	for (i = 0; i < 3; i++)
216 		iowrite8(val >> (8 * i), &chan->data);
217 
218 	/* Reset Borrow, Carry, Compare, and Sign flags */
219 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control);
220 	/* Reset Error flag */
221 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control);
222 
223 	spin_unlock_irqrestore(&priv->lock, irqflags);
224 
225 	return 0;
226 }
227 
228 static const enum counter_function quad8_count_functions_list[] = {
229 	COUNTER_FUNCTION_PULSE_DIRECTION,
230 	COUNTER_FUNCTION_QUADRATURE_X1_A,
231 	COUNTER_FUNCTION_QUADRATURE_X2_A,
232 	COUNTER_FUNCTION_QUADRATURE_X4,
233 };
234 
235 static int quad8_function_read(struct counter_device *counter,
236 			       struct counter_count *count,
237 			       enum counter_function *function)
238 {
239 	struct quad8 *const priv = counter_priv(counter);
240 	const int id = count->id;
241 	unsigned long irqflags;
242 
243 	spin_lock_irqsave(&priv->lock, irqflags);
244 
245 	if (priv->quadrature_mode[id])
246 		switch (priv->quadrature_scale[id]) {
247 		case 0:
248 			*function = COUNTER_FUNCTION_QUADRATURE_X1_A;
249 			break;
250 		case 1:
251 			*function = COUNTER_FUNCTION_QUADRATURE_X2_A;
252 			break;
253 		case 2:
254 			*function = COUNTER_FUNCTION_QUADRATURE_X4;
255 			break;
256 		}
257 	else
258 		*function = COUNTER_FUNCTION_PULSE_DIRECTION;
259 
260 	spin_unlock_irqrestore(&priv->lock, irqflags);
261 
262 	return 0;
263 }
264 
265 static int quad8_function_write(struct counter_device *counter,
266 				struct counter_count *count,
267 				enum counter_function function)
268 {
269 	struct quad8 *const priv = counter_priv(counter);
270 	const int id = count->id;
271 	unsigned int *const quadrature_mode = priv->quadrature_mode + id;
272 	unsigned int *const scale = priv->quadrature_scale + id;
273 	unsigned int *const synchronous_mode = priv->synchronous_mode + id;
274 	u8 __iomem *const control = &priv->reg->channel[id].control;
275 	unsigned long irqflags;
276 	unsigned int mode_cfg;
277 	unsigned int idr_cfg;
278 
279 	spin_lock_irqsave(&priv->lock, irqflags);
280 
281 	mode_cfg = priv->count_mode[id] << 1;
282 	idr_cfg = priv->index_polarity[id] << 1;
283 
284 	if (function == COUNTER_FUNCTION_PULSE_DIRECTION) {
285 		*quadrature_mode = 0;
286 
287 		/* Quadrature scaling only available in quadrature mode */
288 		*scale = 0;
289 
290 		/* Synchronous function not supported in non-quadrature mode */
291 		if (*synchronous_mode) {
292 			*synchronous_mode = 0;
293 			/* Disable synchronous function mode */
294 			iowrite8(QUAD8_CTR_IDR | idr_cfg, control);
295 		}
296 	} else {
297 		*quadrature_mode = 1;
298 
299 		switch (function) {
300 		case COUNTER_FUNCTION_QUADRATURE_X1_A:
301 			*scale = 0;
302 			mode_cfg |= QUAD8_CMR_QUADRATURE_X1;
303 			break;
304 		case COUNTER_FUNCTION_QUADRATURE_X2_A:
305 			*scale = 1;
306 			mode_cfg |= QUAD8_CMR_QUADRATURE_X2;
307 			break;
308 		case COUNTER_FUNCTION_QUADRATURE_X4:
309 			*scale = 2;
310 			mode_cfg |= QUAD8_CMR_QUADRATURE_X4;
311 			break;
312 		default:
313 			/* should never reach this path */
314 			spin_unlock_irqrestore(&priv->lock, irqflags);
315 			return -EINVAL;
316 		}
317 	}
318 
319 	/* Load mode configuration to Counter Mode Register */
320 	iowrite8(QUAD8_CTR_CMR | mode_cfg, control);
321 
322 	spin_unlock_irqrestore(&priv->lock, irqflags);
323 
324 	return 0;
325 }
326 
327 static int quad8_direction_read(struct counter_device *counter,
328 				struct counter_count *count,
329 				enum counter_count_direction *direction)
330 {
331 	const struct quad8 *const priv = counter_priv(counter);
332 	unsigned int ud_flag;
333 	u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control;
334 
335 	/* U/D flag: nonzero = up, zero = down */
336 	ud_flag = ioread8(flag_addr) & QUAD8_FLAG_UD;
337 
338 	*direction = (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD :
339 		COUNTER_COUNT_DIRECTION_BACKWARD;
340 
341 	return 0;
342 }
343 
344 static const enum counter_synapse_action quad8_index_actions_list[] = {
345 	COUNTER_SYNAPSE_ACTION_NONE,
346 	COUNTER_SYNAPSE_ACTION_RISING_EDGE,
347 };
348 
349 static const enum counter_synapse_action quad8_synapse_actions_list[] = {
350 	COUNTER_SYNAPSE_ACTION_NONE,
351 	COUNTER_SYNAPSE_ACTION_RISING_EDGE,
352 	COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
353 	COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
354 };
355 
356 static int quad8_action_read(struct counter_device *counter,
357 			     struct counter_count *count,
358 			     struct counter_synapse *synapse,
359 			     enum counter_synapse_action *action)
360 {
361 	struct quad8 *const priv = counter_priv(counter);
362 	int err;
363 	enum counter_function function;
364 	const size_t signal_a_id = count->synapses[0].signal->id;
365 	enum counter_count_direction direction;
366 
367 	/* Handle Index signals */
368 	if (synapse->signal->id >= 16) {
369 		if (priv->preset_enable[count->id])
370 			*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
371 		else
372 			*action = COUNTER_SYNAPSE_ACTION_NONE;
373 
374 		return 0;
375 	}
376 
377 	err = quad8_function_read(counter, count, &function);
378 	if (err)
379 		return err;
380 
381 	/* Default action mode */
382 	*action = COUNTER_SYNAPSE_ACTION_NONE;
383 
384 	/* Determine action mode based on current count function mode */
385 	switch (function) {
386 	case COUNTER_FUNCTION_PULSE_DIRECTION:
387 		if (synapse->signal->id == signal_a_id)
388 			*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
389 		return 0;
390 	case COUNTER_FUNCTION_QUADRATURE_X1_A:
391 		if (synapse->signal->id == signal_a_id) {
392 			err = quad8_direction_read(counter, count, &direction);
393 			if (err)
394 				return err;
395 
396 			if (direction == COUNTER_COUNT_DIRECTION_FORWARD)
397 				*action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
398 			else
399 				*action = COUNTER_SYNAPSE_ACTION_FALLING_EDGE;
400 		}
401 		return 0;
402 	case COUNTER_FUNCTION_QUADRATURE_X2_A:
403 		if (synapse->signal->id == signal_a_id)
404 			*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
405 		return 0;
406 	case COUNTER_FUNCTION_QUADRATURE_X4:
407 		*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
408 		return 0;
409 	default:
410 		/* should never reach this path */
411 		return -EINVAL;
412 	}
413 }
414 
415 enum {
416 	QUAD8_EVENT_CARRY = 0,
417 	QUAD8_EVENT_COMPARE = 1,
418 	QUAD8_EVENT_CARRY_BORROW = 2,
419 	QUAD8_EVENT_INDEX = 3,
420 };
421 
422 static int quad8_events_configure(struct counter_device *counter)
423 {
424 	struct quad8 *const priv = counter_priv(counter);
425 	unsigned long irq_enabled = 0;
426 	unsigned long irqflags;
427 	struct counter_event_node *event_node;
428 	unsigned int next_irq_trigger;
429 	unsigned long ior_cfg;
430 
431 	spin_lock_irqsave(&priv->lock, irqflags);
432 
433 	list_for_each_entry(event_node, &counter->events_list, l) {
434 		switch (event_node->event) {
435 		case COUNTER_EVENT_OVERFLOW:
436 			next_irq_trigger = QUAD8_EVENT_CARRY;
437 			break;
438 		case COUNTER_EVENT_THRESHOLD:
439 			next_irq_trigger = QUAD8_EVENT_COMPARE;
440 			break;
441 		case COUNTER_EVENT_OVERFLOW_UNDERFLOW:
442 			next_irq_trigger = QUAD8_EVENT_CARRY_BORROW;
443 			break;
444 		case COUNTER_EVENT_INDEX:
445 			next_irq_trigger = QUAD8_EVENT_INDEX;
446 			break;
447 		default:
448 			/* should never reach this path */
449 			spin_unlock_irqrestore(&priv->lock, irqflags);
450 			return -EINVAL;
451 		}
452 
453 		/* Enable IRQ line */
454 		irq_enabled |= BIT(event_node->channel);
455 
456 		/* Skip configuration if it is the same as previously set */
457 		if (priv->irq_trigger[event_node->channel] == next_irq_trigger)
458 			continue;
459 
460 		/* Save new IRQ function configuration */
461 		priv->irq_trigger[event_node->channel] = next_irq_trigger;
462 
463 		/* Load configuration to I/O Control Register */
464 		ior_cfg = priv->ab_enable[event_node->channel] |
465 			  priv->preset_enable[event_node->channel] << 1 |
466 			  priv->irq_trigger[event_node->channel] << 3;
467 		iowrite8(QUAD8_CTR_IOR | ior_cfg,
468 			 &priv->reg->channel[event_node->channel].control);
469 	}
470 
471 	iowrite8(irq_enabled, &priv->reg->index_interrupt);
472 
473 	spin_unlock_irqrestore(&priv->lock, irqflags);
474 
475 	return 0;
476 }
477 
478 static int quad8_watch_validate(struct counter_device *counter,
479 				const struct counter_watch *watch)
480 {
481 	struct counter_event_node *event_node;
482 
483 	if (watch->channel > QUAD8_NUM_COUNTERS - 1)
484 		return -EINVAL;
485 
486 	switch (watch->event) {
487 	case COUNTER_EVENT_OVERFLOW:
488 	case COUNTER_EVENT_THRESHOLD:
489 	case COUNTER_EVENT_OVERFLOW_UNDERFLOW:
490 	case COUNTER_EVENT_INDEX:
491 		list_for_each_entry(event_node, &counter->next_events_list, l)
492 			if (watch->channel == event_node->channel &&
493 				watch->event != event_node->event)
494 				return -EINVAL;
495 		return 0;
496 	default:
497 		return -EINVAL;
498 	}
499 }
500 
501 static const struct counter_ops quad8_ops = {
502 	.signal_read = quad8_signal_read,
503 	.count_read = quad8_count_read,
504 	.count_write = quad8_count_write,
505 	.function_read = quad8_function_read,
506 	.function_write = quad8_function_write,
507 	.action_read = quad8_action_read,
508 	.events_configure = quad8_events_configure,
509 	.watch_validate = quad8_watch_validate,
510 };
511 
512 static const char *const quad8_index_polarity_modes[] = {
513 	"negative",
514 	"positive"
515 };
516 
517 static int quad8_index_polarity_get(struct counter_device *counter,
518 				    struct counter_signal *signal,
519 				    u32 *index_polarity)
520 {
521 	const struct quad8 *const priv = counter_priv(counter);
522 	const size_t channel_id = signal->id - 16;
523 
524 	*index_polarity = priv->index_polarity[channel_id];
525 
526 	return 0;
527 }
528 
529 static int quad8_index_polarity_set(struct counter_device *counter,
530 				    struct counter_signal *signal,
531 				    u32 index_polarity)
532 {
533 	struct quad8 *const priv = counter_priv(counter);
534 	const size_t channel_id = signal->id - 16;
535 	u8 __iomem *const control = &priv->reg->channel[channel_id].control;
536 	unsigned long irqflags;
537 	unsigned int idr_cfg = index_polarity << 1;
538 
539 	spin_lock_irqsave(&priv->lock, irqflags);
540 
541 	idr_cfg |= priv->synchronous_mode[channel_id];
542 
543 	priv->index_polarity[channel_id] = index_polarity;
544 
545 	/* Load Index Control configuration to Index Control Register */
546 	iowrite8(QUAD8_CTR_IDR | idr_cfg, control);
547 
548 	spin_unlock_irqrestore(&priv->lock, irqflags);
549 
550 	return 0;
551 }
552 
553 static int quad8_polarity_read(struct counter_device *counter,
554 			       struct counter_signal *signal,
555 			       enum counter_signal_polarity *polarity)
556 {
557 	int err;
558 	u32 index_polarity;
559 
560 	err = quad8_index_polarity_get(counter, signal, &index_polarity);
561 	if (err)
562 		return err;
563 
564 	*polarity = (index_polarity) ? COUNTER_SIGNAL_POLARITY_POSITIVE :
565 		COUNTER_SIGNAL_POLARITY_NEGATIVE;
566 
567 	return 0;
568 }
569 
570 static int quad8_polarity_write(struct counter_device *counter,
571 				struct counter_signal *signal,
572 				enum counter_signal_polarity polarity)
573 {
574 	const u32 pol = (polarity == COUNTER_SIGNAL_POLARITY_POSITIVE) ? 1 : 0;
575 
576 	return quad8_index_polarity_set(counter, signal, pol);
577 }
578 
579 static const char *const quad8_synchronous_modes[] = {
580 	"non-synchronous",
581 	"synchronous"
582 };
583 
584 static int quad8_synchronous_mode_get(struct counter_device *counter,
585 				      struct counter_signal *signal,
586 				      u32 *synchronous_mode)
587 {
588 	const struct quad8 *const priv = counter_priv(counter);
589 	const size_t channel_id = signal->id - 16;
590 
591 	*synchronous_mode = priv->synchronous_mode[channel_id];
592 
593 	return 0;
594 }
595 
596 static int quad8_synchronous_mode_set(struct counter_device *counter,
597 				      struct counter_signal *signal,
598 				      u32 synchronous_mode)
599 {
600 	struct quad8 *const priv = counter_priv(counter);
601 	const size_t channel_id = signal->id - 16;
602 	u8 __iomem *const control = &priv->reg->channel[channel_id].control;
603 	unsigned long irqflags;
604 	unsigned int idr_cfg = synchronous_mode;
605 
606 	spin_lock_irqsave(&priv->lock, irqflags);
607 
608 	idr_cfg |= priv->index_polarity[channel_id] << 1;
609 
610 	/* Index function must be non-synchronous in non-quadrature mode */
611 	if (synchronous_mode && !priv->quadrature_mode[channel_id]) {
612 		spin_unlock_irqrestore(&priv->lock, irqflags);
613 		return -EINVAL;
614 	}
615 
616 	priv->synchronous_mode[channel_id] = synchronous_mode;
617 
618 	/* Load Index Control configuration to Index Control Register */
619 	iowrite8(QUAD8_CTR_IDR | idr_cfg, control);
620 
621 	spin_unlock_irqrestore(&priv->lock, irqflags);
622 
623 	return 0;
624 }
625 
626 static int quad8_count_floor_read(struct counter_device *counter,
627 				  struct counter_count *count, u64 *floor)
628 {
629 	/* Only a floor of 0 is supported */
630 	*floor = 0;
631 
632 	return 0;
633 }
634 
635 static int quad8_count_mode_read(struct counter_device *counter,
636 				 struct counter_count *count,
637 				 enum counter_count_mode *cnt_mode)
638 {
639 	const struct quad8 *const priv = counter_priv(counter);
640 
641 	/* Map 104-QUAD-8 count mode to Generic Counter count mode */
642 	switch (priv->count_mode[count->id]) {
643 	case 0:
644 		*cnt_mode = COUNTER_COUNT_MODE_NORMAL;
645 		break;
646 	case 1:
647 		*cnt_mode = COUNTER_COUNT_MODE_RANGE_LIMIT;
648 		break;
649 	case 2:
650 		*cnt_mode = COUNTER_COUNT_MODE_NON_RECYCLE;
651 		break;
652 	case 3:
653 		*cnt_mode = COUNTER_COUNT_MODE_MODULO_N;
654 		break;
655 	}
656 
657 	return 0;
658 }
659 
660 static int quad8_count_mode_write(struct counter_device *counter,
661 				  struct counter_count *count,
662 				  enum counter_count_mode cnt_mode)
663 {
664 	struct quad8 *const priv = counter_priv(counter);
665 	unsigned int count_mode;
666 	unsigned int mode_cfg;
667 	u8 __iomem *const control = &priv->reg->channel[count->id].control;
668 	unsigned long irqflags;
669 
670 	/* Map Generic Counter count mode to 104-QUAD-8 count mode */
671 	switch (cnt_mode) {
672 	case COUNTER_COUNT_MODE_NORMAL:
673 		count_mode = 0;
674 		break;
675 	case COUNTER_COUNT_MODE_RANGE_LIMIT:
676 		count_mode = 1;
677 		break;
678 	case COUNTER_COUNT_MODE_NON_RECYCLE:
679 		count_mode = 2;
680 		break;
681 	case COUNTER_COUNT_MODE_MODULO_N:
682 		count_mode = 3;
683 		break;
684 	default:
685 		/* should never reach this path */
686 		return -EINVAL;
687 	}
688 
689 	spin_lock_irqsave(&priv->lock, irqflags);
690 
691 	priv->count_mode[count->id] = count_mode;
692 
693 	/* Set count mode configuration value */
694 	mode_cfg = count_mode << 1;
695 
696 	/* Add quadrature mode configuration */
697 	if (priv->quadrature_mode[count->id])
698 		mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3;
699 
700 	/* Load mode configuration to Counter Mode Register */
701 	iowrite8(QUAD8_CTR_CMR | mode_cfg, control);
702 
703 	spin_unlock_irqrestore(&priv->lock, irqflags);
704 
705 	return 0;
706 }
707 
708 static int quad8_count_enable_read(struct counter_device *counter,
709 				   struct counter_count *count, u8 *enable)
710 {
711 	const struct quad8 *const priv = counter_priv(counter);
712 
713 	*enable = priv->ab_enable[count->id];
714 
715 	return 0;
716 }
717 
718 static int quad8_count_enable_write(struct counter_device *counter,
719 				    struct counter_count *count, u8 enable)
720 {
721 	struct quad8 *const priv = counter_priv(counter);
722 	u8 __iomem *const control = &priv->reg->channel[count->id].control;
723 	unsigned long irqflags;
724 	unsigned int ior_cfg;
725 
726 	spin_lock_irqsave(&priv->lock, irqflags);
727 
728 	priv->ab_enable[count->id] = enable;
729 
730 	ior_cfg = enable | priv->preset_enable[count->id] << 1 |
731 		  priv->irq_trigger[count->id] << 3;
732 
733 	/* Load I/O control configuration */
734 	iowrite8(QUAD8_CTR_IOR | ior_cfg, control);
735 
736 	spin_unlock_irqrestore(&priv->lock, irqflags);
737 
738 	return 0;
739 }
740 
741 static const char *const quad8_noise_error_states[] = {
742 	"No excessive noise is present at the count inputs",
743 	"Excessive noise is present at the count inputs"
744 };
745 
746 static int quad8_error_noise_get(struct counter_device *counter,
747 				 struct counter_count *count, u32 *noise_error)
748 {
749 	const struct quad8 *const priv = counter_priv(counter);
750 	u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control;
751 
752 	*noise_error = !!(ioread8(flag_addr) & QUAD8_FLAG_E);
753 
754 	return 0;
755 }
756 
757 static int quad8_count_preset_read(struct counter_device *counter,
758 				   struct counter_count *count, u64 *preset)
759 {
760 	const struct quad8 *const priv = counter_priv(counter);
761 
762 	*preset = priv->preset[count->id];
763 
764 	return 0;
765 }
766 
767 static void quad8_preset_register_set(struct quad8 *const priv, const int id,
768 				      const unsigned int preset)
769 {
770 	struct channel_reg __iomem *const chan = priv->reg->channel + id;
771 	int i;
772 
773 	priv->preset[id] = preset;
774 
775 	/* Reset Byte Pointer */
776 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
777 
778 	/* Set Preset Register */
779 	for (i = 0; i < 3; i++)
780 		iowrite8(preset >> (8 * i), &chan->data);
781 }
782 
783 static int quad8_count_preset_write(struct counter_device *counter,
784 				    struct counter_count *count, u64 preset)
785 {
786 	struct quad8 *const priv = counter_priv(counter);
787 	unsigned long irqflags;
788 
789 	/* Only 24-bit values are supported */
790 	if (preset > 0xFFFFFF)
791 		return -ERANGE;
792 
793 	spin_lock_irqsave(&priv->lock, irqflags);
794 
795 	quad8_preset_register_set(priv, count->id, preset);
796 
797 	spin_unlock_irqrestore(&priv->lock, irqflags);
798 
799 	return 0;
800 }
801 
802 static int quad8_count_ceiling_read(struct counter_device *counter,
803 				    struct counter_count *count, u64 *ceiling)
804 {
805 	struct quad8 *const priv = counter_priv(counter);
806 	unsigned long irqflags;
807 
808 	spin_lock_irqsave(&priv->lock, irqflags);
809 
810 	/* Range Limit and Modulo-N count modes use preset value as ceiling */
811 	switch (priv->count_mode[count->id]) {
812 	case 1:
813 	case 3:
814 		*ceiling = priv->preset[count->id];
815 		break;
816 	default:
817 		/* By default 0x1FFFFFF (25 bits unsigned) is maximum count */
818 		*ceiling = 0x1FFFFFF;
819 		break;
820 	}
821 
822 	spin_unlock_irqrestore(&priv->lock, irqflags);
823 
824 	return 0;
825 }
826 
827 static int quad8_count_ceiling_write(struct counter_device *counter,
828 				     struct counter_count *count, u64 ceiling)
829 {
830 	struct quad8 *const priv = counter_priv(counter);
831 	unsigned long irqflags;
832 
833 	/* Only 24-bit values are supported */
834 	if (ceiling > 0xFFFFFF)
835 		return -ERANGE;
836 
837 	spin_lock_irqsave(&priv->lock, irqflags);
838 
839 	/* Range Limit and Modulo-N count modes use preset value as ceiling */
840 	switch (priv->count_mode[count->id]) {
841 	case 1:
842 	case 3:
843 		quad8_preset_register_set(priv, count->id, ceiling);
844 		spin_unlock_irqrestore(&priv->lock, irqflags);
845 		return 0;
846 	}
847 
848 	spin_unlock_irqrestore(&priv->lock, irqflags);
849 
850 	return -EINVAL;
851 }
852 
853 static int quad8_count_preset_enable_read(struct counter_device *counter,
854 					  struct counter_count *count,
855 					  u8 *preset_enable)
856 {
857 	const struct quad8 *const priv = counter_priv(counter);
858 
859 	*preset_enable = !priv->preset_enable[count->id];
860 
861 	return 0;
862 }
863 
864 static int quad8_count_preset_enable_write(struct counter_device *counter,
865 					   struct counter_count *count,
866 					   u8 preset_enable)
867 {
868 	struct quad8 *const priv = counter_priv(counter);
869 	u8 __iomem *const control = &priv->reg->channel[count->id].control;
870 	unsigned long irqflags;
871 	unsigned int ior_cfg;
872 
873 	/* Preset enable is active low in Input/Output Control register */
874 	preset_enable = !preset_enable;
875 
876 	spin_lock_irqsave(&priv->lock, irqflags);
877 
878 	priv->preset_enable[count->id] = preset_enable;
879 
880 	ior_cfg = priv->ab_enable[count->id] | preset_enable << 1 |
881 		  priv->irq_trigger[count->id] << 3;
882 
883 	/* Load I/O control configuration to Input / Output Control Register */
884 	iowrite8(QUAD8_CTR_IOR | ior_cfg, control);
885 
886 	spin_unlock_irqrestore(&priv->lock, irqflags);
887 
888 	return 0;
889 }
890 
891 static int quad8_signal_cable_fault_read(struct counter_device *counter,
892 					 struct counter_signal *signal,
893 					 u8 *cable_fault)
894 {
895 	struct quad8 *const priv = counter_priv(counter);
896 	const size_t channel_id = signal->id / 2;
897 	unsigned long irqflags;
898 	bool disabled;
899 	unsigned int status;
900 
901 	spin_lock_irqsave(&priv->lock, irqflags);
902 
903 	disabled = !(priv->cable_fault_enable & BIT(channel_id));
904 
905 	if (disabled) {
906 		spin_unlock_irqrestore(&priv->lock, irqflags);
907 		return -EINVAL;
908 	}
909 
910 	/* Logic 0 = cable fault */
911 	status = ioread8(&priv->reg->cable_status);
912 
913 	spin_unlock_irqrestore(&priv->lock, irqflags);
914 
915 	/* Mask respective channel and invert logic */
916 	*cable_fault = !(status & BIT(channel_id));
917 
918 	return 0;
919 }
920 
921 static int quad8_signal_cable_fault_enable_read(struct counter_device *counter,
922 						struct counter_signal *signal,
923 						u8 *enable)
924 {
925 	const struct quad8 *const priv = counter_priv(counter);
926 	const size_t channel_id = signal->id / 2;
927 
928 	*enable = !!(priv->cable_fault_enable & BIT(channel_id));
929 
930 	return 0;
931 }
932 
933 static int quad8_signal_cable_fault_enable_write(struct counter_device *counter,
934 						 struct counter_signal *signal,
935 						 u8 enable)
936 {
937 	struct quad8 *const priv = counter_priv(counter);
938 	const size_t channel_id = signal->id / 2;
939 	unsigned long irqflags;
940 	unsigned int cable_fault_enable;
941 
942 	spin_lock_irqsave(&priv->lock, irqflags);
943 
944 	if (enable)
945 		priv->cable_fault_enable |= BIT(channel_id);
946 	else
947 		priv->cable_fault_enable &= ~BIT(channel_id);
948 
949 	/* Enable is active low in Differential Encoder Cable Status register */
950 	cable_fault_enable = ~priv->cable_fault_enable;
951 
952 	iowrite8(cable_fault_enable, &priv->reg->cable_status);
953 
954 	spin_unlock_irqrestore(&priv->lock, irqflags);
955 
956 	return 0;
957 }
958 
959 static int quad8_signal_fck_prescaler_read(struct counter_device *counter,
960 					   struct counter_signal *signal,
961 					   u8 *prescaler)
962 {
963 	const struct quad8 *const priv = counter_priv(counter);
964 
965 	*prescaler = priv->fck_prescaler[signal->id / 2];
966 
967 	return 0;
968 }
969 
970 static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
971 					    struct counter_signal *signal,
972 					    u8 prescaler)
973 {
974 	struct quad8 *const priv = counter_priv(counter);
975 	const size_t channel_id = signal->id / 2;
976 	struct channel_reg __iomem *const chan = priv->reg->channel + channel_id;
977 	unsigned long irqflags;
978 
979 	spin_lock_irqsave(&priv->lock, irqflags);
980 
981 	priv->fck_prescaler[channel_id] = prescaler;
982 
983 	/* Reset Byte Pointer */
984 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
985 
986 	/* Set filter clock factor */
987 	iowrite8(prescaler, &chan->data);
988 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
989 		 &chan->control);
990 
991 	spin_unlock_irqrestore(&priv->lock, irqflags);
992 
993 	return 0;
994 }
995 
996 static struct counter_comp quad8_signal_ext[] = {
997 	COUNTER_COMP_SIGNAL_BOOL("cable_fault", quad8_signal_cable_fault_read,
998 				 NULL),
999 	COUNTER_COMP_SIGNAL_BOOL("cable_fault_enable",
1000 				 quad8_signal_cable_fault_enable_read,
1001 				 quad8_signal_cable_fault_enable_write),
1002 	COUNTER_COMP_SIGNAL_U8("filter_clock_prescaler",
1003 			       quad8_signal_fck_prescaler_read,
1004 			       quad8_signal_fck_prescaler_write)
1005 };
1006 
1007 static const enum counter_signal_polarity quad8_polarities[] = {
1008 	COUNTER_SIGNAL_POLARITY_POSITIVE,
1009 	COUNTER_SIGNAL_POLARITY_NEGATIVE,
1010 };
1011 
1012 static DEFINE_COUNTER_AVAILABLE(quad8_polarity_available, quad8_polarities);
1013 
1014 static DEFINE_COUNTER_ENUM(quad8_index_pol_enum, quad8_index_polarity_modes);
1015 static DEFINE_COUNTER_ENUM(quad8_synch_mode_enum, quad8_synchronous_modes);
1016 
1017 static struct counter_comp quad8_index_ext[] = {
1018 	COUNTER_COMP_SIGNAL_ENUM("index_polarity", quad8_index_polarity_get,
1019 				 quad8_index_polarity_set,
1020 				 quad8_index_pol_enum),
1021 	COUNTER_COMP_POLARITY(quad8_polarity_read, quad8_polarity_write,
1022 			      quad8_polarity_available),
1023 	COUNTER_COMP_SIGNAL_ENUM("synchronous_mode", quad8_synchronous_mode_get,
1024 				 quad8_synchronous_mode_set,
1025 				 quad8_synch_mode_enum),
1026 };
1027 
1028 #define QUAD8_QUAD_SIGNAL(_id, _name) {		\
1029 	.id = (_id),				\
1030 	.name = (_name),			\
1031 	.ext = quad8_signal_ext,		\
1032 	.num_ext = ARRAY_SIZE(quad8_signal_ext)	\
1033 }
1034 
1035 #define	QUAD8_INDEX_SIGNAL(_id, _name) {	\
1036 	.id = (_id),				\
1037 	.name = (_name),			\
1038 	.ext = quad8_index_ext,			\
1039 	.num_ext = ARRAY_SIZE(quad8_index_ext)	\
1040 }
1041 
1042 static struct counter_signal quad8_signals[] = {
1043 	QUAD8_QUAD_SIGNAL(0, "Channel 1 Quadrature A"),
1044 	QUAD8_QUAD_SIGNAL(1, "Channel 1 Quadrature B"),
1045 	QUAD8_QUAD_SIGNAL(2, "Channel 2 Quadrature A"),
1046 	QUAD8_QUAD_SIGNAL(3, "Channel 2 Quadrature B"),
1047 	QUAD8_QUAD_SIGNAL(4, "Channel 3 Quadrature A"),
1048 	QUAD8_QUAD_SIGNAL(5, "Channel 3 Quadrature B"),
1049 	QUAD8_QUAD_SIGNAL(6, "Channel 4 Quadrature A"),
1050 	QUAD8_QUAD_SIGNAL(7, "Channel 4 Quadrature B"),
1051 	QUAD8_QUAD_SIGNAL(8, "Channel 5 Quadrature A"),
1052 	QUAD8_QUAD_SIGNAL(9, "Channel 5 Quadrature B"),
1053 	QUAD8_QUAD_SIGNAL(10, "Channel 6 Quadrature A"),
1054 	QUAD8_QUAD_SIGNAL(11, "Channel 6 Quadrature B"),
1055 	QUAD8_QUAD_SIGNAL(12, "Channel 7 Quadrature A"),
1056 	QUAD8_QUAD_SIGNAL(13, "Channel 7 Quadrature B"),
1057 	QUAD8_QUAD_SIGNAL(14, "Channel 8 Quadrature A"),
1058 	QUAD8_QUAD_SIGNAL(15, "Channel 8 Quadrature B"),
1059 	QUAD8_INDEX_SIGNAL(16, "Channel 1 Index"),
1060 	QUAD8_INDEX_SIGNAL(17, "Channel 2 Index"),
1061 	QUAD8_INDEX_SIGNAL(18, "Channel 3 Index"),
1062 	QUAD8_INDEX_SIGNAL(19, "Channel 4 Index"),
1063 	QUAD8_INDEX_SIGNAL(20, "Channel 5 Index"),
1064 	QUAD8_INDEX_SIGNAL(21, "Channel 6 Index"),
1065 	QUAD8_INDEX_SIGNAL(22, "Channel 7 Index"),
1066 	QUAD8_INDEX_SIGNAL(23, "Channel 8 Index")
1067 };
1068 
1069 #define QUAD8_COUNT_SYNAPSES(_id) {					\
1070 	{								\
1071 		.actions_list = quad8_synapse_actions_list,		\
1072 		.num_actions = ARRAY_SIZE(quad8_synapse_actions_list),	\
1073 		.signal = quad8_signals + 2 * (_id)			\
1074 	},								\
1075 	{								\
1076 		.actions_list = quad8_synapse_actions_list,		\
1077 		.num_actions = ARRAY_SIZE(quad8_synapse_actions_list),	\
1078 		.signal = quad8_signals + 2 * (_id) + 1			\
1079 	},								\
1080 	{								\
1081 		.actions_list = quad8_index_actions_list,		\
1082 		.num_actions = ARRAY_SIZE(quad8_index_actions_list),	\
1083 		.signal = quad8_signals + 2 * (_id) + 16		\
1084 	}								\
1085 }
1086 
1087 static struct counter_synapse quad8_count_synapses[][3] = {
1088 	QUAD8_COUNT_SYNAPSES(0), QUAD8_COUNT_SYNAPSES(1),
1089 	QUAD8_COUNT_SYNAPSES(2), QUAD8_COUNT_SYNAPSES(3),
1090 	QUAD8_COUNT_SYNAPSES(4), QUAD8_COUNT_SYNAPSES(5),
1091 	QUAD8_COUNT_SYNAPSES(6), QUAD8_COUNT_SYNAPSES(7)
1092 };
1093 
1094 static const enum counter_count_mode quad8_cnt_modes[] = {
1095 	COUNTER_COUNT_MODE_NORMAL,
1096 	COUNTER_COUNT_MODE_RANGE_LIMIT,
1097 	COUNTER_COUNT_MODE_NON_RECYCLE,
1098 	COUNTER_COUNT_MODE_MODULO_N,
1099 };
1100 
1101 static DEFINE_COUNTER_AVAILABLE(quad8_count_mode_available, quad8_cnt_modes);
1102 
1103 static DEFINE_COUNTER_ENUM(quad8_error_noise_enum, quad8_noise_error_states);
1104 
1105 static struct counter_comp quad8_count_ext[] = {
1106 	COUNTER_COMP_CEILING(quad8_count_ceiling_read,
1107 			     quad8_count_ceiling_write),
1108 	COUNTER_COMP_FLOOR(quad8_count_floor_read, NULL),
1109 	COUNTER_COMP_COUNT_MODE(quad8_count_mode_read, quad8_count_mode_write,
1110 				quad8_count_mode_available),
1111 	COUNTER_COMP_DIRECTION(quad8_direction_read),
1112 	COUNTER_COMP_ENABLE(quad8_count_enable_read, quad8_count_enable_write),
1113 	COUNTER_COMP_COUNT_ENUM("error_noise", quad8_error_noise_get, NULL,
1114 				quad8_error_noise_enum),
1115 	COUNTER_COMP_PRESET(quad8_count_preset_read, quad8_count_preset_write),
1116 	COUNTER_COMP_PRESET_ENABLE(quad8_count_preset_enable_read,
1117 				   quad8_count_preset_enable_write),
1118 };
1119 
1120 #define QUAD8_COUNT(_id, _cntname) {					\
1121 	.id = (_id),							\
1122 	.name = (_cntname),						\
1123 	.functions_list = quad8_count_functions_list,			\
1124 	.num_functions = ARRAY_SIZE(quad8_count_functions_list),	\
1125 	.synapses = quad8_count_synapses[(_id)],			\
1126 	.num_synapses =	2,						\
1127 	.ext = quad8_count_ext,						\
1128 	.num_ext = ARRAY_SIZE(quad8_count_ext)				\
1129 }
1130 
1131 static struct counter_count quad8_counts[] = {
1132 	QUAD8_COUNT(0, "Channel 1 Count"),
1133 	QUAD8_COUNT(1, "Channel 2 Count"),
1134 	QUAD8_COUNT(2, "Channel 3 Count"),
1135 	QUAD8_COUNT(3, "Channel 4 Count"),
1136 	QUAD8_COUNT(4, "Channel 5 Count"),
1137 	QUAD8_COUNT(5, "Channel 6 Count"),
1138 	QUAD8_COUNT(6, "Channel 7 Count"),
1139 	QUAD8_COUNT(7, "Channel 8 Count")
1140 };
1141 
1142 static irqreturn_t quad8_irq_handler(int irq, void *private)
1143 {
1144 	struct counter_device *counter = private;
1145 	struct quad8 *const priv = counter_priv(counter);
1146 	unsigned long irq_status;
1147 	unsigned long channel;
1148 	u8 event;
1149 
1150 	irq_status = ioread8(&priv->reg->interrupt_status);
1151 	if (!irq_status)
1152 		return IRQ_NONE;
1153 
1154 	for_each_set_bit(channel, &irq_status, QUAD8_NUM_COUNTERS) {
1155 		switch (priv->irq_trigger[channel]) {
1156 		case QUAD8_EVENT_CARRY:
1157 			event = COUNTER_EVENT_OVERFLOW;
1158 				break;
1159 		case QUAD8_EVENT_COMPARE:
1160 			event = COUNTER_EVENT_THRESHOLD;
1161 				break;
1162 		case QUAD8_EVENT_CARRY_BORROW:
1163 			event = COUNTER_EVENT_OVERFLOW_UNDERFLOW;
1164 				break;
1165 		case QUAD8_EVENT_INDEX:
1166 			event = COUNTER_EVENT_INDEX;
1167 				break;
1168 		default:
1169 			/* should never reach this path */
1170 			WARN_ONCE(true, "invalid interrupt trigger function %u configured for channel %lu\n",
1171 				  priv->irq_trigger[channel], channel);
1172 			continue;
1173 		}
1174 
1175 		counter_push_event(counter, event, channel);
1176 	}
1177 
1178 	/* Clear pending interrupts on device */
1179 	iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper);
1180 
1181 	return IRQ_HANDLED;
1182 }
1183 
1184 static void quad8_init_counter(struct channel_reg __iomem *const chan)
1185 {
1186 	unsigned long i;
1187 
1188 	/* Reset Byte Pointer */
1189 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
1190 	/* Reset filter clock factor */
1191 	iowrite8(0, &chan->data);
1192 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
1193 		 &chan->control);
1194 	/* Reset Byte Pointer */
1195 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
1196 	/* Reset Preset Register */
1197 	for (i = 0; i < 3; i++)
1198 		iowrite8(0x00, &chan->data);
1199 	/* Reset Borrow, Carry, Compare, and Sign flags */
1200 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control);
1201 	/* Reset Error flag */
1202 	iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control);
1203 	/* Binary encoding; Normal count; non-quadrature mode */
1204 	iowrite8(QUAD8_CTR_CMR, &chan->control);
1205 	/* Disable A and B inputs; preset on index; FLG1 as Carry */
1206 	iowrite8(QUAD8_CTR_IOR, &chan->control);
1207 	/* Disable index function; negative index polarity */
1208 	iowrite8(QUAD8_CTR_IDR, &chan->control);
1209 }
1210 
1211 static int quad8_probe(struct device *dev, unsigned int id)
1212 {
1213 	struct counter_device *counter;
1214 	struct quad8 *priv;
1215 	unsigned long i;
1216 	int err;
1217 
1218 	if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) {
1219 		dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
1220 			base[id], base[id] + QUAD8_EXTENT);
1221 		return -EBUSY;
1222 	}
1223 
1224 	counter = devm_counter_alloc(dev, sizeof(*priv));
1225 	if (!counter)
1226 		return -ENOMEM;
1227 	priv = counter_priv(counter);
1228 
1229 	priv->reg = devm_ioport_map(dev, base[id], QUAD8_EXTENT);
1230 	if (!priv->reg)
1231 		return -ENOMEM;
1232 
1233 	/* Initialize Counter device and driver data */
1234 	counter->name = dev_name(dev);
1235 	counter->parent = dev;
1236 	counter->ops = &quad8_ops;
1237 	counter->counts = quad8_counts;
1238 	counter->num_counts = ARRAY_SIZE(quad8_counts);
1239 	counter->signals = quad8_signals;
1240 	counter->num_signals = ARRAY_SIZE(quad8_signals);
1241 
1242 	spin_lock_init(&priv->lock);
1243 
1244 	/* Reset Index/Interrupt Register */
1245 	iowrite8(0x00, &priv->reg->index_interrupt);
1246 	/* Reset all counters and disable interrupt function */
1247 	iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, &priv->reg->channel_oper);
1248 	/* Set initial configuration for all counters */
1249 	for (i = 0; i < QUAD8_NUM_COUNTERS; i++)
1250 		quad8_init_counter(priv->reg->channel + i);
1251 	/* Disable Differential Encoder Cable Status for all channels */
1252 	iowrite8(0xFF, &priv->reg->cable_status);
1253 	/* Enable all counters and enable interrupt function */
1254 	iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper);
1255 
1256 	err = devm_request_irq(&counter->dev, irq[id], quad8_irq_handler,
1257 			       IRQF_SHARED, counter->name, counter);
1258 	if (err)
1259 		return err;
1260 
1261 	err = devm_counter_add(dev, counter);
1262 	if (err < 0)
1263 		return dev_err_probe(dev, err, "Failed to add counter\n");
1264 
1265 	return 0;
1266 }
1267 
1268 static struct isa_driver quad8_driver = {
1269 	.probe = quad8_probe,
1270 	.driver = {
1271 		.name = "104-quad-8"
1272 	}
1273 };
1274 
1275 module_isa_driver_with_irq(quad8_driver, num_quad8, num_irq);
1276 
1277 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
1278 MODULE_DESCRIPTION("ACCES 104-QUAD-8 driver");
1279 MODULE_LICENSE("GPL v2");
1280 MODULE_IMPORT_NS(COUNTER);
1281