1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * linux/arch/arm/plat-omap/dmtimer.c 4 * 5 * OMAP Dual-Mode Timers 6 * 7 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ 8 * Tarun Kanti DebBarma <tarun.kanti@ti.com> 9 * Thara Gopinath <thara@ti.com> 10 * 11 * dmtimer adaptation to platform_driver. 12 * 13 * Copyright (C) 2005 Nokia Corporation 14 * OMAP2 support by Juha Yrjola 15 * API improvements and OMAP2 clock framework support by Timo Teras 16 * 17 * Copyright (C) 2009 Texas Instruments 18 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/clk-provider.h> 23 #include <linux/clocksource.h> 24 #include <linux/clockchips.h> 25 #include <linux/cpu_pm.h> 26 #include <linux/module.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/device.h> 30 #include <linux/err.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/of.h> 33 #include <linux/platform_device.h> 34 #include <linux/platform_data/dmtimer-omap.h> 35 #include <linux/sched_clock.h> 36 37 #include <clocksource/timer-ti-dm.h> 38 #include <linux/delay.h> 39 40 /* 41 * timer errata flags 42 * 43 * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This 44 * errata prevents us from using posted mode on these devices, unless the 45 * timer counter register is never read. For more details please refer to 46 * the OMAP3/4/5 errata documents. 47 */ 48 #define OMAP_TIMER_ERRATA_I103_I767 0x80000000 49 50 /* posted mode types */ 51 #define OMAP_TIMER_NONPOSTED 0x00 52 #define OMAP_TIMER_POSTED 0x01 53 54 /* register offsets with the write pending bit encoded */ 55 #define WPSHIFT 16 56 57 #define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \ 58 | (WP_NONE << WPSHIFT)) 59 60 #define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \ 61 | (WP_TCLR << WPSHIFT)) 62 63 #define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \ 64 | (WP_TCRR << WPSHIFT)) 65 66 #define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \ 67 | (WP_TLDR << WPSHIFT)) 68 69 #define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \ 70 | (WP_TTGR << WPSHIFT)) 71 72 #define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \ 73 | (WP_NONE << WPSHIFT)) 74 75 #define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \ 76 | (WP_TMAR << WPSHIFT)) 77 78 #define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \ 79 | (WP_NONE << WPSHIFT)) 80 81 #define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \ 82 | (WP_NONE << WPSHIFT)) 83 84 #define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \ 85 | (WP_NONE << WPSHIFT)) 86 87 #define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \ 88 | (WP_TPIR << WPSHIFT)) 89 90 #define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \ 91 | (WP_TNIR << WPSHIFT)) 92 93 #define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \ 94 | (WP_TCVR << WPSHIFT)) 95 96 #define OMAP_TIMER_TICK_INT_MASK_SET_REG \ 97 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT)) 98 99 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ 100 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) 101 102 struct timer_regs { 103 u32 ocp_cfg; 104 u32 tidr; 105 u32 tier; 106 u32 twer; 107 u32 tclr; 108 u32 tcrr; 109 u32 tldr; 110 u32 ttrg; 111 u32 twps; 112 u32 tmar; 113 u32 tcar1; 114 u32 tsicr; 115 u32 tcar2; 116 u32 tpir; 117 u32 tnir; 118 u32 tcvr; 119 u32 tocr; 120 u32 towr; 121 }; 122 123 struct dmtimer { 124 struct omap_dm_timer cookie; 125 int id; 126 int irq; 127 struct clk *fclk; 128 129 void __iomem *io_base; 130 int irq_stat; /* TISR/IRQSTATUS interrupt status */ 131 int irq_ena; /* irq enable */ 132 int irq_dis; /* irq disable, only on v2 ip */ 133 void __iomem *pend; /* write pending */ 134 void __iomem *func_base; /* function register base */ 135 136 atomic_t enabled; 137 unsigned reserved:1; 138 unsigned posted:1; 139 unsigned omap1:1; 140 struct timer_regs context; 141 int revision; 142 u32 capability; 143 u32 errata; 144 struct platform_device *pdev; 145 struct list_head node; 146 struct notifier_block nb; 147 struct notifier_block fclk_nb; 148 unsigned long fclk_rate; 149 }; 150 151 static u32 omap_reserved_systimers; 152 static LIST_HEAD(omap_timer_list); 153 static DEFINE_SPINLOCK(dm_timer_lock); 154 155 struct dmtimer_clocksource { 156 struct clocksource dev; 157 struct dmtimer *timer; 158 unsigned int loadval; 159 }; 160 161 struct omap_dm_timer_clockevent { 162 struct clock_event_device dev; 163 struct dmtimer *timer; 164 u32 period; 165 }; 166 167 static bool omap_dm_timer_clockevent_setup; 168 static void __iomem *omap_dm_timer_sched_clock_counter; 169 170 enum { 171 REQUEST_ANY = 0, 172 REQUEST_BY_ID, 173 REQUEST_BY_CAP, 174 REQUEST_BY_NODE, 175 }; 176 177 /** 178 * dmtimer_read - read timer registers in posted and non-posted mode 179 * @timer: timer pointer over which read operation to perform 180 * @reg: lowest byte holds the register offset 181 * 182 * The posted mode bit is encoded in reg. Note that in posted mode, write 183 * pending bit must be checked. Otherwise a read of a non completed write 184 * will produce an error. 185 */ 186 static inline u32 dmtimer_read(struct dmtimer *timer, u32 reg) 187 { 188 u16 wp, offset; 189 190 wp = reg >> WPSHIFT; 191 offset = reg & 0xff; 192 193 /* Wait for a possible write pending bit in posted mode */ 194 if (wp && timer->posted) 195 while (readl_relaxed(timer->pend) & wp) 196 cpu_relax(); 197 198 return readl_relaxed(timer->func_base + offset); 199 } 200 201 /** 202 * dmtimer_write - write timer registers in posted and non-posted mode 203 * @timer: timer pointer over which write operation is to perform 204 * @reg: lowest byte holds the register offset 205 * @val: data to write into the register 206 * 207 * The posted mode bit is encoded in reg. Note that in posted mode, the write 208 * pending bit must be checked. Otherwise a write on a register which has a 209 * pending write will be lost. 210 */ 211 static inline void dmtimer_write(struct dmtimer *timer, u32 reg, u32 val) 212 { 213 u16 wp, offset; 214 215 wp = reg >> WPSHIFT; 216 offset = reg & 0xff; 217 218 /* Wait for a possible write pending bit in posted mode */ 219 if (wp && timer->posted) 220 while (readl_relaxed(timer->pend) & wp) 221 cpu_relax(); 222 223 writel_relaxed(val, timer->func_base + offset); 224 } 225 226 static inline void __omap_dm_timer_init_regs(struct dmtimer *timer) 227 { 228 u32 tidr; 229 230 /* Assume v1 ip if bits [31:16] are zero */ 231 tidr = readl_relaxed(timer->io_base); 232 if (!(tidr >> 16)) { 233 timer->revision = 1; 234 timer->irq_stat = OMAP_TIMER_V1_STAT_OFFSET; 235 timer->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET; 236 timer->irq_dis = OMAP_TIMER_V1_INT_EN_OFFSET; 237 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET; 238 timer->func_base = timer->io_base; 239 } else { 240 timer->revision = 2; 241 timer->irq_stat = OMAP_TIMER_V2_IRQSTATUS - OMAP_TIMER_V2_FUNC_OFFSET; 242 timer->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET - OMAP_TIMER_V2_FUNC_OFFSET; 243 timer->irq_dis = OMAP_TIMER_V2_IRQENABLE_CLR - OMAP_TIMER_V2_FUNC_OFFSET; 244 timer->pend = timer->io_base + 245 _OMAP_TIMER_WRITE_PEND_OFFSET + 246 OMAP_TIMER_V2_FUNC_OFFSET; 247 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET; 248 } 249 } 250 251 /* 252 * __omap_dm_timer_enable_posted - enables write posted mode 253 * @timer: pointer to timer instance handle 254 * 255 * Enables the write posted mode for the timer. When posted mode is enabled 256 * writes to certain timer registers are immediately acknowledged by the 257 * internal bus and hence prevents stalling the CPU waiting for the write to 258 * complete. Enabling this feature can improve performance for writing to the 259 * timer registers. 260 */ 261 static inline void __omap_dm_timer_enable_posted(struct dmtimer *timer) 262 { 263 if (timer->posted) 264 return; 265 266 if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) { 267 timer->posted = OMAP_TIMER_NONPOSTED; 268 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0); 269 return; 270 } 271 272 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, OMAP_TIMER_CTRL_POSTED); 273 timer->context.tsicr = OMAP_TIMER_CTRL_POSTED; 274 timer->posted = OMAP_TIMER_POSTED; 275 } 276 277 static inline void __omap_dm_timer_stop(struct dmtimer *timer) 278 { 279 u32 l; 280 281 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 282 if (l & OMAP_TIMER_CTRL_ST) { 283 l &= ~0x1; 284 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 285 #ifdef CONFIG_ARCH_OMAP2PLUS 286 /* Readback to make sure write has completed */ 287 dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 288 /* 289 * Wait for functional clock period x 3.5 to make sure that 290 * timer is stopped 291 */ 292 udelay(3500000 / timer->fclk_rate + 1); 293 #endif 294 } 295 296 /* Ack possibly pending interrupt */ 297 dmtimer_write(timer, timer->irq_stat, OMAP_TIMER_INT_OVERFLOW); 298 } 299 300 static inline void __omap_dm_timer_int_enable(struct dmtimer *timer, 301 unsigned int value) 302 { 303 dmtimer_write(timer, timer->irq_ena, value); 304 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value); 305 } 306 307 static inline unsigned int 308 __omap_dm_timer_read_counter(struct dmtimer *timer) 309 { 310 return dmtimer_read(timer, OMAP_TIMER_COUNTER_REG); 311 } 312 313 static inline void __omap_dm_timer_write_status(struct dmtimer *timer, 314 unsigned int value) 315 { 316 dmtimer_write(timer, timer->irq_stat, value); 317 } 318 319 static void omap_timer_restore_context(struct dmtimer *timer) 320 { 321 dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, timer->context.ocp_cfg); 322 323 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, timer->context.twer); 324 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, timer->context.tcrr); 325 dmtimer_write(timer, OMAP_TIMER_LOAD_REG, timer->context.tldr); 326 dmtimer_write(timer, OMAP_TIMER_MATCH_REG, timer->context.tmar); 327 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr); 328 dmtimer_write(timer, timer->irq_ena, timer->context.tier); 329 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr); 330 } 331 332 static void omap_timer_save_context(struct dmtimer *timer) 333 { 334 timer->context.ocp_cfg = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET); 335 336 timer->context.tclr = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 337 timer->context.twer = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG); 338 timer->context.tldr = dmtimer_read(timer, OMAP_TIMER_LOAD_REG); 339 timer->context.tmar = dmtimer_read(timer, OMAP_TIMER_MATCH_REG); 340 timer->context.tier = dmtimer_read(timer, timer->irq_ena); 341 timer->context.tsicr = dmtimer_read(timer, OMAP_TIMER_IF_CTRL_REG); 342 } 343 344 static int omap_timer_context_notifier(struct notifier_block *nb, 345 unsigned long cmd, void *v) 346 { 347 struct dmtimer *timer; 348 349 timer = container_of(nb, struct dmtimer, nb); 350 351 switch (cmd) { 352 case CPU_CLUSTER_PM_ENTER: 353 if ((timer->capability & OMAP_TIMER_ALWON) || 354 !atomic_read(&timer->enabled)) 355 break; 356 omap_timer_save_context(timer); 357 break; 358 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */ 359 break; 360 case CPU_CLUSTER_PM_EXIT: 361 if ((timer->capability & OMAP_TIMER_ALWON) || 362 !atomic_read(&timer->enabled)) 363 break; 364 omap_timer_restore_context(timer); 365 break; 366 } 367 368 return NOTIFY_OK; 369 } 370 371 static int omap_timer_fclk_notifier(struct notifier_block *nb, 372 unsigned long event, void *data) 373 { 374 struct clk_notifier_data *clk_data = data; 375 struct dmtimer *timer = container_of(nb, struct dmtimer, fclk_nb); 376 377 switch (event) { 378 case POST_RATE_CHANGE: 379 timer->fclk_rate = clk_data->new_rate; 380 return NOTIFY_OK; 381 default: 382 return NOTIFY_DONE; 383 } 384 } 385 386 static int omap_dm_timer_reset(struct dmtimer *timer) 387 { 388 u32 l, timeout = 100000; 389 390 if (timer->revision != 1) 391 return -EINVAL; 392 393 dmtimer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); 394 395 do { 396 l = dmtimer_read(timer, OMAP_TIMER_V1_SYS_STAT_OFFSET); 397 } while (!l && timeout--); 398 399 if (!timeout) { 400 dev_err(&timer->pdev->dev, "Timer failed to reset\n"); 401 return -ETIMEDOUT; 402 } 403 404 /* Configure timer for smart-idle mode */ 405 l = dmtimer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET); 406 l |= 0x2 << 0x3; 407 dmtimer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l); 408 409 timer->posted = 0; 410 411 return 0; 412 } 413 414 /* 415 * Functions exposed to PWM and remoteproc drivers via platform_data. 416 * Do not use these in the driver, these will get deprecated and will 417 * will be replaced by Linux generic framework functions such as 418 * chained interrupts and clock framework. 419 */ 420 static struct dmtimer *to_dmtimer(struct omap_dm_timer *cookie) 421 { 422 if (!cookie) 423 return NULL; 424 425 return container_of(cookie, struct dmtimer, cookie); 426 } 427 428 static int omap_dm_timer_set_source(struct omap_dm_timer *cookie, int source) 429 { 430 int ret; 431 const char *parent_name; 432 struct clk *parent; 433 struct dmtimer_platform_data *pdata; 434 struct dmtimer *timer; 435 436 timer = to_dmtimer(cookie); 437 if (unlikely(!timer) || IS_ERR(timer->fclk)) 438 return -EINVAL; 439 440 switch (source) { 441 case OMAP_TIMER_SRC_SYS_CLK: 442 parent_name = "timer_sys_ck"; 443 break; 444 case OMAP_TIMER_SRC_32_KHZ: 445 parent_name = "timer_32k_ck"; 446 break; 447 case OMAP_TIMER_SRC_EXT_CLK: 448 parent_name = "timer_ext_ck"; 449 break; 450 default: 451 return -EINVAL; 452 } 453 454 pdata = timer->pdev->dev.platform_data; 455 456 /* 457 * FIXME: Used for OMAP1 devices only because they do not currently 458 * use the clock framework to set the parent clock. To be removed 459 * once OMAP1 migrated to using clock framework for dmtimers 460 */ 461 if (timer->omap1 && pdata && pdata->set_timer_src) 462 return pdata->set_timer_src(timer->pdev, source); 463 464 #if defined(CONFIG_COMMON_CLK) 465 /* Check if the clock has configurable parents */ 466 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) 467 return 0; 468 #endif 469 470 parent = clk_get(&timer->pdev->dev, parent_name); 471 if (IS_ERR(parent)) { 472 pr_err("%s: %s not found\n", __func__, parent_name); 473 return -EINVAL; 474 } 475 476 ret = clk_set_parent(timer->fclk, parent); 477 if (ret < 0) 478 pr_err("%s: failed to set %s as parent\n", __func__, 479 parent_name); 480 481 clk_put(parent); 482 483 return ret; 484 } 485 486 static void omap_dm_timer_enable(struct omap_dm_timer *cookie) 487 { 488 struct dmtimer *timer = to_dmtimer(cookie); 489 struct device *dev = &timer->pdev->dev; 490 int rc; 491 492 rc = pm_runtime_resume_and_get(dev); 493 if (rc) 494 dev_err(dev, "could not enable timer\n"); 495 } 496 497 static void omap_dm_timer_disable(struct omap_dm_timer *cookie) 498 { 499 struct dmtimer *timer = to_dmtimer(cookie); 500 struct device *dev = &timer->pdev->dev; 501 502 pm_runtime_put_sync(dev); 503 } 504 505 static int omap_dm_timer_prepare(struct dmtimer *timer) 506 { 507 struct device *dev = &timer->pdev->dev; 508 int rc; 509 510 rc = pm_runtime_resume_and_get(dev); 511 if (rc) 512 return rc; 513 514 if (timer->capability & OMAP_TIMER_NEEDS_RESET) { 515 rc = omap_dm_timer_reset(timer); 516 if (rc) { 517 pm_runtime_put_sync(dev); 518 return rc; 519 } 520 } 521 522 __omap_dm_timer_enable_posted(timer); 523 pm_runtime_put_sync(dev); 524 525 return 0; 526 } 527 528 static inline u32 omap_dm_timer_reserved_systimer(int id) 529 { 530 return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; 531 } 532 533 static struct dmtimer *_omap_dm_timer_request(int req_type, void *data) 534 { 535 struct dmtimer *timer = NULL, *t; 536 struct device_node *np = NULL; 537 unsigned long flags; 538 u32 cap = 0; 539 int id = 0; 540 541 switch (req_type) { 542 case REQUEST_BY_ID: 543 id = *(int *)data; 544 break; 545 case REQUEST_BY_CAP: 546 cap = *(u32 *)data; 547 break; 548 case REQUEST_BY_NODE: 549 np = (struct device_node *)data; 550 break; 551 default: 552 /* REQUEST_ANY */ 553 break; 554 } 555 556 spin_lock_irqsave(&dm_timer_lock, flags); 557 list_for_each_entry(t, &omap_timer_list, node) { 558 if (t->reserved) 559 continue; 560 561 switch (req_type) { 562 case REQUEST_BY_ID: 563 if (id == t->pdev->id) { 564 timer = t; 565 timer->reserved = 1; 566 goto found; 567 } 568 break; 569 case REQUEST_BY_CAP: 570 if (cap == (t->capability & cap)) { 571 /* 572 * If timer is not NULL, we have already found 573 * one timer. But it was not an exact match 574 * because it had more capabilities than what 575 * was required. Therefore, unreserve the last 576 * timer found and see if this one is a better 577 * match. 578 */ 579 if (timer) 580 timer->reserved = 0; 581 timer = t; 582 timer->reserved = 1; 583 584 /* Exit loop early if we find an exact match */ 585 if (t->capability == cap) 586 goto found; 587 } 588 break; 589 case REQUEST_BY_NODE: 590 if (np == t->pdev->dev.of_node) { 591 timer = t; 592 timer->reserved = 1; 593 goto found; 594 } 595 break; 596 default: 597 /* REQUEST_ANY */ 598 timer = t; 599 timer->reserved = 1; 600 goto found; 601 } 602 } 603 found: 604 spin_unlock_irqrestore(&dm_timer_lock, flags); 605 606 if (timer && omap_dm_timer_prepare(timer)) { 607 timer->reserved = 0; 608 timer = NULL; 609 } 610 611 if (!timer) 612 pr_debug("%s: timer request failed!\n", __func__); 613 614 return timer; 615 } 616 617 static struct omap_dm_timer *omap_dm_timer_request(void) 618 { 619 struct dmtimer *timer; 620 621 timer = _omap_dm_timer_request(REQUEST_ANY, NULL); 622 if (!timer) 623 return NULL; 624 625 return &timer->cookie; 626 } 627 628 static struct omap_dm_timer *omap_dm_timer_request_specific(int id) 629 { 630 struct dmtimer *timer; 631 632 /* Requesting timer by ID is not supported when device tree is used */ 633 if (of_have_populated_dt()) { 634 pr_warn("%s: Please use omap_dm_timer_request_by_node()\n", 635 __func__); 636 return NULL; 637 } 638 639 timer = _omap_dm_timer_request(REQUEST_BY_ID, &id); 640 if (!timer) 641 return NULL; 642 643 return &timer->cookie; 644 } 645 646 /** 647 * omap_dm_timer_request_by_node - Request a timer by device-tree node 648 * @np: Pointer to device-tree timer node 649 * 650 * Request a timer based upon a device node pointer. Returns pointer to 651 * timer handle on success and a NULL pointer on failure. 652 */ 653 static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np) 654 { 655 struct dmtimer *timer; 656 657 if (!np) 658 return NULL; 659 660 timer = _omap_dm_timer_request(REQUEST_BY_NODE, np); 661 if (!timer) 662 return NULL; 663 664 return &timer->cookie; 665 } 666 667 static int omap_dm_timer_free(struct omap_dm_timer *cookie) 668 { 669 struct dmtimer *timer; 670 struct device *dev; 671 int rc; 672 673 timer = to_dmtimer(cookie); 674 if (unlikely(!timer)) 675 return -EINVAL; 676 677 WARN_ON(!timer->reserved); 678 timer->reserved = 0; 679 680 dev = &timer->pdev->dev; 681 rc = pm_runtime_resume_and_get(dev); 682 if (rc) 683 return rc; 684 685 /* Clear timer configuration */ 686 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0); 687 688 pm_runtime_put_sync(dev); 689 690 return 0; 691 } 692 693 static int omap_dm_timer_get_irq(struct omap_dm_timer *cookie) 694 { 695 struct dmtimer *timer = to_dmtimer(cookie); 696 if (timer) 697 return timer->irq; 698 return -EINVAL; 699 } 700 701 #if defined(CONFIG_ARCH_OMAP1) 702 #include <linux/soc/ti/omap1-io.h> 703 704 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *cookie) 705 { 706 return NULL; 707 } 708 709 /** 710 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR 711 * @inputmask: current value of idlect mask 712 */ 713 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) 714 { 715 int i = 0; 716 struct dmtimer *timer = NULL; 717 unsigned long flags; 718 719 /* If ARMXOR cannot be idled this function call is unnecessary */ 720 if (!(inputmask & (1 << 1))) 721 return inputmask; 722 723 /* If any active timer is using ARMXOR return modified mask */ 724 spin_lock_irqsave(&dm_timer_lock, flags); 725 list_for_each_entry(timer, &omap_timer_list, node) { 726 u32 l; 727 728 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 729 if (l & OMAP_TIMER_CTRL_ST) { 730 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) 731 inputmask &= ~(1 << 1); 732 else 733 inputmask &= ~(1 << 2); 734 } 735 i++; 736 } 737 spin_unlock_irqrestore(&dm_timer_lock, flags); 738 739 return inputmask; 740 } 741 742 #else 743 744 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *cookie) 745 { 746 struct dmtimer *timer = to_dmtimer(cookie); 747 748 if (timer && !IS_ERR(timer->fclk)) 749 return timer->fclk; 750 return NULL; 751 } 752 753 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) 754 { 755 BUG(); 756 757 return 0; 758 } 759 760 #endif 761 762 static int omap_dm_timer_start(struct omap_dm_timer *cookie) 763 { 764 struct dmtimer *timer; 765 struct device *dev; 766 int rc; 767 u32 l; 768 769 timer = to_dmtimer(cookie); 770 if (unlikely(!timer)) 771 return -EINVAL; 772 773 dev = &timer->pdev->dev; 774 775 rc = pm_runtime_resume_and_get(dev); 776 if (rc) 777 return rc; 778 779 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 780 if (!(l & OMAP_TIMER_CTRL_ST)) { 781 l |= OMAP_TIMER_CTRL_ST; 782 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 783 } 784 785 return 0; 786 } 787 788 static int omap_dm_timer_stop(struct omap_dm_timer *cookie) 789 { 790 struct dmtimer *timer; 791 struct device *dev; 792 793 timer = to_dmtimer(cookie); 794 if (unlikely(!timer)) 795 return -EINVAL; 796 797 dev = &timer->pdev->dev; 798 799 __omap_dm_timer_stop(timer); 800 801 pm_runtime_put_sync(dev); 802 803 return 0; 804 } 805 806 static int omap_dm_timer_set_load(struct omap_dm_timer *cookie, 807 unsigned int load) 808 { 809 struct dmtimer *timer; 810 struct device *dev; 811 int rc; 812 813 timer = to_dmtimer(cookie); 814 if (unlikely(!timer)) 815 return -EINVAL; 816 817 dev = &timer->pdev->dev; 818 rc = pm_runtime_resume_and_get(dev); 819 if (rc) 820 return rc; 821 822 dmtimer_write(timer, OMAP_TIMER_LOAD_REG, load); 823 824 pm_runtime_put_sync(dev); 825 826 return 0; 827 } 828 829 static int omap_dm_timer_set_match(struct omap_dm_timer *cookie, int enable, 830 unsigned int match) 831 { 832 struct dmtimer *timer; 833 struct device *dev; 834 int rc; 835 u32 l; 836 837 timer = to_dmtimer(cookie); 838 if (unlikely(!timer)) 839 return -EINVAL; 840 841 dev = &timer->pdev->dev; 842 rc = pm_runtime_resume_and_get(dev); 843 if (rc) 844 return rc; 845 846 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 847 if (enable) 848 l |= OMAP_TIMER_CTRL_CE; 849 else 850 l &= ~OMAP_TIMER_CTRL_CE; 851 dmtimer_write(timer, OMAP_TIMER_MATCH_REG, match); 852 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 853 854 pm_runtime_put_sync(dev); 855 856 return 0; 857 } 858 859 static int omap_dm_timer_set_cap(struct omap_dm_timer *cookie, 860 int autoreload, bool config_period) 861 { 862 struct dmtimer *timer; 863 struct device *dev; 864 int rc; 865 u32 l; 866 867 timer = to_dmtimer(cookie); 868 if (unlikely(!timer)) 869 return -EINVAL; 870 871 dev = &timer->pdev->dev; 872 rc = pm_runtime_resume_and_get(dev); 873 if (rc) 874 return rc; 875 /* 876 * 1. Select autoreload mode. TIMER_TCLR[1] AR bit. 877 * 2. TIMER_TCLR[14]: Sets the functionality of the TIMER IO pin. 878 * 3. TIMER_TCLR[13] : Capture mode select bit. 879 * 3. TIMER_TCLR[9-8] : Select transition capture mode. 880 */ 881 882 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 883 884 if (autoreload) 885 l |= OMAP_TIMER_CTRL_AR; 886 887 l |= OMAP_TIMER_CTRL_CAPTMODE | OMAP_TIMER_CTRL_GPOCFG; 888 889 if (config_period == true) 890 l |= OMAP_TIMER_CTRL_TCM_LOWTOHIGH; /* Time Period config */ 891 else 892 l |= OMAP_TIMER_CTRL_TCM_BOTHEDGES; /* Duty Cycle config */ 893 894 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 895 896 pm_runtime_put_sync(dev); 897 898 return 0; 899 } 900 901 static int omap_dm_timer_set_pwm(struct omap_dm_timer *cookie, int def_on, 902 int toggle, int trigger, int autoreload) 903 { 904 struct dmtimer *timer; 905 struct device *dev; 906 int rc; 907 u32 l; 908 909 timer = to_dmtimer(cookie); 910 if (unlikely(!timer)) 911 return -EINVAL; 912 913 dev = &timer->pdev->dev; 914 rc = pm_runtime_resume_and_get(dev); 915 if (rc) 916 return rc; 917 918 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 919 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | 920 OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR); 921 if (def_on) 922 l |= OMAP_TIMER_CTRL_SCPWM; 923 if (toggle) 924 l |= OMAP_TIMER_CTRL_PT; 925 l |= trigger << 10; 926 if (autoreload) 927 l |= OMAP_TIMER_CTRL_AR; 928 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 929 930 pm_runtime_put_sync(dev); 931 932 return 0; 933 } 934 935 static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *cookie) 936 { 937 struct dmtimer *timer; 938 struct device *dev; 939 int rc; 940 u32 l; 941 942 timer = to_dmtimer(cookie); 943 if (unlikely(!timer)) 944 return -EINVAL; 945 946 dev = &timer->pdev->dev; 947 rc = pm_runtime_resume_and_get(dev); 948 if (rc) 949 return rc; 950 951 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 952 953 pm_runtime_put_sync(dev); 954 955 return l; 956 } 957 958 static int omap_dm_timer_set_prescaler(struct omap_dm_timer *cookie, 959 int prescaler) 960 { 961 struct dmtimer *timer; 962 struct device *dev; 963 int rc; 964 u32 l; 965 966 timer = to_dmtimer(cookie); 967 if (unlikely(!timer) || prescaler < -1 || prescaler > 7) 968 return -EINVAL; 969 970 dev = &timer->pdev->dev; 971 rc = pm_runtime_resume_and_get(dev); 972 if (rc) 973 return rc; 974 975 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 976 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); 977 if (prescaler >= 0) { 978 l |= OMAP_TIMER_CTRL_PRE; 979 l |= prescaler << 2; 980 } 981 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 982 983 pm_runtime_put_sync(dev); 984 985 return 0; 986 } 987 988 static int omap_dm_timer_set_int_enable(struct omap_dm_timer *cookie, 989 unsigned int value) 990 { 991 struct dmtimer *timer; 992 struct device *dev; 993 int rc; 994 995 timer = to_dmtimer(cookie); 996 if (unlikely(!timer)) 997 return -EINVAL; 998 999 dev = &timer->pdev->dev; 1000 rc = pm_runtime_resume_and_get(dev); 1001 if (rc) 1002 return rc; 1003 1004 __omap_dm_timer_int_enable(timer, value); 1005 1006 pm_runtime_put_sync(dev); 1007 1008 return 0; 1009 } 1010 1011 /** 1012 * omap_dm_timer_set_int_disable - disable timer interrupts 1013 * @cookie: pointer to timer cookie 1014 * @mask: bit mask of interrupts to be disabled 1015 * 1016 * Disables the specified timer interrupts for a timer. 1017 */ 1018 static int omap_dm_timer_set_int_disable(struct omap_dm_timer *cookie, u32 mask) 1019 { 1020 struct dmtimer *timer; 1021 struct device *dev; 1022 u32 l = mask; 1023 int rc; 1024 1025 timer = to_dmtimer(cookie); 1026 if (unlikely(!timer)) 1027 return -EINVAL; 1028 1029 dev = &timer->pdev->dev; 1030 rc = pm_runtime_resume_and_get(dev); 1031 if (rc) 1032 return rc; 1033 1034 if (timer->revision == 1) 1035 l = dmtimer_read(timer, timer->irq_ena) & ~mask; 1036 1037 dmtimer_write(timer, timer->irq_dis, l); 1038 l = dmtimer_read(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; 1039 dmtimer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, l); 1040 1041 pm_runtime_put_sync(dev); 1042 1043 return 0; 1044 } 1045 1046 static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *cookie) 1047 { 1048 struct dmtimer *timer; 1049 unsigned int l; 1050 1051 timer = to_dmtimer(cookie); 1052 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 1053 pr_err("%s: timer not available or enabled.\n", __func__); 1054 return 0; 1055 } 1056 1057 l = dmtimer_read(timer, timer->irq_stat); 1058 1059 return l; 1060 } 1061 1062 static int omap_dm_timer_write_status(struct omap_dm_timer *cookie, unsigned int value) 1063 { 1064 struct dmtimer *timer; 1065 1066 timer = to_dmtimer(cookie); 1067 if (unlikely(!timer || !atomic_read(&timer->enabled))) 1068 return -EINVAL; 1069 1070 __omap_dm_timer_write_status(timer, value); 1071 1072 return 0; 1073 } 1074 1075 static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *cookie) 1076 { 1077 struct dmtimer *timer; 1078 1079 timer = to_dmtimer(cookie); 1080 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 1081 pr_err("%s: timer not iavailable or enabled.\n", __func__); 1082 return 0; 1083 } 1084 1085 return __omap_dm_timer_read_counter(timer); 1086 } 1087 1088 static inline unsigned int __omap_dm_timer_cap(struct dmtimer *timer, int idx) 1089 { 1090 return idx == 0 ? dmtimer_read(timer, OMAP_TIMER_CAPTURE_REG) : 1091 dmtimer_read(timer, OMAP_TIMER_CAPTURE2_REG); 1092 } 1093 1094 static int omap_dm_timer_write_counter(struct omap_dm_timer *cookie, unsigned int value) 1095 { 1096 struct dmtimer *timer; 1097 struct device *dev; 1098 int ret; 1099 1100 timer = to_dmtimer(cookie); 1101 if (unlikely(!timer)) { 1102 pr_err("%s: timer not available.\n", __func__); 1103 return -EINVAL; 1104 } 1105 1106 dev = &timer->pdev->dev; 1107 1108 ret = pm_runtime_resume_and_get(dev); 1109 if (ret < 0) 1110 return ret; 1111 1112 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, value); 1113 pm_runtime_put_sync(dev); 1114 1115 /* Save the context */ 1116 timer->context.tcrr = value; 1117 return 0; 1118 } 1119 1120 /** 1121 * omap_dm_timer_cap_counter() - Calculate the high count or period count depending on the 1122 * configuration. 1123 * @cookie:Pointer to OMAP DM timer 1124 * @is_period:Whether to configure timer in period or duty cycle mode 1125 * 1126 * Return high count or period count if timer is enabled else appropriate error. 1127 */ 1128 static unsigned int omap_dm_timer_cap_counter(struct omap_dm_timer *cookie, bool is_period) 1129 { 1130 struct dmtimer *timer; 1131 unsigned int cap1 = 0; 1132 unsigned int cap2 = 0; 1133 u32 l, ret; 1134 1135 timer = to_dmtimer(cookie); 1136 if (unlikely(!timer || !atomic_read(&timer->enabled))) { 1137 pr_err("%s:timer is not available or enabled.%p\n", __func__, (void *)timer); 1138 return -EINVAL; 1139 } 1140 1141 /* Stop the timer */ 1142 omap_dm_timer_stop(cookie); 1143 1144 /* Clear the timer counter value to 0 */ 1145 ret = omap_dm_timer_write_counter(cookie, 0); 1146 if (ret) 1147 return ret; 1148 1149 /* Sets the timer capture configuration for period/duty cycle calculation */ 1150 ret = omap_dm_timer_set_cap(cookie, true, is_period); 1151 if (ret) { 1152 pr_err("%s: Failed to set timer capture configuration.\n", __func__); 1153 return ret; 1154 } 1155 /* Start the timer */ 1156 omap_dm_timer_start(cookie); 1157 1158 /* 1159 * 1 sec delay is given so as to provide 1160 * enough time to capture low frequency signals. 1161 */ 1162 msleep(1000); 1163 1164 cap1 = __omap_dm_timer_cap(timer, 0); 1165 cap2 = __omap_dm_timer_cap(timer, 1); 1166 1167 /* 1168 * Clears the TCLR configuration. 1169 * The start bit must be set to 1 as the timer is already in start mode. 1170 */ 1171 l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 1172 l &= ~(0xffff) | 0x1; 1173 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 1174 1175 return (cap2-cap1); 1176 } 1177 1178 static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev) 1179 { 1180 struct dmtimer *timer = dev_get_drvdata(dev); 1181 1182 atomic_set(&timer->enabled, 0); 1183 1184 if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base) 1185 return 0; 1186 1187 omap_timer_save_context(timer); 1188 1189 return 0; 1190 } 1191 1192 static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev) 1193 { 1194 struct dmtimer *timer = dev_get_drvdata(dev); 1195 1196 if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base) 1197 omap_timer_restore_context(timer); 1198 1199 atomic_set(&timer->enabled, 1); 1200 1201 return 0; 1202 } 1203 1204 static const struct dev_pm_ops omap_dm_timer_pm_ops = { 1205 SET_RUNTIME_PM_OPS(omap_dm_timer_runtime_suspend, 1206 omap_dm_timer_runtime_resume, NULL) 1207 }; 1208 1209 static const struct of_device_id omap_timer_match[]; 1210 1211 static struct dmtimer_clocksource *omap_dm_timer_to_clocksource(struct clocksource *cs) 1212 { 1213 return container_of(cs, struct dmtimer_clocksource, dev); 1214 } 1215 1216 static u64 omap_dm_timer_read_cycles(struct clocksource *cs) 1217 { 1218 struct dmtimer_clocksource *clksrc = omap_dm_timer_to_clocksource(cs); 1219 struct dmtimer *timer = clksrc->timer; 1220 1221 return (u64)__omap_dm_timer_read_counter(timer); 1222 } 1223 1224 static u64 notrace omap_dm_timer_read_sched_clock(void) 1225 { 1226 /* Posted mode is not active here, so we can read directly */ 1227 return readl_relaxed(omap_dm_timer_sched_clock_counter); 1228 } 1229 1230 static void omap_dm_timer_clocksource_suspend(struct clocksource *cs) 1231 { 1232 struct dmtimer_clocksource *clksrc = omap_dm_timer_to_clocksource(cs); 1233 struct dmtimer *timer = clksrc->timer; 1234 1235 clksrc->loadval = __omap_dm_timer_read_counter(timer); 1236 __omap_dm_timer_stop(timer); 1237 } 1238 1239 static void omap_dm_timer_clocksource_resume(struct clocksource *cs) 1240 { 1241 struct dmtimer_clocksource *clksrc = omap_dm_timer_to_clocksource(cs); 1242 struct dmtimer *timer = clksrc->timer; 1243 1244 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, clksrc->loadval); 1245 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR); 1246 } 1247 1248 static void omap_dm_timer_clocksource_unregister(void *data) 1249 { 1250 struct clocksource *cs = data; 1251 1252 clocksource_unregister(cs); 1253 } 1254 1255 static int omap_dm_timer_setup_clocksource(struct dmtimer *timer) 1256 { 1257 struct device *dev = &timer->pdev->dev; 1258 struct dmtimer_clocksource *clksrc; 1259 int err; 1260 1261 __omap_dm_timer_init_regs(timer); 1262 1263 timer->reserved = 1; 1264 1265 clksrc = devm_kzalloc(dev, sizeof(*clksrc), GFP_KERNEL); 1266 if (!clksrc) 1267 return -ENOMEM; 1268 1269 clksrc->timer = timer; 1270 1271 clksrc->dev.name = "omap_dm_timer"; 1272 clksrc->dev.rating = 300; 1273 clksrc->dev.read = omap_dm_timer_read_cycles; 1274 clksrc->dev.mask = CLOCKSOURCE_MASK(32); 1275 clksrc->dev.flags = CLOCK_SOURCE_IS_CONTINUOUS; 1276 clksrc->dev.suspend = omap_dm_timer_clocksource_suspend; 1277 clksrc->dev.resume = omap_dm_timer_clocksource_resume; 1278 1279 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, 0); 1280 dmtimer_write(timer, OMAP_TIMER_LOAD_REG, 0); 1281 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR); 1282 1283 omap_dm_timer_sched_clock_counter = timer->func_base + _OMAP_TIMER_COUNTER_OFFSET; 1284 sched_clock_register(omap_dm_timer_read_sched_clock, 32, timer->fclk_rate); 1285 1286 err = clocksource_register_hz(&clksrc->dev, timer->fclk_rate); 1287 if (err) 1288 return dev_err_probe(dev, err, "Could not register as clocksource\n"); 1289 1290 err = devm_add_action_or_reset(dev, omap_dm_timer_clocksource_unregister, &clksrc->dev); 1291 if (err) 1292 return dev_err_probe(dev, err, "Could not register clocksource_unregister action\n"); 1293 1294 return 0; 1295 } 1296 1297 static struct omap_dm_timer_clockevent *to_dm_timer_clockevent(struct clock_event_device *evt) 1298 { 1299 return container_of(evt, struct omap_dm_timer_clockevent, dev); 1300 } 1301 1302 static int omap_dm_timer_evt_set_next_event(unsigned long cycles, 1303 struct clock_event_device *evt) 1304 { 1305 struct omap_dm_timer_clockevent *clkevt = to_dm_timer_clockevent(evt); 1306 struct dmtimer *timer = clkevt->timer; 1307 1308 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, 0xffffffff - cycles); 1309 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST); 1310 1311 return 0; 1312 } 1313 1314 static int omap_dm_timer_evt_shutdown(struct clock_event_device *evt) 1315 { 1316 struct omap_dm_timer_clockevent *clkevt = to_dm_timer_clockevent(evt); 1317 struct dmtimer *timer = clkevt->timer; 1318 1319 __omap_dm_timer_stop(timer); 1320 1321 return 0; 1322 } 1323 1324 static int omap_dm_timer_evt_set_periodic(struct clock_event_device *evt) 1325 { 1326 struct omap_dm_timer_clockevent *clkevt = to_dm_timer_clockevent(evt); 1327 struct dmtimer *timer = clkevt->timer; 1328 1329 omap_dm_timer_evt_shutdown(evt); 1330 1331 omap_dm_timer_set_load(&timer->cookie, clkevt->period); 1332 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, clkevt->period); 1333 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 1334 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST); 1335 1336 return 0; 1337 } 1338 1339 static irqreturn_t omap_dm_timer_evt_interrupt(int irq, void *dev_id) 1340 { 1341 struct omap_dm_timer_clockevent *clkevt = dev_id; 1342 struct dmtimer *timer = clkevt->timer; 1343 1344 __omap_dm_timer_write_status(timer, OMAP_TIMER_INT_OVERFLOW); 1345 1346 clkevt->dev.event_handler(&clkevt->dev); 1347 1348 return IRQ_HANDLED; 1349 } 1350 1351 static int omap_dm_timer_setup_clockevent(struct dmtimer *timer) 1352 { 1353 struct device *dev = &timer->pdev->dev; 1354 struct omap_dm_timer_clockevent *clkevt; 1355 int ret; 1356 1357 clkevt = devm_kzalloc(dev, sizeof(*clkevt), GFP_KERNEL); 1358 if (!clkevt) 1359 return -ENOMEM; 1360 1361 timer->reserved = 1; 1362 clkevt->timer = timer; 1363 1364 clkevt->dev.name = "omap_dm_timer"; 1365 clkevt->dev.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; 1366 clkevt->dev.rating = 300; 1367 clkevt->dev.set_next_event = omap_dm_timer_evt_set_next_event; 1368 clkevt->dev.set_state_shutdown = omap_dm_timer_evt_shutdown; 1369 clkevt->dev.set_state_periodic = omap_dm_timer_evt_set_periodic; 1370 clkevt->dev.set_state_oneshot = omap_dm_timer_evt_shutdown; 1371 clkevt->dev.set_state_oneshot_stopped = omap_dm_timer_evt_shutdown; 1372 clkevt->dev.tick_resume = omap_dm_timer_evt_shutdown; 1373 clkevt->dev.cpumask = cpu_possible_mask; 1374 clkevt->period = 0xffffffff - DIV_ROUND_CLOSEST(timer->fclk_rate, HZ); 1375 1376 __omap_dm_timer_init_regs(timer); 1377 __omap_dm_timer_stop(timer); 1378 __omap_dm_timer_enable_posted(timer); 1379 1380 ret = devm_request_irq(dev, timer->irq, omap_dm_timer_evt_interrupt, 1381 IRQF_TIMER, "omap_dm_timer_clockevent", clkevt); 1382 if (ret) 1383 return ret; 1384 1385 __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW); 1386 1387 clockevents_config_and_register(&clkevt->dev, timer->fclk_rate, 1388 3, 1389 0xffffffff); 1390 1391 omap_dm_timer_clockevent_setup = true; 1392 return 0; 1393 } 1394 1395 /** 1396 * omap_dm_timer_probe - probe function called for every registered device 1397 * @pdev: pointer to current timer platform device 1398 * 1399 * Called by driver framework at the end of device registration for all 1400 * timer devices. 1401 */ 1402 static int omap_dm_timer_probe(struct platform_device *pdev) 1403 { 1404 unsigned long flags; 1405 struct dmtimer *timer; 1406 struct device *dev = &pdev->dev; 1407 const struct dmtimer_platform_data *pdata; 1408 int ret; 1409 1410 pdata = of_device_get_match_data(dev); 1411 if (!pdata) 1412 pdata = dev_get_platdata(dev); 1413 else 1414 dev->platform_data = (void *)pdata; 1415 1416 if (!pdata) { 1417 dev_err(dev, "%s: no platform data.\n", __func__); 1418 return -ENODEV; 1419 } 1420 1421 timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL); 1422 if (!timer) 1423 return -ENOMEM; 1424 1425 timer->irq = platform_get_irq(pdev, 0); 1426 if (timer->irq < 0) { 1427 if (of_property_read_bool(dev->of_node, "ti,timer-pwm")) 1428 dev_info(dev, "Did not find timer interrupt, timer usable in PWM mode only\n"); 1429 else 1430 return timer->irq; 1431 } 1432 1433 timer->io_base = devm_platform_ioremap_resource(pdev, 0); 1434 if (IS_ERR(timer->io_base)) 1435 return PTR_ERR(timer->io_base); 1436 1437 platform_set_drvdata(pdev, timer); 1438 1439 if (dev->of_node) { 1440 if (of_property_read_bool(dev->of_node, "ti,timer-alwon")) 1441 timer->capability |= OMAP_TIMER_ALWON; 1442 if (of_property_read_bool(dev->of_node, "ti,timer-dsp")) 1443 timer->capability |= OMAP_TIMER_HAS_DSP_IRQ; 1444 if (of_property_read_bool(dev->of_node, "ti,timer-pwm")) 1445 timer->capability |= OMAP_TIMER_HAS_PWM; 1446 if (of_property_read_bool(dev->of_node, "ti,timer-secure")) 1447 timer->capability |= OMAP_TIMER_SECURE; 1448 } else { 1449 timer->id = pdev->id; 1450 timer->capability = pdata->timer_capability; 1451 timer->reserved = omap_dm_timer_reserved_systimer(timer->id); 1452 } 1453 1454 timer->omap1 = timer->capability & OMAP_TIMER_NEEDS_RESET; 1455 1456 /* OMAP1 devices do not yet use the clock framework for dmtimers */ 1457 if (!timer->omap1) { 1458 timer->fclk = devm_clk_get(dev, "fck"); 1459 if (IS_ERR(timer->fclk)) 1460 return PTR_ERR(timer->fclk); 1461 1462 timer->fclk_nb.notifier_call = omap_timer_fclk_notifier; 1463 ret = devm_clk_notifier_register(dev, timer->fclk, 1464 &timer->fclk_nb); 1465 if (ret) 1466 return ret; 1467 1468 timer->fclk_rate = clk_get_rate(timer->fclk); 1469 } else { 1470 timer->fclk = ERR_PTR(-ENODEV); 1471 } 1472 1473 if (!(timer->capability & OMAP_TIMER_ALWON)) { 1474 timer->nb.notifier_call = omap_timer_context_notifier; 1475 cpu_pm_register_notifier(&timer->nb); 1476 } 1477 1478 timer->errata = pdata->timer_errata; 1479 1480 timer->pdev = pdev; 1481 1482 if (pdata->system_timer_capable && 1483 timer->capability & OMAP_TIMER_ALWON && !IS_ERR_OR_NULL(timer->fclk)) { 1484 if (!omap_dm_timer_sched_clock_counter) { 1485 ret = omap_dm_timer_setup_clocksource(timer); 1486 if (ret) 1487 return ret; 1488 } else if (!omap_dm_timer_clockevent_setup) { 1489 ret = omap_dm_timer_setup_clockevent(timer); 1490 if (ret) 1491 return ret; 1492 } 1493 } 1494 1495 pm_runtime_enable(dev); 1496 1497 if (!timer->reserved) { 1498 ret = pm_runtime_resume_and_get(dev); 1499 if (ret) { 1500 dev_err(dev, "%s: pm_runtime_get_sync failed!\n", 1501 __func__); 1502 goto err_disable; 1503 } 1504 __omap_dm_timer_init_regs(timer); 1505 1506 /* Clear timer configuration */ 1507 dmtimer_write(timer, OMAP_TIMER_CTRL_REG, 0); 1508 1509 pm_runtime_put(dev); 1510 } 1511 1512 /* add the timer element to the list */ 1513 spin_lock_irqsave(&dm_timer_lock, flags); 1514 list_add_tail(&timer->node, &omap_timer_list); 1515 spin_unlock_irqrestore(&dm_timer_lock, flags); 1516 1517 dev_dbg(dev, "Device Probed.\n"); 1518 1519 return 0; 1520 1521 err_disable: 1522 pm_runtime_disable(dev); 1523 return ret; 1524 } 1525 1526 /** 1527 * omap_dm_timer_remove - cleanup a registered timer device 1528 * @pdev: pointer to current timer platform device 1529 * 1530 * Called by driver framework whenever a timer device is unregistered. 1531 * In addition to freeing platform resources it also deletes the timer 1532 * entry from the local list. 1533 */ 1534 static void omap_dm_timer_remove(struct platform_device *pdev) 1535 { 1536 struct dmtimer *timer, *found = NULL; 1537 unsigned long flags; 1538 int ret = -EINVAL; 1539 1540 spin_lock_irqsave(&dm_timer_lock, flags); 1541 list_for_each_entry(timer, &omap_timer_list, node) 1542 if (!strcmp(dev_name(&timer->pdev->dev), 1543 dev_name(&pdev->dev))) { 1544 list_del(&timer->node); 1545 found = timer; 1546 ret = 0; 1547 break; 1548 } 1549 spin_unlock_irqrestore(&dm_timer_lock, flags); 1550 1551 /* Unregister outside the lock: cpu_pm_unregister_notifier() may sleep. */ 1552 if (found && !(found->capability & OMAP_TIMER_ALWON)) 1553 cpu_pm_unregister_notifier(&found->nb); 1554 1555 pm_runtime_disable(&pdev->dev); 1556 1557 if (ret) 1558 dev_err(&pdev->dev, "Unable to determine timer entry in list of drivers on remove\n"); 1559 } 1560 1561 static const struct omap_dm_timer_ops dmtimer_ops = { 1562 .request_by_node = omap_dm_timer_request_by_node, 1563 .request_specific = omap_dm_timer_request_specific, 1564 .request = omap_dm_timer_request, 1565 .set_source = omap_dm_timer_set_source, 1566 .get_irq = omap_dm_timer_get_irq, 1567 .set_int_enable = omap_dm_timer_set_int_enable, 1568 .set_int_disable = omap_dm_timer_set_int_disable, 1569 .free = omap_dm_timer_free, 1570 .enable = omap_dm_timer_enable, 1571 .disable = omap_dm_timer_disable, 1572 .get_fclk = omap_dm_timer_get_fclk, 1573 .start = omap_dm_timer_start, 1574 .stop = omap_dm_timer_stop, 1575 .set_load = omap_dm_timer_set_load, 1576 .set_match = omap_dm_timer_set_match, 1577 .set_pwm = omap_dm_timer_set_pwm, 1578 .get_pwm_status = omap_dm_timer_get_pwm_status, 1579 .set_prescaler = omap_dm_timer_set_prescaler, 1580 .read_counter = omap_dm_timer_read_counter, 1581 .write_counter = omap_dm_timer_write_counter, 1582 .read_status = omap_dm_timer_read_status, 1583 .write_status = omap_dm_timer_write_status, 1584 .set_cap = omap_dm_timer_set_cap, 1585 .get_cap_status = omap_dm_timer_get_pwm_status, 1586 .read_cap = omap_dm_timer_cap_counter, 1587 }; 1588 1589 static const struct dmtimer_platform_data omap3plus_pdata = { 1590 .timer_errata = OMAP_TIMER_ERRATA_I103_I767, 1591 .timer_ops = &dmtimer_ops, 1592 }; 1593 1594 static const struct dmtimer_platform_data am6_pdata = { 1595 .timer_ops = &dmtimer_ops, 1596 .system_timer_capable = true, 1597 }; 1598 1599 static const struct of_device_id omap_timer_match[] = { 1600 { 1601 .compatible = "ti,omap2420-timer", 1602 }, 1603 { 1604 .compatible = "ti,omap3430-timer", 1605 .data = &omap3plus_pdata, 1606 }, 1607 { 1608 .compatible = "ti,omap4430-timer", 1609 .data = &omap3plus_pdata, 1610 }, 1611 { 1612 .compatible = "ti,omap5430-timer", 1613 .data = &omap3plus_pdata, 1614 }, 1615 { 1616 .compatible = "ti,am335x-timer", 1617 .data = &omap3plus_pdata, 1618 }, 1619 { 1620 .compatible = "ti,am335x-timer-1ms", 1621 .data = &omap3plus_pdata, 1622 }, 1623 { 1624 .compatible = "ti,dm816-timer", 1625 .data = &omap3plus_pdata, 1626 }, 1627 { 1628 .compatible = "ti,am654-timer", 1629 .data = &am6_pdata, 1630 }, 1631 {}, 1632 }; 1633 MODULE_DEVICE_TABLE(of, omap_timer_match); 1634 1635 static struct platform_driver omap_dm_timer_driver = { 1636 .probe = omap_dm_timer_probe, 1637 .remove = omap_dm_timer_remove, 1638 .driver = { 1639 .name = "omap_timer", 1640 .of_match_table = omap_timer_match, 1641 .pm = &omap_dm_timer_pm_ops, 1642 }, 1643 }; 1644 1645 module_platform_driver(omap_dm_timer_driver); 1646 1647 MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); 1648 MODULE_AUTHOR("Texas Instruments Inc"); 1649