1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * linux/drivers/clocksource/timer-sp.c 4 * 5 * Copyright (C) 1999 - 2003 ARM Limited 6 * Copyright (C) 2000 Deep Blue Solutions Ltd 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/clk.h> 12 #include <linux/clocksource.h> 13 #include <linux/clockchips.h> 14 #include <linux/err.h> 15 #include <linux/interrupt.h> 16 #include <linux/irq.h> 17 #include <linux/io.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/of_clk.h> 21 #include <linux/of_irq.h> 22 #include <linux/sched_clock.h> 23 24 #ifdef CONFIG_ARM 25 #include <linux/delay.h> 26 #endif 27 28 #include "timer-sp.h" 29 30 /* Hisilicon 64-bit timer(a variant of ARM SP804) */ 31 #define HISI_TIMER_1_BASE 0x00 32 #define HISI_TIMER_2_BASE 0x40 33 #define HISI_TIMER_LOAD 0x00 34 #define HISI_TIMER_LOAD_H 0x04 35 #define HISI_TIMER_VALUE 0x08 36 #define HISI_TIMER_VALUE_H 0x0c 37 #define HISI_TIMER_CTRL 0x10 38 #define HISI_TIMER_INTCLR 0x14 39 #define HISI_TIMER_RIS 0x18 40 #define HISI_TIMER_MIS 0x1c 41 #define HISI_TIMER_BGLOAD 0x20 42 #define HISI_TIMER_BGLOAD_H 0x24 43 44 static struct sp804_timer arm_sp804_timer __initdata = { 45 .load = TIMER_LOAD, 46 .value = TIMER_VALUE, 47 .ctrl = TIMER_CTRL, 48 .intclr = TIMER_INTCLR, 49 .timer_base = {TIMER_1_BASE, TIMER_2_BASE}, 50 .width = 32, 51 }; 52 53 static struct sp804_timer hisi_sp804_timer __initdata = { 54 .load = HISI_TIMER_LOAD, 55 .load_h = HISI_TIMER_LOAD_H, 56 .value = HISI_TIMER_VALUE, 57 .value_h = HISI_TIMER_VALUE_H, 58 .ctrl = HISI_TIMER_CTRL, 59 .intclr = HISI_TIMER_INTCLR, 60 .timer_base = {HISI_TIMER_1_BASE, HISI_TIMER_2_BASE}, 61 .width = 64, 62 }; 63 64 static struct sp804_clkevt sp804_clkevt[NR_TIMERS]; 65 66 static long __init sp804_get_clock_rate(struct clk *clk, const char *name) 67 { 68 int err; 69 70 if (!clk) 71 clk = clk_get_sys("sp804", name); 72 if (IS_ERR(clk)) { 73 pr_err("%s clock not found: %ld\n", name, PTR_ERR(clk)); 74 return PTR_ERR(clk); 75 } 76 77 err = clk_prepare_enable(clk); 78 if (err) { 79 pr_err("clock failed to enable: %d\n", err); 80 clk_put(clk); 81 return err; 82 } 83 84 return clk_get_rate(clk); 85 } 86 87 static struct sp804_clkevt * __init sp804_clkevt_get(void __iomem *base) 88 { 89 int i; 90 91 for (i = 0; i < NR_TIMERS; i++) { 92 if (sp804_clkevt[i].base == base) 93 return &sp804_clkevt[i]; 94 } 95 96 /* It's impossible to reach here */ 97 WARN_ON(1); 98 99 return NULL; 100 } 101 102 static struct sp804_clkevt *sched_clkevt; 103 104 static u64 notrace sp804_read(void) 105 { 106 return ~readl_relaxed(sched_clkevt->value); 107 } 108 109 #ifdef CONFIG_ARM 110 static struct delay_timer delay; 111 static unsigned long sp804_read_delay_timer_read(void) 112 { 113 return sp804_read(); 114 } 115 116 static void sp804_register_delay_timer(int freq) 117 { 118 delay.freq = freq; 119 delay.read_current_timer = sp804_read_delay_timer_read; 120 register_current_timer_delay(&delay); 121 } 122 #else 123 static inline void sp804_register_delay_timer(int freq) {} 124 #endif 125 126 static int __init sp804_clocksource_and_sched_clock_init(void __iomem *base, 127 const char *name, 128 struct clk *clk, 129 int use_sched_clock) 130 { 131 long rate; 132 struct sp804_clkevt *clkevt; 133 134 rate = sp804_get_clock_rate(clk, name); 135 if (rate < 0) 136 return -EINVAL; 137 138 sp804_register_delay_timer(rate); 139 140 clkevt = sp804_clkevt_get(base); 141 142 writel(0, clkevt->ctrl); 143 writel(0xffffffff, clkevt->load); 144 writel(0xffffffff, clkevt->value); 145 if (clkevt->width == 64) { 146 writel(0xffffffff, clkevt->load_h); 147 writel(0xffffffff, clkevt->value_h); 148 } 149 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, 150 clkevt->ctrl); 151 152 clocksource_mmio_init(clkevt->value, name, 153 rate, 200, 32, clocksource_mmio_readl_down); 154 155 if (use_sched_clock) { 156 sched_clkevt = clkevt; 157 sched_clock_register(sp804_read, 32, rate); 158 } 159 160 return 0; 161 } 162 163 164 static struct sp804_clkevt *common_clkevt; 165 166 /* 167 * IRQ handler for the timer 168 */ 169 static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id) 170 { 171 struct clock_event_device *evt = dev_id; 172 173 /* clear the interrupt */ 174 writel(1, common_clkevt->intclr); 175 176 evt->event_handler(evt); 177 178 return IRQ_HANDLED; 179 } 180 181 static inline void evt_timer_shutdown(struct clock_event_device *evt) 182 { 183 writel(0, common_clkevt->ctrl); 184 } 185 186 static int sp804_shutdown(struct clock_event_device *evt) 187 { 188 evt_timer_shutdown(evt); 189 return 0; 190 } 191 192 static int sp804_set_periodic(struct clock_event_device *evt) 193 { 194 unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE | 195 TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; 196 197 evt_timer_shutdown(evt); 198 writel(common_clkevt->reload, common_clkevt->load); 199 writel(ctrl, common_clkevt->ctrl); 200 return 0; 201 } 202 203 static int sp804_set_next_event(unsigned long next, 204 struct clock_event_device *evt) 205 { 206 unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE | 207 TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE; 208 209 writel(next, common_clkevt->load); 210 writel(ctrl, common_clkevt->ctrl); 211 212 return 0; 213 } 214 215 static struct clock_event_device sp804_clockevent = { 216 .features = CLOCK_EVT_FEAT_PERIODIC | 217 CLOCK_EVT_FEAT_ONESHOT | 218 CLOCK_EVT_FEAT_DYNIRQ, 219 .set_state_shutdown = sp804_shutdown, 220 .set_state_periodic = sp804_set_periodic, 221 .set_state_oneshot = sp804_shutdown, 222 .tick_resume = sp804_shutdown, 223 .set_next_event = sp804_set_next_event, 224 .rating = 300, 225 }; 226 227 static int __init sp804_clockevents_init(void __iomem *base, unsigned int irq, 228 struct clk *clk, const char *name) 229 { 230 struct clock_event_device *evt = &sp804_clockevent; 231 long rate; 232 233 rate = sp804_get_clock_rate(clk, name); 234 if (rate < 0) 235 return -EINVAL; 236 237 common_clkevt = sp804_clkevt_get(base); 238 common_clkevt->reload = DIV_ROUND_CLOSEST(rate, HZ); 239 evt->name = name; 240 evt->irq = irq; 241 evt->cpumask = cpu_possible_mask; 242 243 writel(0, common_clkevt->ctrl); 244 245 if (request_irq(irq, sp804_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, 246 "timer", &sp804_clockevent)) 247 pr_err("request_irq() failed\n"); 248 clockevents_config_and_register(evt, rate, 0xf, 0xffffffff); 249 250 return 0; 251 } 252 253 static void __init sp804_clkevt_init(struct sp804_timer *timer, void __iomem *base) 254 { 255 int i; 256 257 for (i = 0; i < NR_TIMERS; i++) { 258 void __iomem *timer_base; 259 struct sp804_clkevt *clkevt; 260 261 timer_base = base + timer->timer_base[i]; 262 clkevt = &sp804_clkevt[i]; 263 clkevt->base = timer_base; 264 clkevt->load = timer_base + timer->load; 265 clkevt->load_h = timer_base + timer->load_h; 266 clkevt->value = timer_base + timer->value; 267 clkevt->value_h = timer_base + timer->value_h; 268 clkevt->ctrl = timer_base + timer->ctrl; 269 clkevt->intclr = timer_base + timer->intclr; 270 clkevt->width = timer->width; 271 } 272 } 273 274 static int __init sp804_of_init(struct device_node *np, struct sp804_timer *timer) 275 { 276 static bool initialized = false; 277 void __iomem *base; 278 void __iomem *timer1_base; 279 void __iomem *timer2_base; 280 int irq, ret = -EINVAL; 281 u32 irq_num = 0; 282 struct clk *clk1, *clk2; 283 const char *name = of_get_property(np, "compatible", NULL); 284 285 if (initialized) { 286 pr_debug("%pOF: skipping further SP804 timer device\n", np); 287 return 0; 288 } 289 290 base = of_iomap(np, 0); 291 if (!base) 292 return -ENXIO; 293 294 timer1_base = base + timer->timer_base[0]; 295 timer2_base = base + timer->timer_base[1]; 296 297 /* Ensure timers are disabled */ 298 writel(0, timer1_base + timer->ctrl); 299 writel(0, timer2_base + timer->ctrl); 300 301 clk1 = of_clk_get(np, 0); 302 if (IS_ERR(clk1)) 303 clk1 = NULL; 304 305 /* Get the 2nd clock if the timer has 3 timer clocks */ 306 if (of_clk_get_parent_count(np) == 3) { 307 clk2 = of_clk_get(np, 1); 308 if (IS_ERR(clk2)) { 309 pr_err("%pOFn clock not found: %d\n", np, 310 (int)PTR_ERR(clk2)); 311 clk2 = NULL; 312 } 313 } else 314 clk2 = clk1; 315 316 irq = irq_of_parse_and_map(np, 0); 317 if (irq <= 0) 318 goto err; 319 320 sp804_clkevt_init(timer, base); 321 322 of_property_read_u32(np, "arm,sp804-has-irq", &irq_num); 323 if (irq_num == 2) { 324 325 ret = sp804_clockevents_init(timer2_base, irq, clk2, name); 326 if (ret) 327 goto err; 328 329 ret = sp804_clocksource_and_sched_clock_init(timer1_base, 330 name, clk1, 1); 331 if (ret) 332 goto err; 333 } else { 334 335 ret = sp804_clockevents_init(timer1_base, irq, clk1, name); 336 if (ret) 337 goto err; 338 339 ret = sp804_clocksource_and_sched_clock_init(timer2_base, 340 name, clk2, 1); 341 if (ret) 342 goto err; 343 } 344 345 initialized = true; 346 347 return 0; 348 err: 349 iounmap(base); 350 return ret; 351 } 352 353 static int __init arm_sp804_of_init(struct device_node *np) 354 { 355 return sp804_of_init(np, &arm_sp804_timer); 356 } 357 TIMER_OF_DECLARE(sp804, "arm,sp804", arm_sp804_of_init); 358 359 static int __init hisi_sp804_of_init(struct device_node *np) 360 { 361 return sp804_of_init(np, &hisi_sp804_timer); 362 } 363 TIMER_OF_DECLARE(hisi_sp804, "hisilicon,sp804", hisi_sp804_of_init); 364 365 static int __init integrator_cp_of_init(struct device_node *np) 366 { 367 static int init_count = 0; 368 void __iomem *base; 369 int irq, ret = -EINVAL; 370 const char *name = of_get_property(np, "compatible", NULL); 371 struct clk *clk; 372 373 base = of_iomap(np, 0); 374 if (!base) { 375 pr_err("Failed to iomap\n"); 376 return -ENXIO; 377 } 378 379 clk = of_clk_get(np, 0); 380 if (IS_ERR(clk)) { 381 pr_err("Failed to get clock\n"); 382 return PTR_ERR(clk); 383 } 384 385 /* Ensure timer is disabled */ 386 writel(0, base + arm_sp804_timer.ctrl); 387 388 if (init_count == 2 || !of_device_is_available(np)) 389 goto err; 390 391 sp804_clkevt_init(&arm_sp804_timer, base); 392 393 if (!init_count) { 394 ret = sp804_clocksource_and_sched_clock_init(base, 395 name, clk, 0); 396 if (ret) 397 goto err; 398 } else { 399 irq = irq_of_parse_and_map(np, 0); 400 if (irq <= 0) 401 goto err; 402 403 ret = sp804_clockevents_init(base, irq, clk, name); 404 if (ret) 405 goto err; 406 } 407 408 init_count++; 409 return 0; 410 err: 411 iounmap(base); 412 return ret; 413 } 414 TIMER_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init); 415