1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 4 5 #include <linux/clk.h> 6 #include <linux/clockchips.h> 7 #include <linux/cpu.h> 8 #include <linux/cpuhotplug.h> 9 #include <linux/cpumask.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/jiffies.h> 13 #include <linux/printk.h> 14 #include <linux/sched_clock.h> 15 #include "timer-of.h" 16 17 #define RTTM_DATA 0x0 18 #define RTTM_CNT 0x4 19 #define RTTM_CTRL 0x8 20 #define RTTM_INT 0xc 21 22 #define RTTM_CTRL_ENABLE BIT(28) 23 #define RTTM_INT_PENDING BIT(16) 24 #define RTTM_INT_ENABLE BIT(20) 25 26 /* 27 * The Otto platform provides multiple 28 bit timers/counters with the following 28 * operating logic. If enabled the timer counts up. Per timer one can set a 29 * maximum counter value as an end marker. If end marker is reached the timer 30 * fires an interrupt. If the timer "overflows" by reaching the end marker or 31 * by adding 1 to 0x0fffffff the counter is reset to 0. When this happens and 32 * the timer is in operating mode COUNTER it stops. In mode TIMER it will 33 * continue to count up. 34 */ 35 #define RTTM_CTRL_COUNTER 0 36 #define RTTM_CTRL_TIMER BIT(24) 37 38 #define RTTM_BIT_COUNT 28 39 #define RTTM_MIN_DELTA 8 40 #define RTTM_MAX_DELTA CLOCKSOURCE_MASK(28) 41 #define RTTM_MAX_DIVISOR GENMASK(15, 0) 42 43 /* 44 * Timers are derived from the lexra bus (LXB) clock frequency. This is 175 MHz 45 * on RTL930x and 200 MHz on the other platforms. With 3.125 MHz choose a common 46 * divisor to have enough range and detail. This provides comparability between 47 * the different platforms. 48 */ 49 #define RTTM_TICKS_PER_SEC 3125000 50 51 struct rttm_cs { 52 struct timer_of to; 53 struct clocksource cs; 54 }; 55 56 /* Simple internal register functions */ 57 static inline unsigned int rttm_get_counter(void __iomem *base) 58 { 59 return ioread32(base + RTTM_CNT); 60 } 61 62 static inline void rttm_set_period(void __iomem *base, unsigned int period) 63 { 64 iowrite32(period, base + RTTM_DATA); 65 } 66 67 static inline void rttm_disable_timer(void __iomem *base) 68 { 69 iowrite32(0, base + RTTM_CTRL); 70 } 71 72 static inline void rttm_enable_timer(void __iomem *base, u32 mode, u32 divisor) 73 { 74 iowrite32(RTTM_CTRL_ENABLE | mode | divisor, base + RTTM_CTRL); 75 } 76 77 static inline void rttm_ack_irq(void __iomem *base) 78 { 79 iowrite32(ioread32(base + RTTM_INT) | RTTM_INT_PENDING, base + RTTM_INT); 80 } 81 82 static inline void rttm_enable_irq(void __iomem *base) 83 { 84 iowrite32(RTTM_INT_ENABLE, base + RTTM_INT); 85 } 86 87 static inline void rttm_disable_irq(void __iomem *base) 88 { 89 iowrite32(0, base + RTTM_INT); 90 } 91 92 /* Aggregated control functions for kernel clock framework */ 93 #define RTTM_DEBUG(base) \ 94 pr_debug("------------- %d %p\n", \ 95 smp_processor_id(), base) 96 97 static irqreturn_t rttm_timer_interrupt(int irq, void *dev_id) 98 { 99 struct clock_event_device *clkevt = dev_id; 100 struct timer_of *to = to_timer_of(clkevt); 101 102 rttm_ack_irq(to->of_base.base); 103 RTTM_DEBUG(to->of_base.base); 104 clkevt->event_handler(clkevt); 105 106 return IRQ_HANDLED; 107 } 108 109 static void rttm_bounce_timer(void __iomem *base, u32 mode) 110 { 111 /* 112 * When a running timer has less than ~5us left, a stop/start sequence 113 * might fail. While the details are unknown the most evident effect is 114 * that the subsequent interrupt will not be fired. 115 * 116 * As a workaround issue an intermediate restart with a very slow 117 * frequency of ~3kHz keeping the target counter (>=8). So the follow 118 * up restart will always be issued outside the critical window. 119 */ 120 121 rttm_disable_timer(base); 122 rttm_enable_timer(base, mode, RTTM_MAX_DIVISOR); 123 } 124 125 static void rttm_stop_timer(void __iomem *base) 126 { 127 rttm_disable_timer(base); 128 rttm_ack_irq(base); 129 } 130 131 static void rttm_start_timer(struct timer_of *to, u32 mode) 132 { 133 rttm_enable_timer(to->of_base.base, mode, to->of_clk.rate / RTTM_TICKS_PER_SEC); 134 } 135 136 static int rttm_next_event(unsigned long delta, struct clock_event_device *clkevt) 137 { 138 struct timer_of *to = to_timer_of(clkevt); 139 140 RTTM_DEBUG(to->of_base.base); 141 rttm_bounce_timer(to->of_base.base, RTTM_CTRL_COUNTER); 142 rttm_disable_timer(to->of_base.base); 143 rttm_set_period(to->of_base.base, delta); 144 rttm_start_timer(to, RTTM_CTRL_COUNTER); 145 146 return 0; 147 } 148 149 static int rttm_state_oneshot(struct clock_event_device *clkevt) 150 { 151 struct timer_of *to = to_timer_of(clkevt); 152 153 RTTM_DEBUG(to->of_base.base); 154 rttm_bounce_timer(to->of_base.base, RTTM_CTRL_COUNTER); 155 rttm_disable_timer(to->of_base.base); 156 rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ); 157 rttm_start_timer(to, RTTM_CTRL_COUNTER); 158 159 return 0; 160 } 161 162 static int rttm_state_periodic(struct clock_event_device *clkevt) 163 { 164 struct timer_of *to = to_timer_of(clkevt); 165 166 RTTM_DEBUG(to->of_base.base); 167 rttm_bounce_timer(to->of_base.base, RTTM_CTRL_TIMER); 168 rttm_disable_timer(to->of_base.base); 169 rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ); 170 rttm_start_timer(to, RTTM_CTRL_TIMER); 171 172 return 0; 173 } 174 175 static int rttm_state_shutdown(struct clock_event_device *clkevt) 176 { 177 struct timer_of *to = to_timer_of(clkevt); 178 179 RTTM_DEBUG(to->of_base.base); 180 rttm_stop_timer(to->of_base.base); 181 182 return 0; 183 } 184 185 static void rttm_setup_timer(void __iomem *base) 186 { 187 RTTM_DEBUG(base); 188 rttm_stop_timer(base); 189 rttm_set_period(base, 0); 190 } 191 192 static u64 rttm_read_clocksource(struct clocksource *cs) 193 { 194 struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs); 195 196 return rttm_get_counter(rcs->to.of_base.base); 197 } 198 199 /* Module initialization part. */ 200 static DEFINE_PER_CPU(struct timer_of, rttm_to) = { 201 .flags = TIMER_OF_BASE | TIMER_OF_CLOCK | TIMER_OF_IRQ, 202 .of_irq = { 203 .flags = IRQF_PERCPU | IRQF_TIMER, 204 .handler = rttm_timer_interrupt, 205 }, 206 .clkevt = { 207 .rating = 400, 208 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 209 .set_state_periodic = rttm_state_periodic, 210 .set_state_shutdown = rttm_state_shutdown, 211 .set_state_oneshot = rttm_state_oneshot, 212 .set_next_event = rttm_next_event 213 }, 214 }; 215 216 static int rttm_enable_clocksource(struct clocksource *cs) 217 { 218 struct rttm_cs *rcs = container_of(cs, struct rttm_cs, cs); 219 220 rttm_disable_irq(rcs->to.of_base.base); 221 rttm_setup_timer(rcs->to.of_base.base); 222 rttm_enable_timer(rcs->to.of_base.base, RTTM_CTRL_TIMER, 223 rcs->to.of_clk.rate / RTTM_TICKS_PER_SEC); 224 225 return 0; 226 } 227 228 struct rttm_cs rttm_cs = { 229 .to = { 230 .flags = TIMER_OF_BASE | TIMER_OF_CLOCK, 231 }, 232 .cs = { 233 .name = "realtek_otto_timer", 234 .rating = 400, 235 .mask = CLOCKSOURCE_MASK(RTTM_BIT_COUNT), 236 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 237 .read = rttm_read_clocksource, 238 } 239 }; 240 241 static u64 notrace rttm_read_clock(void) 242 { 243 return rttm_get_counter(rttm_cs.to.of_base.base); 244 } 245 246 static int rttm_cpu_starting(unsigned int cpu) 247 { 248 struct timer_of *to = per_cpu_ptr(&rttm_to, cpu); 249 250 RTTM_DEBUG(to->of_base.base); 251 to->clkevt.cpumask = cpumask_of(cpu); 252 irq_force_affinity(to->of_irq.irq, to->clkevt.cpumask); 253 clockevents_config_and_register(&to->clkevt, RTTM_TICKS_PER_SEC, 254 RTTM_MIN_DELTA, RTTM_MAX_DELTA); 255 rttm_enable_irq(to->of_base.base); 256 257 return 0; 258 } 259 260 static int __init rttm_probe(struct device_node *np) 261 { 262 unsigned int cpu, cpu_rollback; 263 struct timer_of *to; 264 unsigned int clkidx = num_possible_cpus(); 265 266 /* Use the first n timers as per CPU clock event generators */ 267 for_each_possible_cpu(cpu) { 268 to = per_cpu_ptr(&rttm_to, cpu); 269 to->of_irq.index = to->of_base.index = cpu; 270 if (timer_of_init(np, to)) { 271 pr_err("setup of timer %d failed\n", cpu); 272 goto rollback; 273 } 274 rttm_setup_timer(to->of_base.base); 275 } 276 277 /* Activate the n'th + 1 timer as a stable CPU clocksource. */ 278 to = &rttm_cs.to; 279 to->of_base.index = clkidx; 280 timer_of_init(np, to); 281 if (rttm_cs.to.of_base.base && rttm_cs.to.of_clk.rate) { 282 rttm_enable_clocksource(&rttm_cs.cs); 283 clocksource_register_hz(&rttm_cs.cs, RTTM_TICKS_PER_SEC); 284 sched_clock_register(rttm_read_clock, RTTM_BIT_COUNT, RTTM_TICKS_PER_SEC); 285 } else 286 pr_err(" setup of timer %d as clocksource failed", clkidx); 287 288 return cpuhp_setup_state(CPUHP_AP_REALTEK_TIMER_STARTING, 289 "timer/realtek:online", 290 rttm_cpu_starting, NULL); 291 rollback: 292 pr_err("timer registration failed\n"); 293 for_each_possible_cpu(cpu_rollback) { 294 if (cpu_rollback == cpu) 295 break; 296 to = per_cpu_ptr(&rttm_to, cpu_rollback); 297 timer_of_cleanup(to); 298 } 299 300 return -EINVAL; 301 } 302 303 TIMER_OF_DECLARE(otto_timer, "realtek,otto-timer", rttm_probe); 304