1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MStar timer driver 4 * 5 * Copyright (C) 2021 Daniel Palmer 6 * Copyright (C) 2021 Romain Perier 7 * 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clockchips.h> 12 #include <linux/interrupt.h> 13 #include <linux/irq.h> 14 #include <linux/irqreturn.h> 15 #include <linux/sched_clock.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_irq.h> 19 20 #ifdef CONFIG_ARM 21 #include <linux/delay.h> 22 #endif 23 24 #include "timer-of.h" 25 26 #define TIMER_NAME "msc313e_timer" 27 28 #define MSC313E_REG_CTRL 0x00 29 #define MSC313E_REG_CTRL_TIMER_EN BIT(0) 30 #define MSC313E_REG_CTRL_TIMER_TRIG BIT(1) 31 #define MSC313E_REG_CTRL_TIMER_INT_EN BIT(8) 32 #define MSC313E_REG_TIMER_MAX_LOW 0x08 33 #define MSC313E_REG_TIMER_MAX_HIGH 0x0c 34 #define MSC313E_REG_COUNTER_LOW 0x10 35 #define MSC313E_REG_COUNTER_HIGH 0x14 36 #define MSC313E_REG_TIMER_DIVIDE 0x18 37 38 #define MSC313E_CLK_DIVIDER 9 39 #define TIMER_SYNC_TICKS 3 40 41 #ifdef CONFIG_ARM 42 struct msc313e_delay { 43 void __iomem *base; 44 struct delay_timer delay; 45 }; 46 static struct msc313e_delay msc313e_delay; 47 #endif 48 49 static void __iomem *msc313e_clksrc; 50 51 static void msc313e_timer_stop(void __iomem *base) 52 { 53 writew(0, base + MSC313E_REG_CTRL); 54 } 55 56 static void msc313e_timer_start(void __iomem *base, bool periodic) 57 { 58 u16 reg; 59 60 reg = readw(base + MSC313E_REG_CTRL); 61 if (periodic) 62 reg |= MSC313E_REG_CTRL_TIMER_EN; 63 else 64 reg |= MSC313E_REG_CTRL_TIMER_TRIG; 65 writew(reg | MSC313E_REG_CTRL_TIMER_INT_EN, base + MSC313E_REG_CTRL); 66 } 67 68 static void msc313e_timer_setup(void __iomem *base, unsigned long delay) 69 { 70 unsigned long flags; 71 72 local_irq_save(flags); 73 writew(delay >> 16, base + MSC313E_REG_TIMER_MAX_HIGH); 74 writew(delay & 0xffff, base + MSC313E_REG_TIMER_MAX_LOW); 75 local_irq_restore(flags); 76 } 77 78 static unsigned long msc313e_timer_current_value(void __iomem *base) 79 { 80 unsigned long flags; 81 u16 l, h; 82 83 local_irq_save(flags); 84 l = readw(base + MSC313E_REG_COUNTER_LOW); 85 h = readw(base + MSC313E_REG_COUNTER_HIGH); 86 local_irq_restore(flags); 87 88 return (((u32)h) << 16 | l); 89 } 90 91 static int msc313e_timer_clkevt_shutdown(struct clock_event_device *evt) 92 { 93 struct timer_of *timer = to_timer_of(evt); 94 95 msc313e_timer_stop(timer_of_base(timer)); 96 97 return 0; 98 } 99 100 static int msc313e_timer_clkevt_set_oneshot(struct clock_event_device *evt) 101 { 102 struct timer_of *timer = to_timer_of(evt); 103 104 msc313e_timer_stop(timer_of_base(timer)); 105 msc313e_timer_start(timer_of_base(timer), false); 106 107 return 0; 108 } 109 110 static int msc313e_timer_clkevt_set_periodic(struct clock_event_device *evt) 111 { 112 struct timer_of *timer = to_timer_of(evt); 113 114 msc313e_timer_stop(timer_of_base(timer)); 115 msc313e_timer_setup(timer_of_base(timer), timer_of_period(timer)); 116 msc313e_timer_start(timer_of_base(timer), true); 117 118 return 0; 119 } 120 121 static int msc313e_timer_clkevt_next_event(unsigned long evt, struct clock_event_device *clkevt) 122 { 123 struct timer_of *timer = to_timer_of(clkevt); 124 125 msc313e_timer_stop(timer_of_base(timer)); 126 msc313e_timer_setup(timer_of_base(timer), evt); 127 msc313e_timer_start(timer_of_base(timer), false); 128 129 return 0; 130 } 131 132 static irqreturn_t msc313e_timer_clkevt_irq(int irq, void *dev_id) 133 { 134 struct clock_event_device *evt = dev_id; 135 136 evt->event_handler(evt); 137 138 return IRQ_HANDLED; 139 } 140 141 static u64 msc313e_timer_clksrc_read(struct clocksource *cs) 142 { 143 return msc313e_timer_current_value(msc313e_clksrc) & cs->mask; 144 } 145 146 #ifdef CONFIG_ARM 147 static unsigned long msc313e_read_delay_timer_read(void) 148 { 149 return msc313e_timer_current_value(msc313e_delay.base); 150 } 151 #endif 152 153 static u64 msc313e_timer_sched_clock_read(void) 154 { 155 return msc313e_timer_current_value(msc313e_clksrc); 156 } 157 158 static struct clock_event_device msc313e_clkevt = { 159 .name = TIMER_NAME, 160 .rating = 300, 161 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 162 .set_state_shutdown = msc313e_timer_clkevt_shutdown, 163 .set_state_periodic = msc313e_timer_clkevt_set_periodic, 164 .set_state_oneshot = msc313e_timer_clkevt_set_oneshot, 165 .tick_resume = msc313e_timer_clkevt_shutdown, 166 .set_next_event = msc313e_timer_clkevt_next_event, 167 }; 168 169 static int __init msc313e_clkevt_init(struct device_node *np) 170 { 171 int ret; 172 struct timer_of *to; 173 174 to = kzalloc(sizeof(*to), GFP_KERNEL); 175 if (!to) 176 return -ENOMEM; 177 178 to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; 179 to->of_irq.handler = msc313e_timer_clkevt_irq; 180 ret = timer_of_init(np, to); 181 if (ret) 182 return ret; 183 184 if (of_device_is_compatible(np, "sstar,ssd20xd-timer")) { 185 to->of_clk.rate = clk_get_rate(to->of_clk.clk) / MSC313E_CLK_DIVIDER; 186 to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); 187 writew(MSC313E_CLK_DIVIDER - 1, timer_of_base(to) + MSC313E_REG_TIMER_DIVIDE); 188 } 189 190 msc313e_clkevt.cpumask = cpu_possible_mask; 191 msc313e_clkevt.irq = to->of_irq.irq; 192 to->clkevt = msc313e_clkevt; 193 194 clockevents_config_and_register(&to->clkevt, timer_of_rate(to), 195 TIMER_SYNC_TICKS, 0xffffffff); 196 return 0; 197 } 198 199 static int __init msc313e_clksrc_init(struct device_node *np) 200 { 201 struct timer_of to = { 0 }; 202 int ret; 203 u16 reg; 204 205 to.flags = TIMER_OF_BASE | TIMER_OF_CLOCK; 206 ret = timer_of_init(np, &to); 207 if (ret) 208 return ret; 209 210 msc313e_clksrc = timer_of_base(&to); 211 reg = readw(msc313e_clksrc + MSC313E_REG_CTRL); 212 reg |= MSC313E_REG_CTRL_TIMER_EN; 213 writew(reg, msc313e_clksrc + MSC313E_REG_CTRL); 214 215 #ifdef CONFIG_ARM 216 msc313e_delay.base = timer_of_base(&to); 217 msc313e_delay.delay.read_current_timer = msc313e_read_delay_timer_read; 218 msc313e_delay.delay.freq = timer_of_rate(&to); 219 220 register_current_timer_delay(&msc313e_delay.delay); 221 #endif 222 223 sched_clock_register(msc313e_timer_sched_clock_read, 32, timer_of_rate(&to)); 224 return clocksource_mmio_init(timer_of_base(&to), TIMER_NAME, timer_of_rate(&to), 300, 32, 225 msc313e_timer_clksrc_read); 226 } 227 228 static int __init msc313e_timer_init(struct device_node *np) 229 { 230 int ret = 0; 231 static int num_called; 232 233 switch (num_called) { 234 case 0: 235 ret = msc313e_clksrc_init(np); 236 if (ret) 237 return ret; 238 break; 239 240 default: 241 ret = msc313e_clkevt_init(np); 242 if (ret) 243 return ret; 244 break; 245 } 246 247 num_called++; 248 249 return 0; 250 } 251 252 TIMER_OF_DECLARE(msc313, "mstar,msc313e-timer", msc313e_timer_init); 253 TIMER_OF_DECLARE(ssd20xd, "sstar,ssd20xd-timer", msc313e_timer_init); 254