1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 64-bit Periodic Interval Timer driver 4 * 5 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Claudiu Beznea <claudiu.beznea@microchip.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clockchips.h> 12 #include <linux/delay.h> 13 #include <linux/interrupt.h> 14 #include <linux/of_address.h> 15 #include <linux/of_irq.h> 16 #include <linux/sched_clock.h> 17 #include <linux/slab.h> 18 19 #define MCHP_PIT64B_CR 0x00 /* Control Register */ 20 #define MCHP_PIT64B_CR_START BIT(0) 21 #define MCHP_PIT64B_CR_SWRST BIT(8) 22 23 #define MCHP_PIT64B_MR 0x04 /* Mode Register */ 24 #define MCHP_PIT64B_MR_CONT BIT(0) 25 #define MCHP_PIT64B_MR_ONE_SHOT (0) 26 #define MCHP_PIT64B_MR_SGCLK BIT(3) 27 #define MCHP_PIT64B_MR_PRES GENMASK(11, 8) 28 29 #define MCHP_PIT64B_LSB_PR 0x08 /* LSB Period Register */ 30 31 #define MCHP_PIT64B_MSB_PR 0x0C /* MSB Period Register */ 32 33 #define MCHP_PIT64B_IER 0x10 /* Interrupt Enable Register */ 34 #define MCHP_PIT64B_IER_PERIOD BIT(0) 35 36 #define MCHP_PIT64B_ISR 0x1C /* Interrupt Status Register */ 37 38 #define MCHP_PIT64B_TLSBR 0x20 /* Timer LSB Register */ 39 40 #define MCHP_PIT64B_TMSBR 0x24 /* Timer MSB Register */ 41 42 #define MCHP_PIT64B_PRES_MAX 0x10 43 #define MCHP_PIT64B_LSBMASK GENMASK_ULL(31, 0) 44 #define MCHP_PIT64B_PRES_TO_MODE(p) (MCHP_PIT64B_MR_PRES & ((p) << 8)) 45 #define MCHP_PIT64B_MODE_TO_PRES(m) ((MCHP_PIT64B_MR_PRES & (m)) >> 8) 46 #define MCHP_PIT64B_DEF_FREQ 5000000UL /* 5 MHz */ 47 48 #define MCHP_PIT64B_NAME "pit64b" 49 50 /** 51 * struct mchp_pit64b_timer - PIT64B timer data structure 52 * @base: base address of PIT64B hardware block 53 * @pclk: PIT64B's peripheral clock 54 * @gclk: PIT64B's generic clock 55 * @mode: precomputed value for mode register 56 */ 57 struct mchp_pit64b_timer { 58 void __iomem *base; 59 struct clk *pclk; 60 struct clk *gclk; 61 u32 mode; 62 }; 63 64 /** 65 * struct mchp_pit64b_clkevt - PIT64B clockevent data structure 66 * @timer: PIT64B timer 67 * @clkevt: clockevent 68 */ 69 struct mchp_pit64b_clkevt { 70 struct mchp_pit64b_timer timer; 71 struct clock_event_device clkevt; 72 }; 73 74 #define clkevt_to_mchp_pit64b_timer(x) \ 75 ((struct mchp_pit64b_timer *)container_of(x,\ 76 struct mchp_pit64b_clkevt, clkevt)) 77 78 /** 79 * struct mchp_pit64b_clksrc - PIT64B clocksource data structure 80 * @timer: PIT64B timer 81 * @clksrc: clocksource 82 */ 83 struct mchp_pit64b_clksrc { 84 struct mchp_pit64b_timer timer; 85 struct clocksource clksrc; 86 }; 87 88 #define clksrc_to_mchp_pit64b_timer(x) \ 89 ((struct mchp_pit64b_timer *)container_of(x,\ 90 struct mchp_pit64b_clksrc, clksrc)) 91 92 /* Base address for clocksource timer. */ 93 static void __iomem *mchp_pit64b_cs_base; 94 /* Default cycles for clockevent timer. */ 95 static u64 mchp_pit64b_ce_cycles; 96 /* Delay timer. */ 97 static struct delay_timer mchp_pit64b_dt; 98 99 static inline u64 mchp_pit64b_cnt_read(void __iomem *base) 100 { 101 unsigned long flags; 102 u32 low, high; 103 104 raw_local_irq_save(flags); 105 106 /* 107 * When using a 64 bit period TLSB must be read first, followed by the 108 * read of TMSB. This sequence generates an atomic read of the 64 bit 109 * timer value whatever the lapse of time between the accesses. 110 */ 111 low = readl_relaxed(base + MCHP_PIT64B_TLSBR); 112 high = readl_relaxed(base + MCHP_PIT64B_TMSBR); 113 114 raw_local_irq_restore(flags); 115 116 return (((u64)high << 32) | low); 117 } 118 119 static inline void mchp_pit64b_reset(struct mchp_pit64b_timer *timer, 120 u64 cycles, u32 mode, u32 irqs) 121 { 122 u32 low, high; 123 124 low = cycles & MCHP_PIT64B_LSBMASK; 125 high = cycles >> 32; 126 127 writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); 128 writel_relaxed(mode | timer->mode, timer->base + MCHP_PIT64B_MR); 129 writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR); 130 writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR); 131 writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER); 132 writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR); 133 } 134 135 static void mchp_pit64b_suspend(struct mchp_pit64b_timer *timer) 136 { 137 writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR); 138 if (timer->mode & MCHP_PIT64B_MR_SGCLK) 139 clk_disable_unprepare(timer->gclk); 140 clk_disable_unprepare(timer->pclk); 141 } 142 143 static void mchp_pit64b_resume(struct mchp_pit64b_timer *timer) 144 { 145 clk_prepare_enable(timer->pclk); 146 if (timer->mode & MCHP_PIT64B_MR_SGCLK) 147 clk_prepare_enable(timer->gclk); 148 } 149 150 static void mchp_pit64b_clksrc_suspend(struct clocksource *cs) 151 { 152 struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs); 153 154 mchp_pit64b_suspend(timer); 155 } 156 157 static void mchp_pit64b_clksrc_resume(struct clocksource *cs) 158 { 159 struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs); 160 161 mchp_pit64b_resume(timer); 162 mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0); 163 } 164 165 static u64 mchp_pit64b_clksrc_read(struct clocksource *cs) 166 { 167 return mchp_pit64b_cnt_read(mchp_pit64b_cs_base); 168 } 169 170 static u64 notrace mchp_pit64b_sched_read_clk(void) 171 { 172 return mchp_pit64b_cnt_read(mchp_pit64b_cs_base); 173 } 174 175 static unsigned long notrace mchp_pit64b_dt_read(void) 176 { 177 return mchp_pit64b_cnt_read(mchp_pit64b_cs_base); 178 } 179 180 static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev) 181 { 182 struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); 183 184 if (!clockevent_state_detached(cedev)) 185 mchp_pit64b_suspend(timer); 186 187 return 0; 188 } 189 190 static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev) 191 { 192 struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); 193 194 if (clockevent_state_shutdown(cedev)) 195 mchp_pit64b_resume(timer); 196 197 mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT, 198 MCHP_PIT64B_IER_PERIOD); 199 200 return 0; 201 } 202 203 static int mchp_pit64b_clkevt_set_oneshot(struct clock_event_device *cedev) 204 { 205 struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); 206 207 if (clockevent_state_shutdown(cedev)) 208 mchp_pit64b_resume(timer); 209 210 mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_ONE_SHOT, 211 MCHP_PIT64B_IER_PERIOD); 212 213 return 0; 214 } 215 216 static int mchp_pit64b_clkevt_set_next_event(unsigned long evt, 217 struct clock_event_device *cedev) 218 { 219 struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev); 220 221 mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT, 222 MCHP_PIT64B_IER_PERIOD); 223 224 return 0; 225 } 226 227 static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id) 228 { 229 struct mchp_pit64b_clkevt *irq_data = dev_id; 230 231 /* Need to clear the interrupt. */ 232 readl_relaxed(irq_data->timer.base + MCHP_PIT64B_ISR); 233 234 irq_data->clkevt.event_handler(&irq_data->clkevt); 235 236 return IRQ_HANDLED; 237 } 238 239 static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate, 240 u32 max_rate) 241 { 242 u32 tmp; 243 244 for (*pres = 0; *pres < MCHP_PIT64B_PRES_MAX; (*pres)++) { 245 tmp = clk_rate / (*pres + 1); 246 if (tmp <= max_rate) 247 break; 248 } 249 250 /* Use the biggest prescaler if we didn't match one. */ 251 if (*pres == MCHP_PIT64B_PRES_MAX) 252 *pres = MCHP_PIT64B_PRES_MAX - 1; 253 } 254 255 /** 256 * mchp_pit64b_init_mode() - prepare PIT64B mode register value to be used at 257 * runtime; this includes prescaler and SGCLK bit 258 * @timer: pointer to pit64b timer to init 259 * @max_rate: maximum rate that timer's clock could use 260 * 261 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to 262 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate 263 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be 264 * divided by the internal PIT64B's divider. 265 * 266 * This function, first tries to use GCLK by requesting the desired rate from 267 * PMC and then using the internal PIT64B prescaler, if any, to reach the 268 * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware) 269 * then the function falls back on using PCLK as clock source for PIT64B timer 270 * choosing the highest prescaler in case it doesn't locate one to match the 271 * requested frequency. 272 * 273 * Below is presented the PIT64B block in relation with PMC: 274 * 275 * PIT64B 276 * PMC +------------------------------------+ 277 * +----+ | +-----+ | 278 * | |-->gclk -->|-->| | +---------+ +-----+ | 279 * | | | | MUX |--->| Divider |->|timer| | 280 * | |-->pclk -->|-->| | +---------+ +-----+ | 281 * +----+ | +-----+ | 282 * | ^ | 283 * | sel | 284 * +------------------------------------+ 285 * 286 * Where: 287 * - gclk rate <= pclk rate/3 288 * - gclk rate could be requested from PMC 289 * - pclk rate is fixed (cannot be requested from PMC) 290 */ 291 static int __init mchp_pit64b_init_mode(struct mchp_pit64b_timer *timer, 292 unsigned long max_rate) 293 { 294 unsigned long pclk_rate, diff = 0, best_diff = ULONG_MAX; 295 long gclk_round = 0; 296 u32 pres, best_pres = 0; 297 298 pclk_rate = clk_get_rate(timer->pclk); 299 if (!pclk_rate) 300 return -EINVAL; 301 302 timer->mode = 0; 303 304 /* Try using GCLK. */ 305 gclk_round = clk_round_rate(timer->gclk, max_rate); 306 if (gclk_round < 0) 307 goto pclk; 308 309 if (pclk_rate / gclk_round < 3) 310 goto pclk; 311 312 mchp_pit64b_pres_compute(&pres, gclk_round, max_rate); 313 best_diff = abs(gclk_round / (pres + 1) - max_rate); 314 best_pres = pres; 315 316 if (!best_diff) { 317 timer->mode |= MCHP_PIT64B_MR_SGCLK; 318 clk_set_rate(timer->gclk, gclk_round); 319 goto done; 320 } 321 322 pclk: 323 /* Check if requested rate could be obtained using PCLK. */ 324 mchp_pit64b_pres_compute(&pres, pclk_rate, max_rate); 325 diff = abs(pclk_rate / (pres + 1) - max_rate); 326 327 if (best_diff > diff) { 328 /* Use PCLK. */ 329 best_pres = pres; 330 } else { 331 /* Use GCLK. */ 332 timer->mode |= MCHP_PIT64B_MR_SGCLK; 333 clk_set_rate(timer->gclk, gclk_round); 334 } 335 336 done: 337 timer->mode |= MCHP_PIT64B_PRES_TO_MODE(best_pres); 338 339 pr_info("PIT64B: using clk=%s with prescaler %u, freq=%lu [Hz]\n", 340 timer->mode & MCHP_PIT64B_MR_SGCLK ? "gclk" : "pclk", best_pres, 341 timer->mode & MCHP_PIT64B_MR_SGCLK ? 342 gclk_round / (best_pres + 1) : pclk_rate / (best_pres + 1)); 343 344 return 0; 345 } 346 347 static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer, 348 u32 clk_rate) 349 { 350 struct mchp_pit64b_clksrc *cs; 351 int ret; 352 353 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 354 if (!cs) 355 return -ENOMEM; 356 357 mchp_pit64b_resume(timer); 358 mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0); 359 360 mchp_pit64b_cs_base = timer->base; 361 362 cs->timer.base = timer->base; 363 cs->timer.pclk = timer->pclk; 364 cs->timer.gclk = timer->gclk; 365 cs->timer.mode = timer->mode; 366 cs->clksrc.name = MCHP_PIT64B_NAME; 367 cs->clksrc.mask = CLOCKSOURCE_MASK(64); 368 cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; 369 cs->clksrc.rating = 210; 370 cs->clksrc.read = mchp_pit64b_clksrc_read; 371 cs->clksrc.suspend = mchp_pit64b_clksrc_suspend; 372 cs->clksrc.resume = mchp_pit64b_clksrc_resume; 373 374 ret = clocksource_register_hz(&cs->clksrc, clk_rate); 375 if (ret) { 376 pr_debug("clksrc: Failed to register PIT64B clocksource!\n"); 377 378 /* Stop timer. */ 379 mchp_pit64b_suspend(timer); 380 kfree(cs); 381 382 return ret; 383 } 384 385 sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate); 386 387 mchp_pit64b_dt.read_current_timer = mchp_pit64b_dt_read; 388 mchp_pit64b_dt.freq = clk_rate; 389 register_current_timer_delay(&mchp_pit64b_dt); 390 391 return 0; 392 } 393 394 static int __init mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer, 395 u32 clk_rate, u32 irq) 396 { 397 struct mchp_pit64b_clkevt *ce; 398 int ret; 399 400 ce = kzalloc(sizeof(*ce), GFP_KERNEL); 401 if (!ce) 402 return -ENOMEM; 403 404 mchp_pit64b_ce_cycles = DIV_ROUND_CLOSEST(clk_rate, HZ); 405 406 ce->timer.base = timer->base; 407 ce->timer.pclk = timer->pclk; 408 ce->timer.gclk = timer->gclk; 409 ce->timer.mode = timer->mode; 410 ce->clkevt.name = MCHP_PIT64B_NAME; 411 ce->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC; 412 ce->clkevt.rating = 150; 413 ce->clkevt.set_state_shutdown = mchp_pit64b_clkevt_shutdown; 414 ce->clkevt.set_state_periodic = mchp_pit64b_clkevt_set_periodic; 415 ce->clkevt.set_state_oneshot = mchp_pit64b_clkevt_set_oneshot; 416 ce->clkevt.set_next_event = mchp_pit64b_clkevt_set_next_event; 417 ce->clkevt.cpumask = cpumask_of(0); 418 ce->clkevt.irq = irq; 419 420 ret = request_irq(irq, mchp_pit64b_interrupt, IRQF_TIMER, 421 "pit64b_tick", ce); 422 if (ret) { 423 pr_debug("clkevt: Failed to setup PIT64B IRQ\n"); 424 kfree(ce); 425 return ret; 426 } 427 428 clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX); 429 430 return 0; 431 } 432 433 static int __init mchp_pit64b_dt_init_timer(struct device_node *node, 434 bool clkevt) 435 { 436 struct mchp_pit64b_timer timer; 437 unsigned long clk_rate; 438 u32 irq = 0; 439 int ret; 440 441 /* Parse DT node. */ 442 timer.pclk = of_clk_get_by_name(node, "pclk"); 443 if (IS_ERR(timer.pclk)) 444 return PTR_ERR(timer.pclk); 445 446 timer.gclk = of_clk_get_by_name(node, "gclk"); 447 if (IS_ERR(timer.gclk)) 448 return PTR_ERR(timer.gclk); 449 450 timer.base = of_iomap(node, 0); 451 if (!timer.base) 452 return -ENXIO; 453 454 if (clkevt) { 455 irq = irq_of_parse_and_map(node, 0); 456 if (!irq) { 457 ret = -ENODEV; 458 goto io_unmap; 459 } 460 } 461 462 /* Initialize mode (prescaler + SGCK bit). To be used at runtime. */ 463 ret = mchp_pit64b_init_mode(&timer, MCHP_PIT64B_DEF_FREQ); 464 if (ret) 465 goto irq_unmap; 466 467 if (timer.mode & MCHP_PIT64B_MR_SGCLK) 468 clk_rate = clk_get_rate(timer.gclk); 469 else 470 clk_rate = clk_get_rate(timer.pclk); 471 clk_rate = clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1); 472 473 if (clkevt) 474 ret = mchp_pit64b_init_clkevt(&timer, clk_rate, irq); 475 else 476 ret = mchp_pit64b_init_clksrc(&timer, clk_rate); 477 478 if (ret) 479 goto irq_unmap; 480 481 return 0; 482 483 irq_unmap: 484 irq_dispose_mapping(irq); 485 io_unmap: 486 iounmap(timer.base); 487 488 return ret; 489 } 490 491 static int __init mchp_pit64b_dt_init(struct device_node *node) 492 { 493 static int inits; 494 495 switch (inits++) { 496 case 0: 497 /* 1st request, register clockevent. */ 498 return mchp_pit64b_dt_init_timer(node, true); 499 case 1: 500 /* 2nd request, register clocksource. */ 501 return mchp_pit64b_dt_init_timer(node, false); 502 } 503 504 /* The rest, don't care. */ 505 return -EINVAL; 506 } 507 508 TIMER_OF_DECLARE(mchp_pit64b, "microchip,sam9x60-pit64b", mchp_pit64b_dt_init); 509