1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Mediatek SoCs General-Purpose Timer handling. 4 * 5 * Copyright (C) 2014 Matthias Brugger 6 * 7 * Matthias Brugger <matthias.bgg@gmail.com> 8 */ 9 10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 11 12 #include <linux/clk.h> 13 #include <linux/clockchips.h> 14 #include <linux/clocksource.h> 15 #include <linux/interrupt.h> 16 #include <linux/irqreturn.h> 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/platform_device.h> 20 #include <linux/sched_clock.h> 21 #include <linux/slab.h> 22 #include "timer-of.h" 23 24 #define TIMER_CLK_EVT (1) 25 #define TIMER_CLK_SRC (2) 26 27 #define TIMER_SYNC_TICKS (3) 28 29 /* gpt */ 30 #define GPT_IRQ_EN_REG 0x00 31 #define GPT_IRQ_ENABLE(val) BIT((val) - 1) 32 #define GPT_IRQ_ACK_REG 0x08 33 #define GPT_IRQ_ACK(val) BIT((val) - 1) 34 35 #define GPT_CTRL_REG(val) (0x10 * (val)) 36 #define GPT_CTRL_OP(val) (((val) & 0x3) << 4) 37 #define GPT_CTRL_OP_ONESHOT (0) 38 #define GPT_CTRL_OP_REPEAT (1) 39 #define GPT_CTRL_OP_FREERUN (3) 40 #define GPT_CTRL_CLEAR (2) 41 #define GPT_CTRL_ENABLE (1) 42 #define GPT_CTRL_DISABLE (0) 43 44 #define GPT_CLK_REG(val) (0x04 + (0x10 * (val))) 45 #define GPT_CLK_SRC(val) (((val) & 0x1) << 4) 46 #define GPT_CLK_SRC_SYS13M (0) 47 #define GPT_CLK_SRC_RTC32K (1) 48 #define GPT_CLK_DIV1 (0x0) 49 #define GPT_CLK_DIV2 (0x1) 50 51 #define GPT_CNT_REG(val) (0x08 + (0x10 * (val))) 52 #define GPT_CMP_REG(val) (0x0C + (0x10 * (val))) 53 54 /* system timer */ 55 #define SYST_BASE (0x40) 56 57 #define SYST_CON (SYST_BASE + 0x0) 58 #define SYST_VAL (SYST_BASE + 0x4) 59 60 #define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON) 61 #define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL) 62 63 /* 64 * SYST_CON_EN: Clock enable. Shall be set to 65 * - Start timer countdown. 66 * - Allow timeout ticks being updated. 67 * - Allow changing interrupt status,like clear irq pending. 68 * 69 * SYST_CON_IRQ_EN: Set to enable interrupt. 70 * 71 * SYST_CON_IRQ_CLR: Set to clear interrupt. 72 */ 73 #define SYST_CON_EN BIT(0) 74 #define SYST_CON_IRQ_EN BIT(1) 75 #define SYST_CON_IRQ_CLR BIT(4) 76 77 static void __iomem *gpt_sched_reg __read_mostly; 78 79 static void mtk_syst_ack_irq(struct timer_of *to) 80 { 81 /* Clear and disable interrupt */ 82 writel(SYST_CON_EN, SYST_CON_REG(to)); 83 writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to)); 84 } 85 86 static irqreturn_t mtk_syst_handler(int irq, void *dev_id) 87 { 88 struct clock_event_device *clkevt = dev_id; 89 struct timer_of *to = to_timer_of(clkevt); 90 91 mtk_syst_ack_irq(to); 92 clkevt->event_handler(clkevt); 93 94 return IRQ_HANDLED; 95 } 96 97 static int mtk_syst_clkevt_next_event(unsigned long ticks, 98 struct clock_event_device *clkevt) 99 { 100 struct timer_of *to = to_timer_of(clkevt); 101 102 /* Enable clock to allow timeout tick update later */ 103 writel(SYST_CON_EN, SYST_CON_REG(to)); 104 105 /* 106 * Write new timeout ticks. Timer shall start countdown 107 * after timeout ticks are updated. 108 */ 109 writel(ticks, SYST_VAL_REG(to)); 110 111 /* Enable interrupt */ 112 writel(SYST_CON_EN | SYST_CON_IRQ_EN, SYST_CON_REG(to)); 113 114 return 0; 115 } 116 117 static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt) 118 { 119 /* Clear any irq */ 120 mtk_syst_ack_irq(to_timer_of(clkevt)); 121 122 /* Disable timer */ 123 writel(0, SYST_CON_REG(to_timer_of(clkevt))); 124 125 return 0; 126 } 127 128 static int mtk_syst_clkevt_resume(struct clock_event_device *clkevt) 129 { 130 return mtk_syst_clkevt_shutdown(clkevt); 131 } 132 133 static int mtk_syst_clkevt_oneshot(struct clock_event_device *clkevt) 134 { 135 return 0; 136 } 137 138 static u64 notrace mtk_gpt_read_sched_clock(void) 139 { 140 return readl_relaxed(gpt_sched_reg); 141 } 142 143 static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer) 144 { 145 u32 val; 146 147 val = readl(timer_of_base(to) + GPT_CTRL_REG(timer)); 148 writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) + 149 GPT_CTRL_REG(timer)); 150 } 151 152 static void mtk_gpt_clkevt_time_setup(struct timer_of *to, 153 unsigned long delay, u8 timer) 154 { 155 writel(delay, timer_of_base(to) + GPT_CMP_REG(timer)); 156 } 157 158 static void mtk_gpt_clkevt_time_start(struct timer_of *to, 159 bool periodic, u8 timer) 160 { 161 u32 val; 162 163 /* Acknowledge interrupt */ 164 writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG); 165 166 val = readl(timer_of_base(to) + GPT_CTRL_REG(timer)); 167 168 /* Clear 2 bit timer operation mode field */ 169 val &= ~GPT_CTRL_OP(0x3); 170 171 if (periodic) 172 val |= GPT_CTRL_OP(GPT_CTRL_OP_REPEAT); 173 else 174 val |= GPT_CTRL_OP(GPT_CTRL_OP_ONESHOT); 175 176 writel(val | GPT_CTRL_ENABLE | GPT_CTRL_CLEAR, 177 timer_of_base(to) + GPT_CTRL_REG(timer)); 178 } 179 180 static int mtk_gpt_clkevt_shutdown(struct clock_event_device *clk) 181 { 182 mtk_gpt_clkevt_time_stop(to_timer_of(clk), TIMER_CLK_EVT); 183 184 return 0; 185 } 186 187 static int mtk_gpt_clkevt_set_periodic(struct clock_event_device *clk) 188 { 189 struct timer_of *to = to_timer_of(clk); 190 191 mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT); 192 mtk_gpt_clkevt_time_setup(to, to->of_clk.period, TIMER_CLK_EVT); 193 mtk_gpt_clkevt_time_start(to, true, TIMER_CLK_EVT); 194 195 return 0; 196 } 197 198 static int mtk_gpt_clkevt_next_event(unsigned long event, 199 struct clock_event_device *clk) 200 { 201 struct timer_of *to = to_timer_of(clk); 202 203 mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT); 204 mtk_gpt_clkevt_time_setup(to, event, TIMER_CLK_EVT); 205 mtk_gpt_clkevt_time_start(to, false, TIMER_CLK_EVT); 206 207 return 0; 208 } 209 210 static irqreturn_t mtk_gpt_interrupt(int irq, void *dev_id) 211 { 212 struct clock_event_device *clkevt = (struct clock_event_device *)dev_id; 213 struct timer_of *to = to_timer_of(clkevt); 214 215 /* Acknowledge timer0 irq */ 216 writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG); 217 clkevt->event_handler(clkevt); 218 219 return IRQ_HANDLED; 220 } 221 222 static void mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option) 223 { 224 writel(GPT_CTRL_CLEAR | GPT_CTRL_DISABLE, 225 timer_of_base(to) + GPT_CTRL_REG(timer)); 226 227 writel(GPT_CLK_SRC(GPT_CLK_SRC_SYS13M) | GPT_CLK_DIV1, 228 timer_of_base(to) + GPT_CLK_REG(timer)); 229 230 writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer)); 231 232 writel(GPT_CTRL_OP(option) | GPT_CTRL_ENABLE, 233 timer_of_base(to) + GPT_CTRL_REG(timer)); 234 } 235 236 static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer) 237 { 238 u32 val; 239 240 /* Disable all interrupts */ 241 writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG); 242 243 /* Acknowledge all spurious pending interrupts */ 244 writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG); 245 246 val = readl(timer_of_base(to) + GPT_IRQ_EN_REG); 247 writel(val | GPT_IRQ_ENABLE(timer), 248 timer_of_base(to) + GPT_IRQ_EN_REG); 249 } 250 251 static void mtk_gpt_resume(struct clock_event_device *clk) 252 { 253 struct timer_of *to = to_timer_of(clk); 254 255 mtk_gpt_enable_irq(to, TIMER_CLK_EVT); 256 } 257 258 static void mtk_gpt_suspend(struct clock_event_device *clk) 259 { 260 struct timer_of *to = to_timer_of(clk); 261 262 /* Disable all interrupts */ 263 writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG); 264 265 /* 266 * This is called with interrupts disabled, 267 * so we need to ack any interrupt that is pending 268 * or for example ATF will prevent a suspend from completing. 269 */ 270 writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG); 271 } 272 273 static struct timer_of to = { 274 .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, 275 276 .clkevt = { 277 .name = "mtk-clkevt", 278 .rating = 300, 279 .cpumask = cpu_possible_mask, 280 }, 281 282 .of_irq = { 283 .flags = IRQF_TIMER | IRQF_IRQPOLL | IRQF_NO_AUTOEN, 284 }, 285 }; 286 287 static int mtk_syst_init(struct platform_device *pdev) 288 { 289 struct device_node *node = pdev->dev.of_node; 290 int ret; 291 292 to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT; 293 to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown; 294 to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot; 295 to.clkevt.tick_resume = mtk_syst_clkevt_resume; 296 to.clkevt.set_next_event = mtk_syst_clkevt_next_event; 297 to.of_irq.handler = mtk_syst_handler; 298 299 ret = timer_of_init(node, &to); 300 if (ret) 301 return ret; 302 303 clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 304 TIMER_SYNC_TICKS, 0xffffffff); 305 enable_irq(timer_of_irq(&to)); 306 307 return 0; 308 } 309 310 static int mtk_gpt_init(struct platform_device *pdev) 311 { 312 struct device_node *node = pdev->dev.of_node; 313 struct clk *clk_bus; 314 int ret; 315 316 clk_bus = devm_clk_get_optional_enabled(&pdev->dev, "bus"); 317 318 to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; 319 to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown; 320 to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic; 321 to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown; 322 to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown; 323 to.clkevt.set_next_event = mtk_gpt_clkevt_next_event; 324 to.clkevt.suspend = mtk_gpt_suspend; 325 to.clkevt.resume = mtk_gpt_resume; 326 to.of_irq.handler = mtk_gpt_interrupt; 327 328 ret = timer_of_init(node, &to); 329 if (ret) 330 return ret; 331 332 /* Configure clock source */ 333 mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN); 334 clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC), 335 node->name, timer_of_rate(&to), 300, 32, 336 clocksource_mmio_readl_up); 337 gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC); 338 sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to)); 339 340 /* Configure clock event */ 341 mtk_gpt_setup(&to, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT); 342 clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 343 TIMER_SYNC_TICKS, 0xffffffff); 344 345 mtk_gpt_enable_irq(&to, TIMER_CLK_EVT); 346 enable_irq(timer_of_irq(&to)); 347 348 return 0; 349 } 350 351 static int mtk_timer_probe(struct platform_device *pdev) 352 { 353 int (*timer_init)(struct platform_device *pdev); 354 355 timer_init = of_device_get_match_data(&pdev->dev); 356 return timer_init(pdev); 357 } 358 359 static const struct of_device_id mtk_timer_match_table[] = { 360 { .compatible = "mediatek,mt6577-timer", .data = mtk_gpt_init }, 361 { .compatible = "mediatek,mt6765-timer", .data = mtk_syst_init }, 362 { /* sentinel */ } 363 }; 364 365 static struct platform_driver mtk_timer_driver = { 366 .probe = mtk_timer_probe, 367 .driver = { 368 .name = "mediatek-timer", 369 .of_match_table = mtk_timer_match_table, 370 }, 371 }; 372 module_platform_driver(mtk_timer_driver); 373 374 MODULE_DESCRIPTION("MediaTek Timer driver"); 375