1 /* 2 * SuperH Timer Support - MTU2 3 * 4 * Copyright (C) 2009 Magnus Damm 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/spinlock.h> 23 #include <linux/interrupt.h> 24 #include <linux/ioport.h> 25 #include <linux/delay.h> 26 #include <linux/io.h> 27 #include <linux/clk.h> 28 #include <linux/irq.h> 29 #include <linux/err.h> 30 #include <linux/clockchips.h> 31 #include <linux/sh_timer.h> 32 #include <linux/slab.h> 33 #include <linux/module.h> 34 35 struct sh_mtu2_priv { 36 void __iomem *mapbase; 37 struct clk *clk; 38 struct irqaction irqaction; 39 struct platform_device *pdev; 40 unsigned long rate; 41 unsigned long periodic; 42 struct clock_event_device ced; 43 }; 44 45 static DEFINE_SPINLOCK(sh_mtu2_lock); 46 47 #define TSTR -1 /* shared register */ 48 #define TCR 0 /* channel register */ 49 #define TMDR 1 /* channel register */ 50 #define TIOR 2 /* channel register */ 51 #define TIER 3 /* channel register */ 52 #define TSR 4 /* channel register */ 53 #define TCNT 5 /* channel register */ 54 #define TGR 6 /* channel register */ 55 56 static unsigned long mtu2_reg_offs[] = { 57 [TCR] = 0, 58 [TMDR] = 1, 59 [TIOR] = 2, 60 [TIER] = 4, 61 [TSR] = 5, 62 [TCNT] = 6, 63 [TGR] = 8, 64 }; 65 66 static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr) 67 { 68 struct sh_timer_config *cfg = p->pdev->dev.platform_data; 69 void __iomem *base = p->mapbase; 70 unsigned long offs; 71 72 if (reg_nr == TSTR) 73 return ioread8(base + cfg->channel_offset); 74 75 offs = mtu2_reg_offs[reg_nr]; 76 77 if ((reg_nr == TCNT) || (reg_nr == TGR)) 78 return ioread16(base + offs); 79 else 80 return ioread8(base + offs); 81 } 82 83 static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr, 84 unsigned long value) 85 { 86 struct sh_timer_config *cfg = p->pdev->dev.platform_data; 87 void __iomem *base = p->mapbase; 88 unsigned long offs; 89 90 if (reg_nr == TSTR) { 91 iowrite8(value, base + cfg->channel_offset); 92 return; 93 } 94 95 offs = mtu2_reg_offs[reg_nr]; 96 97 if ((reg_nr == TCNT) || (reg_nr == TGR)) 98 iowrite16(value, base + offs); 99 else 100 iowrite8(value, base + offs); 101 } 102 103 static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start) 104 { 105 struct sh_timer_config *cfg = p->pdev->dev.platform_data; 106 unsigned long flags, value; 107 108 /* start stop register shared by multiple timer channels */ 109 spin_lock_irqsave(&sh_mtu2_lock, flags); 110 value = sh_mtu2_read(p, TSTR); 111 112 if (start) 113 value |= 1 << cfg->timer_bit; 114 else 115 value &= ~(1 << cfg->timer_bit); 116 117 sh_mtu2_write(p, TSTR, value); 118 spin_unlock_irqrestore(&sh_mtu2_lock, flags); 119 } 120 121 static int sh_mtu2_enable(struct sh_mtu2_priv *p) 122 { 123 int ret; 124 125 /* enable clock */ 126 ret = clk_enable(p->clk); 127 if (ret) { 128 dev_err(&p->pdev->dev, "cannot enable clock\n"); 129 return ret; 130 } 131 132 /* make sure channel is disabled */ 133 sh_mtu2_start_stop_ch(p, 0); 134 135 p->rate = clk_get_rate(p->clk) / 64; 136 p->periodic = (p->rate + HZ/2) / HZ; 137 138 /* "Periodic Counter Operation" */ 139 sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */ 140 sh_mtu2_write(p, TIOR, 0); 141 sh_mtu2_write(p, TGR, p->periodic); 142 sh_mtu2_write(p, TCNT, 0); 143 sh_mtu2_write(p, TMDR, 0); 144 sh_mtu2_write(p, TIER, 0x01); 145 146 /* enable channel */ 147 sh_mtu2_start_stop_ch(p, 1); 148 149 return 0; 150 } 151 152 static void sh_mtu2_disable(struct sh_mtu2_priv *p) 153 { 154 /* disable channel */ 155 sh_mtu2_start_stop_ch(p, 0); 156 157 /* stop clock */ 158 clk_disable(p->clk); 159 } 160 161 static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id) 162 { 163 struct sh_mtu2_priv *p = dev_id; 164 165 /* acknowledge interrupt */ 166 sh_mtu2_read(p, TSR); 167 sh_mtu2_write(p, TSR, 0xfe); 168 169 /* notify clockevent layer */ 170 p->ced.event_handler(&p->ced); 171 return IRQ_HANDLED; 172 } 173 174 static struct sh_mtu2_priv *ced_to_sh_mtu2(struct clock_event_device *ced) 175 { 176 return container_of(ced, struct sh_mtu2_priv, ced); 177 } 178 179 static void sh_mtu2_clock_event_mode(enum clock_event_mode mode, 180 struct clock_event_device *ced) 181 { 182 struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced); 183 int disabled = 0; 184 185 /* deal with old setting first */ 186 switch (ced->mode) { 187 case CLOCK_EVT_MODE_PERIODIC: 188 sh_mtu2_disable(p); 189 disabled = 1; 190 break; 191 default: 192 break; 193 } 194 195 switch (mode) { 196 case CLOCK_EVT_MODE_PERIODIC: 197 dev_info(&p->pdev->dev, "used for periodic clock events\n"); 198 sh_mtu2_enable(p); 199 break; 200 case CLOCK_EVT_MODE_UNUSED: 201 if (!disabled) 202 sh_mtu2_disable(p); 203 break; 204 case CLOCK_EVT_MODE_SHUTDOWN: 205 default: 206 break; 207 } 208 } 209 210 static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p, 211 char *name, unsigned long rating) 212 { 213 struct clock_event_device *ced = &p->ced; 214 int ret; 215 216 memset(ced, 0, sizeof(*ced)); 217 218 ced->name = name; 219 ced->features = CLOCK_EVT_FEAT_PERIODIC; 220 ced->rating = rating; 221 ced->cpumask = cpumask_of(0); 222 ced->set_mode = sh_mtu2_clock_event_mode; 223 224 dev_info(&p->pdev->dev, "used for clock events\n"); 225 clockevents_register_device(ced); 226 227 ret = setup_irq(p->irqaction.irq, &p->irqaction); 228 if (ret) { 229 dev_err(&p->pdev->dev, "failed to request irq %d\n", 230 p->irqaction.irq); 231 return; 232 } 233 } 234 235 static int sh_mtu2_register(struct sh_mtu2_priv *p, char *name, 236 unsigned long clockevent_rating) 237 { 238 if (clockevent_rating) 239 sh_mtu2_register_clockevent(p, name, clockevent_rating); 240 241 return 0; 242 } 243 244 static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev) 245 { 246 struct sh_timer_config *cfg = pdev->dev.platform_data; 247 struct resource *res; 248 int irq, ret; 249 ret = -ENXIO; 250 251 memset(p, 0, sizeof(*p)); 252 p->pdev = pdev; 253 254 if (!cfg) { 255 dev_err(&p->pdev->dev, "missing platform data\n"); 256 goto err0; 257 } 258 259 platform_set_drvdata(pdev, p); 260 261 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0); 262 if (!res) { 263 dev_err(&p->pdev->dev, "failed to get I/O memory\n"); 264 goto err0; 265 } 266 267 irq = platform_get_irq(p->pdev, 0); 268 if (irq < 0) { 269 dev_err(&p->pdev->dev, "failed to get irq\n"); 270 goto err0; 271 } 272 273 /* map memory, let mapbase point to our channel */ 274 p->mapbase = ioremap_nocache(res->start, resource_size(res)); 275 if (p->mapbase == NULL) { 276 dev_err(&p->pdev->dev, "failed to remap I/O memory\n"); 277 goto err0; 278 } 279 280 /* setup data for setup_irq() (too early for request_irq()) */ 281 p->irqaction.name = dev_name(&p->pdev->dev); 282 p->irqaction.handler = sh_mtu2_interrupt; 283 p->irqaction.dev_id = p; 284 p->irqaction.irq = irq; 285 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \ 286 IRQF_IRQPOLL | IRQF_NOBALANCING; 287 288 /* get hold of clock */ 289 p->clk = clk_get(&p->pdev->dev, "mtu2_fck"); 290 if (IS_ERR(p->clk)) { 291 dev_err(&p->pdev->dev, "cannot get clock\n"); 292 ret = PTR_ERR(p->clk); 293 goto err1; 294 } 295 296 return sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev), 297 cfg->clockevent_rating); 298 err1: 299 iounmap(p->mapbase); 300 err0: 301 return ret; 302 } 303 304 static int __devinit sh_mtu2_probe(struct platform_device *pdev) 305 { 306 struct sh_mtu2_priv *p = platform_get_drvdata(pdev); 307 int ret; 308 309 if (p) { 310 dev_info(&pdev->dev, "kept as earlytimer\n"); 311 return 0; 312 } 313 314 p = kmalloc(sizeof(*p), GFP_KERNEL); 315 if (p == NULL) { 316 dev_err(&pdev->dev, "failed to allocate driver data\n"); 317 return -ENOMEM; 318 } 319 320 ret = sh_mtu2_setup(p, pdev); 321 if (ret) { 322 kfree(p); 323 platform_set_drvdata(pdev, NULL); 324 } 325 return ret; 326 } 327 328 static int __devexit sh_mtu2_remove(struct platform_device *pdev) 329 { 330 return -EBUSY; /* cannot unregister clockevent */ 331 } 332 333 static struct platform_driver sh_mtu2_device_driver = { 334 .probe = sh_mtu2_probe, 335 .remove = __devexit_p(sh_mtu2_remove), 336 .driver = { 337 .name = "sh_mtu2", 338 } 339 }; 340 341 static int __init sh_mtu2_init(void) 342 { 343 return platform_driver_register(&sh_mtu2_device_driver); 344 } 345 346 static void __exit sh_mtu2_exit(void) 347 { 348 platform_driver_unregister(&sh_mtu2_device_driver); 349 } 350 351 early_platform_init("earlytimer", &sh_mtu2_device_driver); 352 module_init(sh_mtu2_init); 353 module_exit(sh_mtu2_exit); 354 355 MODULE_AUTHOR("Magnus Damm"); 356 MODULE_DESCRIPTION("SuperH MTU2 Timer Driver"); 357 MODULE_LICENSE("GPL v2"); 358