1 /* 2 * SuperH Timer Support - CMT 3 * 4 * Copyright (C) 2008 Magnus Damm 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/spinlock.h> 23 #include <linux/interrupt.h> 24 #include <linux/ioport.h> 25 #include <linux/io.h> 26 #include <linux/clk.h> 27 #include <linux/irq.h> 28 #include <linux/err.h> 29 #include <linux/clocksource.h> 30 #include <linux/clockchips.h> 31 #include <linux/sh_timer.h> 32 33 struct sh_cmt_priv { 34 void __iomem *mapbase; 35 struct clk *clk; 36 unsigned long width; /* 16 or 32 bit version of hardware block */ 37 unsigned long overflow_bit; 38 unsigned long clear_bits; 39 struct irqaction irqaction; 40 struct platform_device *pdev; 41 42 unsigned long flags; 43 unsigned long match_value; 44 unsigned long next_match_value; 45 unsigned long max_match_value; 46 unsigned long rate; 47 spinlock_t lock; 48 struct clock_event_device ced; 49 struct clocksource cs; 50 unsigned long total_cycles; 51 }; 52 53 static DEFINE_SPINLOCK(sh_cmt_lock); 54 55 #define CMSTR -1 /* shared register */ 56 #define CMCSR 0 /* channel register */ 57 #define CMCNT 1 /* channel register */ 58 #define CMCOR 2 /* channel register */ 59 60 static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr) 61 { 62 struct sh_timer_config *cfg = p->pdev->dev.platform_data; 63 void __iomem *base = p->mapbase; 64 unsigned long offs; 65 66 if (reg_nr == CMSTR) { 67 offs = 0; 68 base -= cfg->channel_offset; 69 } else 70 offs = reg_nr; 71 72 if (p->width == 16) 73 offs <<= 1; 74 else { 75 offs <<= 2; 76 if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) 77 return ioread32(base + offs); 78 } 79 80 return ioread16(base + offs); 81 } 82 83 static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr, 84 unsigned long value) 85 { 86 struct sh_timer_config *cfg = p->pdev->dev.platform_data; 87 void __iomem *base = p->mapbase; 88 unsigned long offs; 89 90 if (reg_nr == CMSTR) { 91 offs = 0; 92 base -= cfg->channel_offset; 93 } else 94 offs = reg_nr; 95 96 if (p->width == 16) 97 offs <<= 1; 98 else { 99 offs <<= 2; 100 if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) { 101 iowrite32(value, base + offs); 102 return; 103 } 104 } 105 106 iowrite16(value, base + offs); 107 } 108 109 static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p, 110 int *has_wrapped) 111 { 112 unsigned long v1, v2, v3; 113 int o1, o2; 114 115 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit; 116 117 /* Make sure the timer value is stable. Stolen from acpi_pm.c */ 118 do { 119 o2 = o1; 120 v1 = sh_cmt_read(p, CMCNT); 121 v2 = sh_cmt_read(p, CMCNT); 122 v3 = sh_cmt_read(p, CMCNT); 123 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit; 124 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) 125 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); 126 127 *has_wrapped = o1; 128 return v2; 129 } 130 131 132 static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start) 133 { 134 struct sh_timer_config *cfg = p->pdev->dev.platform_data; 135 unsigned long flags, value; 136 137 /* start stop register shared by multiple timer channels */ 138 spin_lock_irqsave(&sh_cmt_lock, flags); 139 value = sh_cmt_read(p, CMSTR); 140 141 if (start) 142 value |= 1 << cfg->timer_bit; 143 else 144 value &= ~(1 << cfg->timer_bit); 145 146 sh_cmt_write(p, CMSTR, value); 147 spin_unlock_irqrestore(&sh_cmt_lock, flags); 148 } 149 150 static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate) 151 { 152 struct sh_timer_config *cfg = p->pdev->dev.platform_data; 153 int ret; 154 155 /* enable clock */ 156 ret = clk_enable(p->clk); 157 if (ret) { 158 pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg->clk); 159 return ret; 160 } 161 162 /* make sure channel is disabled */ 163 sh_cmt_start_stop_ch(p, 0); 164 165 /* configure channel, periodic mode and maximum timeout */ 166 if (p->width == 16) { 167 *rate = clk_get_rate(p->clk) / 512; 168 sh_cmt_write(p, CMCSR, 0x43); 169 } else { 170 *rate = clk_get_rate(p->clk) / 8; 171 sh_cmt_write(p, CMCSR, 0x01a4); 172 } 173 174 sh_cmt_write(p, CMCOR, 0xffffffff); 175 sh_cmt_write(p, CMCNT, 0); 176 177 /* enable channel */ 178 sh_cmt_start_stop_ch(p, 1); 179 return 0; 180 } 181 182 static void sh_cmt_disable(struct sh_cmt_priv *p) 183 { 184 /* disable channel */ 185 sh_cmt_start_stop_ch(p, 0); 186 187 /* disable interrupts in CMT block */ 188 sh_cmt_write(p, CMCSR, 0); 189 190 /* stop clock */ 191 clk_disable(p->clk); 192 } 193 194 /* private flags */ 195 #define FLAG_CLOCKEVENT (1 << 0) 196 #define FLAG_CLOCKSOURCE (1 << 1) 197 #define FLAG_REPROGRAM (1 << 2) 198 #define FLAG_SKIPEVENT (1 << 3) 199 #define FLAG_IRQCONTEXT (1 << 4) 200 201 static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p, 202 int absolute) 203 { 204 unsigned long new_match; 205 unsigned long value = p->next_match_value; 206 unsigned long delay = 0; 207 unsigned long now = 0; 208 int has_wrapped; 209 210 now = sh_cmt_get_counter(p, &has_wrapped); 211 p->flags |= FLAG_REPROGRAM; /* force reprogram */ 212 213 if (has_wrapped) { 214 /* we're competing with the interrupt handler. 215 * -> let the interrupt handler reprogram the timer. 216 * -> interrupt number two handles the event. 217 */ 218 p->flags |= FLAG_SKIPEVENT; 219 return; 220 } 221 222 if (absolute) 223 now = 0; 224 225 do { 226 /* reprogram the timer hardware, 227 * but don't save the new match value yet. 228 */ 229 new_match = now + value + delay; 230 if (new_match > p->max_match_value) 231 new_match = p->max_match_value; 232 233 sh_cmt_write(p, CMCOR, new_match); 234 235 now = sh_cmt_get_counter(p, &has_wrapped); 236 if (has_wrapped && (new_match > p->match_value)) { 237 /* we are changing to a greater match value, 238 * so this wrap must be caused by the counter 239 * matching the old value. 240 * -> first interrupt reprograms the timer. 241 * -> interrupt number two handles the event. 242 */ 243 p->flags |= FLAG_SKIPEVENT; 244 break; 245 } 246 247 if (has_wrapped) { 248 /* we are changing to a smaller match value, 249 * so the wrap must be caused by the counter 250 * matching the new value. 251 * -> save programmed match value. 252 * -> let isr handle the event. 253 */ 254 p->match_value = new_match; 255 break; 256 } 257 258 /* be safe: verify hardware settings */ 259 if (now < new_match) { 260 /* timer value is below match value, all good. 261 * this makes sure we won't miss any match events. 262 * -> save programmed match value. 263 * -> let isr handle the event. 264 */ 265 p->match_value = new_match; 266 break; 267 } 268 269 /* the counter has reached a value greater 270 * than our new match value. and since the 271 * has_wrapped flag isn't set we must have 272 * programmed a too close event. 273 * -> increase delay and retry. 274 */ 275 if (delay) 276 delay <<= 1; 277 else 278 delay = 1; 279 280 if (!delay) 281 pr_warning("sh_cmt: too long delay\n"); 282 283 } while (delay); 284 } 285 286 static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta) 287 { 288 unsigned long flags; 289 290 if (delta > p->max_match_value) 291 pr_warning("sh_cmt: delta out of range\n"); 292 293 spin_lock_irqsave(&p->lock, flags); 294 p->next_match_value = delta; 295 sh_cmt_clock_event_program_verify(p, 0); 296 spin_unlock_irqrestore(&p->lock, flags); 297 } 298 299 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) 300 { 301 struct sh_cmt_priv *p = dev_id; 302 303 /* clear flags */ 304 sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits); 305 306 /* update clock source counter to begin with if enabled 307 * the wrap flag should be cleared by the timer specific 308 * isr before we end up here. 309 */ 310 if (p->flags & FLAG_CLOCKSOURCE) 311 p->total_cycles += p->match_value; 312 313 if (!(p->flags & FLAG_REPROGRAM)) 314 p->next_match_value = p->max_match_value; 315 316 p->flags |= FLAG_IRQCONTEXT; 317 318 if (p->flags & FLAG_CLOCKEVENT) { 319 if (!(p->flags & FLAG_SKIPEVENT)) { 320 if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) { 321 p->next_match_value = p->max_match_value; 322 p->flags |= FLAG_REPROGRAM; 323 } 324 325 p->ced.event_handler(&p->ced); 326 } 327 } 328 329 p->flags &= ~FLAG_SKIPEVENT; 330 331 if (p->flags & FLAG_REPROGRAM) { 332 p->flags &= ~FLAG_REPROGRAM; 333 sh_cmt_clock_event_program_verify(p, 1); 334 335 if (p->flags & FLAG_CLOCKEVENT) 336 if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN) 337 || (p->match_value == p->next_match_value)) 338 p->flags &= ~FLAG_REPROGRAM; 339 } 340 341 p->flags &= ~FLAG_IRQCONTEXT; 342 343 return IRQ_HANDLED; 344 } 345 346 static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag) 347 { 348 int ret = 0; 349 unsigned long flags; 350 351 spin_lock_irqsave(&p->lock, flags); 352 353 if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) 354 ret = sh_cmt_enable(p, &p->rate); 355 356 if (ret) 357 goto out; 358 p->flags |= flag; 359 360 /* setup timeout if no clockevent */ 361 if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT))) 362 sh_cmt_set_next(p, p->max_match_value); 363 out: 364 spin_unlock_irqrestore(&p->lock, flags); 365 366 return ret; 367 } 368 369 static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag) 370 { 371 unsigned long flags; 372 unsigned long f; 373 374 spin_lock_irqsave(&p->lock, flags); 375 376 f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); 377 p->flags &= ~flag; 378 379 if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) 380 sh_cmt_disable(p); 381 382 /* adjust the timeout to maximum if only clocksource left */ 383 if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE)) 384 sh_cmt_set_next(p, p->max_match_value); 385 386 spin_unlock_irqrestore(&p->lock, flags); 387 } 388 389 static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs) 390 { 391 return container_of(cs, struct sh_cmt_priv, cs); 392 } 393 394 static cycle_t sh_cmt_clocksource_read(struct clocksource *cs) 395 { 396 struct sh_cmt_priv *p = cs_to_sh_cmt(cs); 397 unsigned long flags, raw; 398 unsigned long value; 399 int has_wrapped; 400 401 spin_lock_irqsave(&p->lock, flags); 402 value = p->total_cycles; 403 raw = sh_cmt_get_counter(p, &has_wrapped); 404 405 if (unlikely(has_wrapped)) 406 raw += p->match_value; 407 spin_unlock_irqrestore(&p->lock, flags); 408 409 return value + raw; 410 } 411 412 static int sh_cmt_clocksource_enable(struct clocksource *cs) 413 { 414 struct sh_cmt_priv *p = cs_to_sh_cmt(cs); 415 int ret; 416 417 p->total_cycles = 0; 418 419 ret = sh_cmt_start(p, FLAG_CLOCKSOURCE); 420 if (ret) 421 return ret; 422 423 /* TODO: calculate good shift from rate and counter bit width */ 424 cs->shift = 0; 425 cs->mult = clocksource_hz2mult(p->rate, cs->shift); 426 return 0; 427 } 428 429 static void sh_cmt_clocksource_disable(struct clocksource *cs) 430 { 431 sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE); 432 } 433 434 static int sh_cmt_register_clocksource(struct sh_cmt_priv *p, 435 char *name, unsigned long rating) 436 { 437 struct clocksource *cs = &p->cs; 438 439 cs->name = name; 440 cs->rating = rating; 441 cs->read = sh_cmt_clocksource_read; 442 cs->enable = sh_cmt_clocksource_enable; 443 cs->disable = sh_cmt_clocksource_disable; 444 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); 445 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; 446 pr_info("sh_cmt: %s used as clock source\n", cs->name); 447 clocksource_register(cs); 448 return 0; 449 } 450 451 static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced) 452 { 453 return container_of(ced, struct sh_cmt_priv, ced); 454 } 455 456 static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic) 457 { 458 struct clock_event_device *ced = &p->ced; 459 460 sh_cmt_start(p, FLAG_CLOCKEVENT); 461 462 /* TODO: calculate good shift from rate and counter bit width */ 463 464 ced->shift = 32; 465 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift); 466 ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced); 467 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); 468 469 if (periodic) 470 sh_cmt_set_next(p, (p->rate + HZ/2) / HZ); 471 else 472 sh_cmt_set_next(p, p->max_match_value); 473 } 474 475 static void sh_cmt_clock_event_mode(enum clock_event_mode mode, 476 struct clock_event_device *ced) 477 { 478 struct sh_cmt_priv *p = ced_to_sh_cmt(ced); 479 480 /* deal with old setting first */ 481 switch (ced->mode) { 482 case CLOCK_EVT_MODE_PERIODIC: 483 case CLOCK_EVT_MODE_ONESHOT: 484 sh_cmt_stop(p, FLAG_CLOCKEVENT); 485 break; 486 default: 487 break; 488 } 489 490 switch (mode) { 491 case CLOCK_EVT_MODE_PERIODIC: 492 pr_info("sh_cmt: %s used for periodic clock events\n", 493 ced->name); 494 sh_cmt_clock_event_start(p, 1); 495 break; 496 case CLOCK_EVT_MODE_ONESHOT: 497 pr_info("sh_cmt: %s used for oneshot clock events\n", 498 ced->name); 499 sh_cmt_clock_event_start(p, 0); 500 break; 501 case CLOCK_EVT_MODE_SHUTDOWN: 502 case CLOCK_EVT_MODE_UNUSED: 503 sh_cmt_stop(p, FLAG_CLOCKEVENT); 504 break; 505 default: 506 break; 507 } 508 } 509 510 static int sh_cmt_clock_event_next(unsigned long delta, 511 struct clock_event_device *ced) 512 { 513 struct sh_cmt_priv *p = ced_to_sh_cmt(ced); 514 515 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT); 516 if (likely(p->flags & FLAG_IRQCONTEXT)) 517 p->next_match_value = delta; 518 else 519 sh_cmt_set_next(p, delta); 520 521 return 0; 522 } 523 524 static void sh_cmt_register_clockevent(struct sh_cmt_priv *p, 525 char *name, unsigned long rating) 526 { 527 struct clock_event_device *ced = &p->ced; 528 529 memset(ced, 0, sizeof(*ced)); 530 531 ced->name = name; 532 ced->features = CLOCK_EVT_FEAT_PERIODIC; 533 ced->features |= CLOCK_EVT_FEAT_ONESHOT; 534 ced->rating = rating; 535 ced->cpumask = cpumask_of(0); 536 ced->set_next_event = sh_cmt_clock_event_next; 537 ced->set_mode = sh_cmt_clock_event_mode; 538 539 pr_info("sh_cmt: %s used for clock events\n", ced->name); 540 clockevents_register_device(ced); 541 } 542 543 static int sh_cmt_register(struct sh_cmt_priv *p, char *name, 544 unsigned long clockevent_rating, 545 unsigned long clocksource_rating) 546 { 547 if (p->width == (sizeof(p->max_match_value) * 8)) 548 p->max_match_value = ~0; 549 else 550 p->max_match_value = (1 << p->width) - 1; 551 552 p->match_value = p->max_match_value; 553 spin_lock_init(&p->lock); 554 555 if (clockevent_rating) 556 sh_cmt_register_clockevent(p, name, clockevent_rating); 557 558 if (clocksource_rating) 559 sh_cmt_register_clocksource(p, name, clocksource_rating); 560 561 return 0; 562 } 563 564 static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev) 565 { 566 struct sh_timer_config *cfg = pdev->dev.platform_data; 567 struct resource *res; 568 int irq, ret; 569 ret = -ENXIO; 570 571 memset(p, 0, sizeof(*p)); 572 p->pdev = pdev; 573 574 if (!cfg) { 575 dev_err(&p->pdev->dev, "missing platform data\n"); 576 goto err0; 577 } 578 579 platform_set_drvdata(pdev, p); 580 581 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0); 582 if (!res) { 583 dev_err(&p->pdev->dev, "failed to get I/O memory\n"); 584 goto err0; 585 } 586 587 irq = platform_get_irq(p->pdev, 0); 588 if (irq < 0) { 589 dev_err(&p->pdev->dev, "failed to get irq\n"); 590 goto err0; 591 } 592 593 /* map memory, let mapbase point to our channel */ 594 p->mapbase = ioremap_nocache(res->start, resource_size(res)); 595 if (p->mapbase == NULL) { 596 pr_err("sh_cmt: failed to remap I/O memory\n"); 597 goto err0; 598 } 599 600 /* request irq using setup_irq() (too early for request_irq()) */ 601 p->irqaction.name = cfg->name; 602 p->irqaction.handler = sh_cmt_interrupt; 603 p->irqaction.dev_id = p; 604 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL; 605 ret = setup_irq(irq, &p->irqaction); 606 if (ret) { 607 pr_err("sh_cmt: failed to request irq %d\n", irq); 608 goto err1; 609 } 610 611 /* get hold of clock */ 612 p->clk = clk_get(&p->pdev->dev, cfg->clk); 613 if (IS_ERR(p->clk)) { 614 pr_err("sh_cmt: cannot get clock \"%s\"\n", cfg->clk); 615 ret = PTR_ERR(p->clk); 616 goto err2; 617 } 618 619 if (resource_size(res) == 6) { 620 p->width = 16; 621 p->overflow_bit = 0x80; 622 p->clear_bits = ~0x80; 623 } else { 624 p->width = 32; 625 p->overflow_bit = 0x8000; 626 p->clear_bits = ~0xc000; 627 } 628 629 return sh_cmt_register(p, cfg->name, 630 cfg->clockevent_rating, 631 cfg->clocksource_rating); 632 err2: 633 remove_irq(irq, &p->irqaction); 634 err1: 635 iounmap(p->mapbase); 636 err0: 637 return ret; 638 } 639 640 static int __devinit sh_cmt_probe(struct platform_device *pdev) 641 { 642 struct sh_cmt_priv *p = platform_get_drvdata(pdev); 643 struct sh_timer_config *cfg = pdev->dev.platform_data; 644 int ret; 645 646 if (p) { 647 pr_info("sh_cmt: %s kept as earlytimer\n", cfg->name); 648 return 0; 649 } 650 651 p = kmalloc(sizeof(*p), GFP_KERNEL); 652 if (p == NULL) { 653 dev_err(&pdev->dev, "failed to allocate driver data\n"); 654 return -ENOMEM; 655 } 656 657 ret = sh_cmt_setup(p, pdev); 658 if (ret) { 659 kfree(p); 660 platform_set_drvdata(pdev, NULL); 661 } 662 return ret; 663 } 664 665 static int __devexit sh_cmt_remove(struct platform_device *pdev) 666 { 667 return -EBUSY; /* cannot unregister clockevent and clocksource */ 668 } 669 670 static struct platform_driver sh_cmt_device_driver = { 671 .probe = sh_cmt_probe, 672 .remove = __devexit_p(sh_cmt_remove), 673 .driver = { 674 .name = "sh_cmt", 675 } 676 }; 677 678 static int __init sh_cmt_init(void) 679 { 680 return platform_driver_register(&sh_cmt_device_driver); 681 } 682 683 static void __exit sh_cmt_exit(void) 684 { 685 platform_driver_unregister(&sh_cmt_device_driver); 686 } 687 688 early_platform_init("earlytimer", &sh_cmt_device_driver); 689 module_init(sh_cmt_init); 690 module_exit(sh_cmt_exit); 691 692 MODULE_AUTHOR("Magnus Damm"); 693 MODULE_DESCRIPTION("SuperH CMT Timer Driver"); 694 MODULE_LICENSE("GPL v2"); 695