1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 3 4 #define pr_fmt(fmt) "mips-gic-timer: " fmt 5 6 #include <linux/clk.h> 7 #include <linux/clockchips.h> 8 #include <linux/cpu.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/notifier.h> 12 #include <linux/of_irq.h> 13 #include <linux/percpu.h> 14 #include <linux/sched_clock.h> 15 #include <linux/smp.h> 16 #include <linux/time.h> 17 #include <asm/mips-cps.h> 18 19 static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device); 20 static int gic_timer_irq; 21 static unsigned int gic_frequency; 22 static unsigned int gic_count_width; 23 static bool __read_mostly gic_clock_unstable; 24 25 static void gic_clocksource_unstable(char *reason); 26 27 static u64 notrace gic_read_count_2x32(void) 28 { 29 unsigned int hi, hi2, lo; 30 31 do { 32 hi = read_gic_counter_32h(); 33 lo = read_gic_counter_32l(); 34 hi2 = read_gic_counter_32h(); 35 } while (hi2 != hi); 36 37 return (((u64) hi) << 32) + lo; 38 } 39 40 static u64 notrace gic_read_count_64(void) 41 { 42 return read_gic_counter(); 43 } 44 45 static u64 notrace gic_read_count(void) 46 { 47 if (mips_cm_is64) 48 return gic_read_count_64(); 49 50 return gic_read_count_2x32(); 51 } 52 53 static int gic_next_event(unsigned long delta, struct clock_event_device *evt) 54 { 55 int cpu = cpumask_first(evt->cpumask); 56 u64 cnt; 57 int res; 58 59 cnt = gic_read_count(); 60 cnt += (u64)delta; 61 if (cpu == raw_smp_processor_id()) { 62 write_gic_vl_compare(cnt); 63 } else { 64 write_gic_vl_other(mips_cm_vp_id(cpu)); 65 write_gic_vo_compare(cnt); 66 } 67 res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0; 68 return res; 69 } 70 71 static irqreturn_t gic_compare_interrupt(int irq, void *dev_id) 72 { 73 struct clock_event_device *cd = dev_id; 74 75 write_gic_vl_compare(read_gic_vl_compare()); 76 cd->event_handler(cd); 77 return IRQ_HANDLED; 78 } 79 80 static struct irqaction gic_compare_irqaction = { 81 .handler = gic_compare_interrupt, 82 .percpu_dev_id = &gic_clockevent_device, 83 .flags = IRQF_PERCPU | IRQF_TIMER, 84 .name = "timer", 85 }; 86 87 static void gic_clockevent_cpu_init(unsigned int cpu, 88 struct clock_event_device *cd) 89 { 90 cd->name = "MIPS GIC"; 91 cd->features = CLOCK_EVT_FEAT_ONESHOT | 92 CLOCK_EVT_FEAT_C3STOP; 93 94 cd->rating = 350; 95 cd->irq = gic_timer_irq; 96 cd->cpumask = cpumask_of(cpu); 97 cd->set_next_event = gic_next_event; 98 99 clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff); 100 101 enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE); 102 } 103 104 static void gic_clockevent_cpu_exit(struct clock_event_device *cd) 105 { 106 disable_percpu_irq(gic_timer_irq); 107 } 108 109 static void gic_update_frequency(void *data) 110 { 111 unsigned long rate = (unsigned long)data; 112 113 clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device), rate); 114 } 115 116 static int gic_starting_cpu(unsigned int cpu) 117 { 118 /* Ensure the GIC counter is running */ 119 clear_gic_config(GIC_CONFIG_COUNTSTOP); 120 121 gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device)); 122 return 0; 123 } 124 125 static int gic_clk_notifier(struct notifier_block *nb, unsigned long action, 126 void *data) 127 { 128 struct clk_notifier_data *cnd = data; 129 130 if (action == POST_RATE_CHANGE) { 131 gic_clocksource_unstable("ref clock rate change"); 132 on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1); 133 } 134 135 return NOTIFY_OK; 136 } 137 138 static int gic_dying_cpu(unsigned int cpu) 139 { 140 gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device)); 141 return 0; 142 } 143 144 static struct notifier_block gic_clk_nb = { 145 .notifier_call = gic_clk_notifier, 146 }; 147 148 static int gic_clockevent_init(void) 149 { 150 int ret; 151 152 if (!gic_frequency) 153 return -ENXIO; 154 155 ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction); 156 if (ret < 0) { 157 pr_err("IRQ %d setup failed (%d)\n", gic_timer_irq, ret); 158 return ret; 159 } 160 161 cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING, 162 "clockevents/mips/gic/timer:starting", 163 gic_starting_cpu, gic_dying_cpu); 164 return 0; 165 } 166 167 static u64 gic_hpt_read(struct clocksource *cs) 168 { 169 return gic_read_count(); 170 } 171 172 static u64 gic_hpt_read_multicluster(struct clocksource *cs) 173 { 174 unsigned int hi, hi2, lo; 175 u64 count; 176 177 mips_cm_lock_other(0, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 178 179 if (mips_cm_is64) { 180 count = read_gic_redir_counter(); 181 goto out; 182 } 183 184 hi = read_gic_redir_counter_32h(); 185 while (true) { 186 lo = read_gic_redir_counter_32l(); 187 188 /* If hi didn't change then lo didn't wrap & we're done */ 189 hi2 = read_gic_redir_counter_32h(); 190 if (hi2 == hi) 191 break; 192 193 /* Otherwise, repeat with the latest hi value */ 194 hi = hi2; 195 } 196 197 count = (((u64)hi) << 32) + lo; 198 out: 199 mips_cm_unlock_other(); 200 return count; 201 } 202 203 static struct clocksource gic_clocksource = { 204 .name = "GIC", 205 .read = gic_hpt_read, 206 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 207 .vdso_clock_mode = VDSO_CLOCKMODE_GIC, 208 }; 209 210 static void gic_clocksource_unstable(char *reason) 211 { 212 if (gic_clock_unstable) 213 return; 214 215 gic_clock_unstable = true; 216 217 pr_info("GIC timer is unstable due to %s\n", reason); 218 219 clocksource_mark_unstable(&gic_clocksource); 220 } 221 222 static int __init __gic_clocksource_init(void) 223 { 224 int ret; 225 226 /* Set clocksource mask. */ 227 gic_count_width = read_gic_config() & GIC_CONFIG_COUNTBITS; 228 gic_count_width >>= __ffs(GIC_CONFIG_COUNTBITS); 229 gic_count_width *= 4; 230 gic_count_width += 32; 231 gic_clocksource.mask = CLOCKSOURCE_MASK(gic_count_width); 232 233 /* Calculate a somewhat reasonable rating value. */ 234 if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) 235 gic_clocksource.rating = 300; /* Good when frequecy is stable */ 236 else 237 gic_clocksource.rating = 200; 238 gic_clocksource.rating += clamp(gic_frequency / 10000000, 0, 99); 239 240 if (mips_cps_multicluster_cpus()) { 241 gic_clocksource.read = &gic_hpt_read_multicluster; 242 gic_clocksource.vdso_clock_mode = VDSO_CLOCKMODE_NONE; 243 } 244 245 ret = clocksource_register_hz(&gic_clocksource, gic_frequency); 246 if (ret < 0) 247 pr_warn("Unable to register clocksource\n"); 248 249 return ret; 250 } 251 252 static int __init gic_clocksource_of_init(struct device_node *node) 253 { 254 struct clk *clk; 255 int ret; 256 257 if (!mips_gic_present() || !node->parent || 258 !of_device_is_compatible(node->parent, "mti,gic")) { 259 pr_warn("No DT definition\n"); 260 return -ENXIO; 261 } 262 263 clk = of_clk_get(node, 0); 264 if (!IS_ERR(clk)) { 265 ret = clk_prepare_enable(clk); 266 if (ret < 0) { 267 pr_err("Failed to enable clock\n"); 268 clk_put(clk); 269 return ret; 270 } 271 272 gic_frequency = clk_get_rate(clk); 273 } else if (of_property_read_u32(node, "clock-frequency", 274 &gic_frequency)) { 275 pr_err("Frequency not specified\n"); 276 return -EINVAL; 277 } 278 gic_timer_irq = irq_of_parse_and_map(node, 0); 279 if (!gic_timer_irq) { 280 pr_err("IRQ not specified\n"); 281 return -EINVAL; 282 } 283 284 ret = __gic_clocksource_init(); 285 if (ret) 286 return ret; 287 288 ret = gic_clockevent_init(); 289 if (!ret && !IS_ERR(clk)) { 290 if (clk_notifier_register(clk, &gic_clk_nb) < 0) 291 pr_warn("Unable to register clock notifier\n"); 292 } 293 294 /* 295 * It's safe to use the MIPS GIC timer as a sched clock source only if 296 * its ticks are stable, which is true on either the platforms with 297 * stable CPU frequency or on the platforms with CM3 and CPU frequency 298 * change performed by the CPC core clocks divider. 299 */ 300 if ((mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) && 301 !mips_cps_multicluster_cpus()) { 302 sched_clock_register(mips_cm_is64 ? 303 gic_read_count_64 : gic_read_count_2x32, 304 gic_count_width, gic_frequency); 305 } 306 307 return 0; 308 } 309 TIMER_OF_DECLARE(mips_gic_timer, "mti,gic-timer", 310 gic_clocksource_of_init); 311