1 /* linux/arch/arm/mach-exynos4/mct.c 2 * 3 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com 5 * 6 * EXYNOS4 MCT(Multi-Core Timer) support 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/sched.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/err.h> 17 #include <linux/clk.h> 18 #include <linux/clockchips.h> 19 #include <linux/cpu.h> 20 #include <linux/platform_device.h> 21 #include <linux/delay.h> 22 #include <linux/percpu.h> 23 #include <linux/of.h> 24 #include <linux/of_irq.h> 25 #include <linux/of_address.h> 26 #include <linux/clocksource.h> 27 #include <linux/sched_clock.h> 28 29 #define EXYNOS4_MCTREG(x) (x) 30 #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100) 31 #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104) 32 #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110) 33 #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) 34 #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) 35 #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) 36 #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) 37 #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244) 38 #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) 39 #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) 40 #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) 41 #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) 42 #define EXYNOS4_MCT_L_MASK (0xffffff00) 43 44 #define MCT_L_TCNTB_OFFSET (0x00) 45 #define MCT_L_ICNTB_OFFSET (0x08) 46 #define MCT_L_TCON_OFFSET (0x20) 47 #define MCT_L_INT_CSTAT_OFFSET (0x30) 48 #define MCT_L_INT_ENB_OFFSET (0x34) 49 #define MCT_L_WSTAT_OFFSET (0x40) 50 #define MCT_G_TCON_START (1 << 8) 51 #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1) 52 #define MCT_G_TCON_COMP0_ENABLE (1 << 0) 53 #define MCT_L_TCON_INTERVAL_MODE (1 << 2) 54 #define MCT_L_TCON_INT_START (1 << 1) 55 #define MCT_L_TCON_TIMER_START (1 << 0) 56 57 #define TICK_BASE_CNT 1 58 59 enum { 60 MCT_INT_SPI, 61 MCT_INT_PPI 62 }; 63 64 enum { 65 MCT_G0_IRQ, 66 MCT_G1_IRQ, 67 MCT_G2_IRQ, 68 MCT_G3_IRQ, 69 MCT_L0_IRQ, 70 MCT_L1_IRQ, 71 MCT_L2_IRQ, 72 MCT_L3_IRQ, 73 MCT_L4_IRQ, 74 MCT_L5_IRQ, 75 MCT_L6_IRQ, 76 MCT_L7_IRQ, 77 MCT_NR_IRQS, 78 }; 79 80 static void __iomem *reg_base; 81 static unsigned long clk_rate; 82 static unsigned int mct_int_type; 83 static int mct_irqs[MCT_NR_IRQS]; 84 85 struct mct_clock_event_device { 86 struct clock_event_device evt; 87 unsigned long base; 88 char name[10]; 89 }; 90 91 static void exynos4_mct_write(unsigned int value, unsigned long offset) 92 { 93 unsigned long stat_addr; 94 u32 mask; 95 u32 i; 96 97 writel_relaxed(value, reg_base + offset); 98 99 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) { 100 stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; 101 switch (offset & ~EXYNOS4_MCT_L_MASK) { 102 case MCT_L_TCON_OFFSET: 103 mask = 1 << 3; /* L_TCON write status */ 104 break; 105 case MCT_L_ICNTB_OFFSET: 106 mask = 1 << 1; /* L_ICNTB write status */ 107 break; 108 case MCT_L_TCNTB_OFFSET: 109 mask = 1 << 0; /* L_TCNTB write status */ 110 break; 111 default: 112 return; 113 } 114 } else { 115 switch (offset) { 116 case EXYNOS4_MCT_G_TCON: 117 stat_addr = EXYNOS4_MCT_G_WSTAT; 118 mask = 1 << 16; /* G_TCON write status */ 119 break; 120 case EXYNOS4_MCT_G_COMP0_L: 121 stat_addr = EXYNOS4_MCT_G_WSTAT; 122 mask = 1 << 0; /* G_COMP0_L write status */ 123 break; 124 case EXYNOS4_MCT_G_COMP0_U: 125 stat_addr = EXYNOS4_MCT_G_WSTAT; 126 mask = 1 << 1; /* G_COMP0_U write status */ 127 break; 128 case EXYNOS4_MCT_G_COMP0_ADD_INCR: 129 stat_addr = EXYNOS4_MCT_G_WSTAT; 130 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */ 131 break; 132 case EXYNOS4_MCT_G_CNT_L: 133 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; 134 mask = 1 << 0; /* G_CNT_L write status */ 135 break; 136 case EXYNOS4_MCT_G_CNT_U: 137 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; 138 mask = 1 << 1; /* G_CNT_U write status */ 139 break; 140 default: 141 return; 142 } 143 } 144 145 /* Wait maximum 1 ms until written values are applied */ 146 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++) 147 if (readl_relaxed(reg_base + stat_addr) & mask) { 148 writel_relaxed(mask, reg_base + stat_addr); 149 return; 150 } 151 152 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset); 153 } 154 155 /* Clocksource handling */ 156 static void exynos4_mct_frc_start(void) 157 { 158 u32 reg; 159 160 reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); 161 reg |= MCT_G_TCON_START; 162 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); 163 } 164 165 /** 166 * exynos4_read_count_64 - Read all 64-bits of the global counter 167 * 168 * This will read all 64-bits of the global counter taking care to make sure 169 * that the upper and lower half match. Note that reading the MCT can be quite 170 * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half 171 * only) version when possible. 172 * 173 * Returns the number of cycles in the global counter. 174 */ 175 static u64 exynos4_read_count_64(void) 176 { 177 unsigned int lo, hi; 178 u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); 179 180 do { 181 hi = hi2; 182 lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); 183 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); 184 } while (hi != hi2); 185 186 return ((cycle_t)hi << 32) | lo; 187 } 188 189 /** 190 * exynos4_read_count_32 - Read the lower 32-bits of the global counter 191 * 192 * This will read just the lower 32-bits of the global counter. This is marked 193 * as notrace so it can be used by the scheduler clock. 194 * 195 * Returns the number of cycles in the global counter (lower 32 bits). 196 */ 197 static u32 notrace exynos4_read_count_32(void) 198 { 199 return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); 200 } 201 202 static cycle_t exynos4_frc_read(struct clocksource *cs) 203 { 204 return exynos4_read_count_32(); 205 } 206 207 static void exynos4_frc_resume(struct clocksource *cs) 208 { 209 exynos4_mct_frc_start(); 210 } 211 212 static struct clocksource mct_frc = { 213 .name = "mct-frc", 214 .rating = 400, 215 .read = exynos4_frc_read, 216 .mask = CLOCKSOURCE_MASK(32), 217 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 218 .resume = exynos4_frc_resume, 219 }; 220 221 static u64 notrace exynos4_read_sched_clock(void) 222 { 223 return exynos4_read_count_32(); 224 } 225 226 static struct delay_timer exynos4_delay_timer; 227 228 static cycles_t exynos4_read_current_timer(void) 229 { 230 BUILD_BUG_ON_MSG(sizeof(cycles_t) != sizeof(u32), 231 "cycles_t needs to move to 32-bit for ARM64 usage"); 232 return exynos4_read_count_32(); 233 } 234 235 static void __init exynos4_clocksource_init(void) 236 { 237 exynos4_mct_frc_start(); 238 239 exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer; 240 exynos4_delay_timer.freq = clk_rate; 241 register_current_timer_delay(&exynos4_delay_timer); 242 243 if (clocksource_register_hz(&mct_frc, clk_rate)) 244 panic("%s: can't register clocksource\n", mct_frc.name); 245 246 sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); 247 } 248 249 static void exynos4_mct_comp0_stop(void) 250 { 251 unsigned int tcon; 252 253 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); 254 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC); 255 256 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON); 257 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB); 258 } 259 260 static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles) 261 { 262 unsigned int tcon; 263 cycle_t comp_cycle; 264 265 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); 266 267 if (periodic) { 268 tcon |= MCT_G_TCON_COMP0_AUTO_INC; 269 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR); 270 } 271 272 comp_cycle = exynos4_read_count_64() + cycles; 273 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L); 274 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U); 275 276 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB); 277 278 tcon |= MCT_G_TCON_COMP0_ENABLE; 279 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON); 280 } 281 282 static int exynos4_comp_set_next_event(unsigned long cycles, 283 struct clock_event_device *evt) 284 { 285 exynos4_mct_comp0_start(false, cycles); 286 287 return 0; 288 } 289 290 static int mct_set_state_shutdown(struct clock_event_device *evt) 291 { 292 exynos4_mct_comp0_stop(); 293 return 0; 294 } 295 296 static int mct_set_state_periodic(struct clock_event_device *evt) 297 { 298 unsigned long cycles_per_jiffy; 299 300 cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult) 301 >> evt->shift); 302 exynos4_mct_comp0_stop(); 303 exynos4_mct_comp0_start(true, cycles_per_jiffy); 304 return 0; 305 } 306 307 static struct clock_event_device mct_comp_device = { 308 .name = "mct-comp", 309 .features = CLOCK_EVT_FEAT_PERIODIC | 310 CLOCK_EVT_FEAT_ONESHOT, 311 .rating = 250, 312 .set_next_event = exynos4_comp_set_next_event, 313 .set_state_periodic = mct_set_state_periodic, 314 .set_state_shutdown = mct_set_state_shutdown, 315 .set_state_oneshot = mct_set_state_shutdown, 316 .tick_resume = mct_set_state_shutdown, 317 }; 318 319 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id) 320 { 321 struct clock_event_device *evt = dev_id; 322 323 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT); 324 325 evt->event_handler(evt); 326 327 return IRQ_HANDLED; 328 } 329 330 static struct irqaction mct_comp_event_irq = { 331 .name = "mct_comp_irq", 332 .flags = IRQF_TIMER | IRQF_IRQPOLL, 333 .handler = exynos4_mct_comp_isr, 334 .dev_id = &mct_comp_device, 335 }; 336 337 static void exynos4_clockevent_init(void) 338 { 339 mct_comp_device.cpumask = cpumask_of(0); 340 clockevents_config_and_register(&mct_comp_device, clk_rate, 341 0xf, 0xffffffff); 342 setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq); 343 } 344 345 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick); 346 347 /* Clock event handling */ 348 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt) 349 { 350 unsigned long tmp; 351 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START; 352 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET; 353 354 tmp = readl_relaxed(reg_base + offset); 355 if (tmp & mask) { 356 tmp &= ~mask; 357 exynos4_mct_write(tmp, offset); 358 } 359 } 360 361 static void exynos4_mct_tick_start(unsigned long cycles, 362 struct mct_clock_event_device *mevt) 363 { 364 unsigned long tmp; 365 366 exynos4_mct_tick_stop(mevt); 367 368 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */ 369 370 /* update interrupt count buffer */ 371 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET); 372 373 /* enable MCT tick interrupt */ 374 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); 375 376 tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET); 377 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START | 378 MCT_L_TCON_INTERVAL_MODE; 379 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET); 380 } 381 382 static int exynos4_tick_set_next_event(unsigned long cycles, 383 struct clock_event_device *evt) 384 { 385 struct mct_clock_event_device *mevt; 386 387 mevt = container_of(evt, struct mct_clock_event_device, evt); 388 exynos4_mct_tick_start(cycles, mevt); 389 return 0; 390 } 391 392 static int set_state_shutdown(struct clock_event_device *evt) 393 { 394 struct mct_clock_event_device *mevt; 395 396 mevt = container_of(evt, struct mct_clock_event_device, evt); 397 exynos4_mct_tick_stop(mevt); 398 return 0; 399 } 400 401 static int set_state_periodic(struct clock_event_device *evt) 402 { 403 struct mct_clock_event_device *mevt; 404 unsigned long cycles_per_jiffy; 405 406 mevt = container_of(evt, struct mct_clock_event_device, evt); 407 cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult) 408 >> evt->shift); 409 exynos4_mct_tick_stop(mevt); 410 exynos4_mct_tick_start(cycles_per_jiffy, mevt); 411 return 0; 412 } 413 414 static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) 415 { 416 /* 417 * This is for supporting oneshot mode. 418 * Mct would generate interrupt periodically 419 * without explicit stopping. 420 */ 421 if (!clockevent_state_periodic(&mevt->evt)) 422 exynos4_mct_tick_stop(mevt); 423 424 /* Clear the MCT tick interrupt */ 425 if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) 426 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); 427 } 428 429 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) 430 { 431 struct mct_clock_event_device *mevt = dev_id; 432 struct clock_event_device *evt = &mevt->evt; 433 434 exynos4_mct_tick_clear(mevt); 435 436 evt->event_handler(evt); 437 438 return IRQ_HANDLED; 439 } 440 441 static int exynos4_local_timer_setup(struct mct_clock_event_device *mevt) 442 { 443 struct clock_event_device *evt = &mevt->evt; 444 unsigned int cpu = smp_processor_id(); 445 446 mevt->base = EXYNOS4_MCT_L_BASE(cpu); 447 snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu); 448 449 evt->name = mevt->name; 450 evt->cpumask = cpumask_of(cpu); 451 evt->set_next_event = exynos4_tick_set_next_event; 452 evt->set_state_periodic = set_state_periodic; 453 evt->set_state_shutdown = set_state_shutdown; 454 evt->set_state_oneshot = set_state_shutdown; 455 evt->tick_resume = set_state_shutdown; 456 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; 457 evt->rating = 450; 458 459 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); 460 461 if (mct_int_type == MCT_INT_SPI) { 462 463 if (evt->irq == -1) 464 return -EIO; 465 466 irq_force_affinity(evt->irq, cpumask_of(cpu)); 467 enable_irq(evt->irq); 468 } else { 469 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0); 470 } 471 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1), 472 0xf, 0x7fffffff); 473 474 return 0; 475 } 476 477 static void exynos4_local_timer_stop(struct mct_clock_event_device *mevt) 478 { 479 struct clock_event_device *evt = &mevt->evt; 480 481 evt->set_state_shutdown(evt); 482 if (mct_int_type == MCT_INT_SPI) { 483 if (evt->irq != -1) 484 disable_irq_nosync(evt->irq); 485 } else { 486 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); 487 } 488 } 489 490 static int exynos4_mct_cpu_notify(struct notifier_block *self, 491 unsigned long action, void *hcpu) 492 { 493 struct mct_clock_event_device *mevt; 494 495 /* 496 * Grab cpu pointer in each case to avoid spurious 497 * preemptible warnings 498 */ 499 switch (action & ~CPU_TASKS_FROZEN) { 500 case CPU_STARTING: 501 mevt = this_cpu_ptr(&percpu_mct_tick); 502 exynos4_local_timer_setup(mevt); 503 break; 504 case CPU_DYING: 505 mevt = this_cpu_ptr(&percpu_mct_tick); 506 exynos4_local_timer_stop(mevt); 507 break; 508 } 509 510 return NOTIFY_OK; 511 } 512 513 static struct notifier_block exynos4_mct_cpu_nb = { 514 .notifier_call = exynos4_mct_cpu_notify, 515 }; 516 517 static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base) 518 { 519 int err, cpu; 520 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick); 521 struct clk *mct_clk, *tick_clk; 522 523 tick_clk = np ? of_clk_get_by_name(np, "fin_pll") : 524 clk_get(NULL, "fin_pll"); 525 if (IS_ERR(tick_clk)) 526 panic("%s: unable to determine tick clock rate\n", __func__); 527 clk_rate = clk_get_rate(tick_clk); 528 529 mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct"); 530 if (IS_ERR(mct_clk)) 531 panic("%s: unable to retrieve mct clock instance\n", __func__); 532 clk_prepare_enable(mct_clk); 533 534 reg_base = base; 535 if (!reg_base) 536 panic("%s: unable to ioremap mct address space\n", __func__); 537 538 if (mct_int_type == MCT_INT_PPI) { 539 540 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ], 541 exynos4_mct_tick_isr, "MCT", 542 &percpu_mct_tick); 543 WARN(err, "MCT: can't request IRQ %d (%d)\n", 544 mct_irqs[MCT_L0_IRQ], err); 545 } else { 546 for_each_possible_cpu(cpu) { 547 int mct_irq = mct_irqs[MCT_L0_IRQ + cpu]; 548 struct mct_clock_event_device *pcpu_mevt = 549 per_cpu_ptr(&percpu_mct_tick, cpu); 550 551 pcpu_mevt->evt.irq = -1; 552 553 irq_set_status_flags(mct_irq, IRQ_NOAUTOEN); 554 if (request_irq(mct_irq, 555 exynos4_mct_tick_isr, 556 IRQF_TIMER | IRQF_NOBALANCING, 557 pcpu_mevt->name, pcpu_mevt)) { 558 pr_err("exynos-mct: cannot register IRQ (cpu%d)\n", 559 cpu); 560 561 continue; 562 } 563 pcpu_mevt->evt.irq = mct_irq; 564 } 565 } 566 567 err = register_cpu_notifier(&exynos4_mct_cpu_nb); 568 if (err) 569 goto out_irq; 570 571 /* Immediately configure the timer on the boot CPU */ 572 exynos4_local_timer_setup(mevt); 573 return; 574 575 out_irq: 576 free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick); 577 } 578 579 static void __init mct_init_dt(struct device_node *np, unsigned int int_type) 580 { 581 u32 nr_irqs, i; 582 583 mct_int_type = int_type; 584 585 /* This driver uses only one global timer interrupt */ 586 mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ); 587 588 /* 589 * Find out the number of local irqs specified. The local 590 * timer irqs are specified after the four global timer 591 * irqs are specified. 592 */ 593 #ifdef CONFIG_OF 594 nr_irqs = of_irq_count(np); 595 #else 596 nr_irqs = 0; 597 #endif 598 for (i = MCT_L0_IRQ; i < nr_irqs; i++) 599 mct_irqs[i] = irq_of_parse_and_map(np, i); 600 601 exynos4_timer_resources(np, of_iomap(np, 0)); 602 exynos4_clocksource_init(); 603 exynos4_clockevent_init(); 604 } 605 606 607 static void __init mct_init_spi(struct device_node *np) 608 { 609 return mct_init_dt(np, MCT_INT_SPI); 610 } 611 612 static void __init mct_init_ppi(struct device_node *np) 613 { 614 return mct_init_dt(np, MCT_INT_PPI); 615 } 616 CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi); 617 CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi); 618