1 /* 2 * Clocksource using the Low Power Timer found in the Low Power Controller (LPC) 3 * 4 * Copyright (C) 2015 STMicroelectronics – All Rights Reserved 5 * 6 * Author(s): Francesco Virlinzi <francesco.virlinzi@st.com> 7 * Ajit Pal Singh <ajitpal.singh@st.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/clocksource.h> 17 #include <linux/init.h> 18 #include <linux/of_address.h> 19 #include <linux/sched_clock.h> 20 #include <linux/slab.h> 21 22 #include <dt-bindings/mfd/st-lpc.h> 23 24 /* Low Power Timer */ 25 #define LPC_LPT_LSB_OFF 0x400 26 #define LPC_LPT_MSB_OFF 0x404 27 #define LPC_LPT_START_OFF 0x408 28 29 static struct st_clksrc_ddata { 30 struct clk *clk; 31 void __iomem *base; 32 } ddata; 33 34 static void __init st_clksrc_reset(void) 35 { 36 writel_relaxed(0, ddata.base + LPC_LPT_START_OFF); 37 writel_relaxed(0, ddata.base + LPC_LPT_MSB_OFF); 38 writel_relaxed(0, ddata.base + LPC_LPT_LSB_OFF); 39 writel_relaxed(1, ddata.base + LPC_LPT_START_OFF); 40 } 41 42 static u64 notrace st_clksrc_sched_clock_read(void) 43 { 44 return (u64)readl_relaxed(ddata.base + LPC_LPT_LSB_OFF); 45 } 46 47 static int __init st_clksrc_init(void) 48 { 49 unsigned long rate; 50 int ret; 51 52 st_clksrc_reset(); 53 54 rate = clk_get_rate(ddata.clk); 55 56 sched_clock_register(st_clksrc_sched_clock_read, 32, rate); 57 58 ret = clocksource_mmio_init(ddata.base + LPC_LPT_LSB_OFF, 59 "clksrc-st-lpc", rate, 300, 32, 60 clocksource_mmio_readl_up); 61 if (ret) { 62 pr_err("clksrc-st-lpc: Failed to register clocksource\n"); 63 return ret; 64 } 65 66 return 0; 67 } 68 69 static int __init st_clksrc_setup_clk(struct device_node *np) 70 { 71 struct clk *clk; 72 73 clk = of_clk_get(np, 0); 74 if (IS_ERR(clk)) { 75 pr_err("clksrc-st-lpc: Failed to get LPC clock\n"); 76 return PTR_ERR(clk); 77 } 78 79 if (clk_prepare_enable(clk)) { 80 pr_err("clksrc-st-lpc: Failed to enable LPC clock\n"); 81 return -EINVAL; 82 } 83 84 if (!clk_get_rate(clk)) { 85 pr_err("clksrc-st-lpc: Failed to get LPC clock rate\n"); 86 clk_disable_unprepare(clk); 87 return -EINVAL; 88 } 89 90 ddata.clk = clk; 91 92 return 0; 93 } 94 95 static void __init st_clksrc_of_register(struct device_node *np) 96 { 97 int ret; 98 uint32_t mode; 99 100 ret = of_property_read_u32(np, "st,lpc-mode", &mode); 101 if (ret) { 102 pr_err("clksrc-st-lpc: An LPC mode must be provided\n"); 103 return; 104 } 105 106 /* LPC can either run as a Clocksource or in RTC or WDT mode */ 107 if (mode != ST_LPC_MODE_CLKSRC) 108 return; 109 110 ddata.base = of_iomap(np, 0); 111 if (!ddata.base) { 112 pr_err("clksrc-st-lpc: Unable to map iomem\n"); 113 return; 114 } 115 116 if (st_clksrc_setup_clk(np)) { 117 iounmap(ddata.base); 118 return; 119 } 120 121 if (st_clksrc_init()) { 122 clk_disable_unprepare(ddata.clk); 123 clk_put(ddata.clk); 124 iounmap(ddata.base); 125 return; 126 } 127 128 pr_info("clksrc-st-lpc: clocksource initialised - running @ %luHz\n", 129 clk_get_rate(ddata.clk)); 130 } 131 CLOCKSOURCE_OF_DECLARE(ddata, "st,stih407-lpc", st_clksrc_of_register); 132