xref: /linux/drivers/clocksource/arm_global_timer.c (revision fcb3ad4366b9c810cbb9da34c076a9a52d8aa1e0)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * drivers/clocksource/arm_global_timer.c
4  *
5  * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
6  * Author: Stuart Menefy <stuart.menefy@st.com>
7  * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
8  */
9 
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/bitfield.h>
13 #include <linux/clocksource.h>
14 #include <linux/clockchips.h>
15 #include <linux/cpu.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20 #include <linux/of.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_address.h>
23 #include <linux/sched_clock.h>
24 
25 #include <asm/cputype.h>
26 
27 #define GT_COUNTER0	0x00
28 #define GT_COUNTER1	0x04
29 
30 #define GT_CONTROL	0x08
31 #define GT_CONTROL_TIMER_ENABLE		BIT(0)  /* this bit is NOT banked */
32 #define GT_CONTROL_COMP_ENABLE		BIT(1)	/* banked */
33 #define GT_CONTROL_IRQ_ENABLE		BIT(2)	/* banked */
34 #define GT_CONTROL_AUTO_INC		BIT(3)	/* banked */
35 #define GT_CONTROL_PRESCALER_MASK	GENMASK(15, 8)
36 
37 #define GT_INT_STATUS	0x0c
38 #define GT_INT_STATUS_EVENT_FLAG	BIT(0)
39 
40 #define GT_COMP0	0x10
41 #define GT_COMP1	0x14
42 #define GT_AUTO_INC	0x18
43 
44 #define MAX_F_ERR 50
45 /*
46  * We are expecting to be clocked by the ARM peripheral clock.
47  *
48  * Note: it is assumed we are using a prescaler value of zero, so this is
49  * the units for all operations.
50  */
51 static void __iomem *gt_base;
52 static struct notifier_block gt_clk_rate_change_nb;
53 static u32 gt_psv_new, gt_psv_bck;
54 static unsigned long gt_target_rate;
55 static int gt_ppi;
56 static struct clock_event_device __percpu *gt_evt;
57 
58 /*
59  * To get the value from the Global Timer Counter register proceed as follows:
60  * 1. Read the upper 32-bit timer counter register
61  * 2. Read the lower 32-bit timer counter register
62  * 3. Read the upper 32-bit timer counter register again. If the value is
63  *  different to the 32-bit upper value read previously, go back to step 2.
64  *  Otherwise the 64-bit timer counter value is correct.
65  */
66 static u64 notrace _gt_counter_read(void)
67 {
68 	u64 counter;
69 	u32 lower;
70 	u32 upper, old_upper;
71 
72 	upper = readl_relaxed(gt_base + GT_COUNTER1);
73 	do {
74 		old_upper = upper;
75 		lower = readl_relaxed(gt_base + GT_COUNTER0);
76 		upper = readl_relaxed(gt_base + GT_COUNTER1);
77 	} while (upper != old_upper);
78 
79 	counter = upper;
80 	counter <<= 32;
81 	counter |= lower;
82 	return counter;
83 }
84 
85 static u64 gt_counter_read(void)
86 {
87 	return _gt_counter_read();
88 }
89 
90 /*
91  * To ensure that updates to comparator value register do not set the
92  * Interrupt Status Register proceed as follows:
93  * 1. Clear the Comp Enable bit in the Timer Control Register.
94  * 2. Write the lower 32-bit Comparator Value Register.
95  * 3. Write the upper 32-bit Comparator Value Register.
96  * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.
97  */
98 static void gt_compare_set(unsigned long delta, int periodic)
99 {
100 	u64 counter = gt_counter_read();
101 	unsigned long ctrl;
102 
103 	counter += delta;
104 	ctrl = readl(gt_base + GT_CONTROL);
105 	ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE |
106 		  GT_CONTROL_AUTO_INC);
107 	ctrl |= GT_CONTROL_TIMER_ENABLE;
108 	writel_relaxed(ctrl, gt_base + GT_CONTROL);
109 	writel_relaxed(lower_32_bits(counter), gt_base + GT_COMP0);
110 	writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1);
111 
112 	if (periodic) {
113 		writel_relaxed(delta, gt_base + GT_AUTO_INC);
114 		ctrl |= GT_CONTROL_AUTO_INC;
115 	}
116 
117 	ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
118 	writel_relaxed(ctrl, gt_base + GT_CONTROL);
119 }
120 
121 static int gt_clockevent_shutdown(struct clock_event_device *evt)
122 {
123 	unsigned long ctrl;
124 
125 	ctrl = readl(gt_base + GT_CONTROL);
126 	ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE |
127 		  GT_CONTROL_AUTO_INC);
128 	writel(ctrl, gt_base + GT_CONTROL);
129 	return 0;
130 }
131 
132 static int gt_clockevent_set_periodic(struct clock_event_device *evt)
133 {
134 	gt_compare_set(DIV_ROUND_CLOSEST(gt_target_rate, HZ), 1);
135 	return 0;
136 }
137 
138 static int gt_clockevent_set_next_event(unsigned long evt,
139 					struct clock_event_device *unused)
140 {
141 	gt_compare_set(evt, 0);
142 	return 0;
143 }
144 
145 static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
146 {
147 	struct clock_event_device *evt = dev_id;
148 
149 	if (!(readl_relaxed(gt_base + GT_INT_STATUS) &
150 				GT_INT_STATUS_EVENT_FLAG))
151 		return IRQ_NONE;
152 
153 	/**
154 	 * ERRATA 740657( Global Timer can send 2 interrupts for
155 	 * the same event in single-shot mode)
156 	 * Workaround:
157 	 *	Either disable single-shot mode.
158 	 *	Or
159 	 *	Modify the Interrupt Handler to avoid the
160 	 *	offending sequence. This is achieved by clearing
161 	 *	the Global Timer flag _after_ having incremented
162 	 *	the Comparator register	value to a higher value.
163 	 */
164 	if (clockevent_state_oneshot(evt))
165 		gt_compare_set(ULONG_MAX, 0);
166 
167 	writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
168 	evt->event_handler(evt);
169 
170 	return IRQ_HANDLED;
171 }
172 
173 static int gt_starting_cpu(unsigned int cpu)
174 {
175 	struct clock_event_device *clk = this_cpu_ptr(gt_evt);
176 
177 	clk->name = "arm_global_timer";
178 	clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
179 		CLOCK_EVT_FEAT_PERCPU;
180 	clk->set_state_shutdown = gt_clockevent_shutdown;
181 	clk->set_state_periodic = gt_clockevent_set_periodic;
182 	clk->set_state_oneshot = gt_clockevent_shutdown;
183 	clk->set_state_oneshot_stopped = gt_clockevent_shutdown;
184 	clk->set_next_event = gt_clockevent_set_next_event;
185 	clk->cpumask = cpumask_of(cpu);
186 	clk->rating = 300;
187 	clk->irq = gt_ppi;
188 	clockevents_config_and_register(clk, gt_target_rate,
189 					1, 0xffffffff);
190 	enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
191 	return 0;
192 }
193 
194 static int gt_dying_cpu(unsigned int cpu)
195 {
196 	struct clock_event_device *clk = this_cpu_ptr(gt_evt);
197 
198 	disable_percpu_irq(clk->irq);
199 	return 0;
200 }
201 
202 static u64 gt_clocksource_read(struct clocksource *cs)
203 {
204 	return gt_counter_read();
205 }
206 
207 static void gt_resume(struct clocksource *cs)
208 {
209 	unsigned long ctrl;
210 
211 	ctrl = readl(gt_base + GT_CONTROL);
212 	if (!(ctrl & GT_CONTROL_TIMER_ENABLE))
213 		/* re-enable timer on resume */
214 		writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
215 }
216 
217 static struct clocksource gt_clocksource = {
218 	.name	= "arm_global_timer",
219 	.rating	= 300,
220 	.read	= gt_clocksource_read,
221 	.mask	= CLOCKSOURCE_MASK(64),
222 	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
223 	.resume = gt_resume,
224 };
225 
226 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
227 static u64 notrace gt_sched_clock_read(void)
228 {
229 	return _gt_counter_read();
230 }
231 #endif
232 
233 static unsigned long gt_read_long(void)
234 {
235 	return readl_relaxed(gt_base + GT_COUNTER0);
236 }
237 
238 static struct delay_timer gt_delay_timer = {
239 	.read_current_timer = gt_read_long,
240 };
241 
242 static void gt_write_presc(u32 psv)
243 {
244 	u32 reg;
245 
246 	reg = readl(gt_base + GT_CONTROL);
247 	reg &= ~GT_CONTROL_PRESCALER_MASK;
248 	reg |= FIELD_PREP(GT_CONTROL_PRESCALER_MASK, psv);
249 	writel(reg, gt_base + GT_CONTROL);
250 }
251 
252 static u32 gt_read_presc(void)
253 {
254 	u32 reg;
255 
256 	reg = readl(gt_base + GT_CONTROL);
257 	return FIELD_GET(GT_CONTROL_PRESCALER_MASK, reg);
258 }
259 
260 static void __init gt_delay_timer_init(void)
261 {
262 	gt_delay_timer.freq = gt_target_rate;
263 	register_current_timer_delay(&gt_delay_timer);
264 }
265 
266 static int __init gt_clocksource_init(void)
267 {
268 	writel(0, gt_base + GT_CONTROL);
269 	writel(0, gt_base + GT_COUNTER0);
270 	writel(0, gt_base + GT_COUNTER1);
271 	/* set prescaler and enable timer on all the cores */
272 	writel(FIELD_PREP(GT_CONTROL_PRESCALER_MASK,
273 			  CONFIG_ARM_GT_INITIAL_PRESCALER_VAL - 1) |
274 	       GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
275 
276 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
277 	sched_clock_register(gt_sched_clock_read, 64, gt_target_rate);
278 #endif
279 	return clocksource_register_hz(&gt_clocksource, gt_target_rate);
280 }
281 
282 static int gt_clk_rate_change_cb(struct notifier_block *nb,
283 				 unsigned long event, void *data)
284 {
285 	struct clk_notifier_data *ndata = data;
286 
287 	switch (event) {
288 	case PRE_RATE_CHANGE:
289 	{
290 		unsigned long psv;
291 
292 		psv = DIV_ROUND_CLOSEST(ndata->new_rate, gt_target_rate);
293 		if (!psv ||
294 		    abs(gt_target_rate - (ndata->new_rate / psv)) > MAX_F_ERR)
295 			return NOTIFY_BAD;
296 
297 		psv--;
298 
299 		/* prescaler within legal range? */
300 		if (!FIELD_FIT(GT_CONTROL_PRESCALER_MASK, psv))
301 			return NOTIFY_BAD;
302 
303 		/*
304 		 * store timer clock ctrl register so we can restore it in case
305 		 * of an abort.
306 		 */
307 		gt_psv_bck = gt_read_presc();
308 		gt_psv_new = psv;
309 		/* scale down: adjust divider in post-change notification */
310 		if (ndata->new_rate < ndata->old_rate)
311 			return NOTIFY_DONE;
312 
313 		/* scale up: adjust divider now - before frequency change */
314 		gt_write_presc(psv);
315 		break;
316 	}
317 	case POST_RATE_CHANGE:
318 		/* scale up: pre-change notification did the adjustment */
319 		if (ndata->new_rate > ndata->old_rate)
320 			return NOTIFY_OK;
321 
322 		/* scale down: adjust divider now - after frequency change */
323 		gt_write_presc(gt_psv_new);
324 		break;
325 
326 	case ABORT_RATE_CHANGE:
327 		/* we have to undo the adjustment in case we scale up */
328 		if (ndata->new_rate < ndata->old_rate)
329 			return NOTIFY_OK;
330 
331 		/* restore original register value */
332 		gt_write_presc(gt_psv_bck);
333 		break;
334 	default:
335 		return NOTIFY_DONE;
336 	}
337 
338 	return NOTIFY_DONE;
339 }
340 
341 static int __init global_timer_of_register(struct device_node *np)
342 {
343 	struct clk *gt_clk;
344 	static unsigned long gt_clk_rate;
345 	int err;
346 
347 	/*
348 	 * In A9 r2p0 the comparators for each processor with the global timer
349 	 * fire when the timer value is greater than or equal to. In previous
350 	 * revisions the comparators fired when the timer value was equal to.
351 	 */
352 	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9
353 	    && (read_cpuid_id() & 0xf0000f) < 0x200000) {
354 		pr_warn("global-timer: non support for this cpu version.\n");
355 		return -ENOSYS;
356 	}
357 
358 	gt_ppi = irq_of_parse_and_map(np, 0);
359 	if (!gt_ppi) {
360 		pr_warn("global-timer: unable to parse irq\n");
361 		return -EINVAL;
362 	}
363 
364 	gt_base = of_iomap(np, 0);
365 	if (!gt_base) {
366 		pr_warn("global-timer: invalid base address\n");
367 		return -ENXIO;
368 	}
369 
370 	gt_clk = of_clk_get(np, 0);
371 	if (!IS_ERR(gt_clk)) {
372 		err = clk_prepare_enable(gt_clk);
373 		if (err)
374 			goto out_unmap;
375 	} else {
376 		pr_warn("global-timer: clk not found\n");
377 		err = -EINVAL;
378 		goto out_unmap;
379 	}
380 
381 	gt_clk_rate = clk_get_rate(gt_clk);
382 	gt_target_rate = gt_clk_rate / CONFIG_ARM_GT_INITIAL_PRESCALER_VAL;
383 	gt_clk_rate_change_nb.notifier_call =
384 		gt_clk_rate_change_cb;
385 	err = clk_notifier_register(gt_clk, &gt_clk_rate_change_nb);
386 	if (err) {
387 		pr_warn("Unable to register clock notifier\n");
388 		goto out_clk;
389 	}
390 
391 	gt_evt = alloc_percpu(struct clock_event_device);
392 	if (!gt_evt) {
393 		pr_warn("global-timer: can't allocate memory\n");
394 		err = -ENOMEM;
395 		goto out_clk_nb;
396 	}
397 
398 	err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt,
399 				 "gt", gt_evt);
400 	if (err) {
401 		pr_warn("global-timer: can't register interrupt %d (%d)\n",
402 			gt_ppi, err);
403 		goto out_free;
404 	}
405 
406 	/* Register and immediately configure the timer on the boot CPU */
407 	err = gt_clocksource_init();
408 	if (err)
409 		goto out_irq;
410 
411 	err = cpuhp_setup_state(CPUHP_AP_ARM_GLOBAL_TIMER_STARTING,
412 				"clockevents/arm/global_timer:starting",
413 				gt_starting_cpu, gt_dying_cpu);
414 	if (err)
415 		goto out_irq;
416 
417 	gt_delay_timer_init();
418 
419 	return 0;
420 
421 out_irq:
422 	free_percpu_irq(gt_ppi, gt_evt);
423 out_free:
424 	free_percpu(gt_evt);
425 out_clk_nb:
426 	clk_notifier_unregister(gt_clk, &gt_clk_rate_change_nb);
427 out_clk:
428 	clk_disable_unprepare(gt_clk);
429 out_unmap:
430 	iounmap(gt_base);
431 	WARN(err, "ARM Global timer register failed (%d)\n", err);
432 
433 	return err;
434 }
435 
436 /* Only tested on r2p2 and r3p0  */
437 TIMER_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
438 			global_timer_of_register);
439