1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ARM Generic Memory Mapped Timer support 4 * 5 * Split from drivers/clocksource/arm_arch_timer.c 6 * 7 * Copyright (C) 2011 ARM Ltd. 8 * All Rights Reserved 9 */ 10 11 #define pr_fmt(fmt) "arch_timer_mmio: " fmt 12 13 #include <linux/clockchips.h> 14 #include <linux/interrupt.h> 15 #include <linux/io-64-nonatomic-lo-hi.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_address.h> 18 #include <linux/platform_device.h> 19 20 #include <clocksource/arm_arch_timer.h> 21 22 #define CNTTIDR 0x08 23 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4)) 24 25 #define CNTACR(n) (0x40 + ((n) * 4)) 26 #define CNTACR_RPCT BIT(0) 27 #define CNTACR_RVCT BIT(1) 28 #define CNTACR_RFRQ BIT(2) 29 #define CNTACR_RVOFF BIT(3) 30 #define CNTACR_RWVT BIT(4) 31 #define CNTACR_RWPT BIT(5) 32 33 #define CNTPCT_LO 0x00 34 #define CNTVCT_LO 0x08 35 #define CNTFRQ 0x10 36 #define CNTP_CVAL_LO 0x20 37 #define CNTP_CTL 0x2c 38 #define CNTV_CVAL_LO 0x30 39 #define CNTV_CTL 0x3c 40 41 enum arch_timer_access { 42 PHYS_ACCESS, 43 VIRT_ACCESS, 44 }; 45 46 struct arch_timer { 47 struct clock_event_device evt; 48 struct arch_timer_mem *gt_block; 49 void __iomem *base; 50 enum arch_timer_access access; 51 u32 rate; 52 }; 53 54 #define evt_to_arch_timer(e) container_of(e, struct arch_timer, evt) 55 56 static void arch_timer_mmio_write(struct arch_timer *timer, 57 enum arch_timer_reg reg, u64 val) 58 { 59 switch (timer->access) { 60 case PHYS_ACCESS: 61 switch (reg) { 62 case ARCH_TIMER_REG_CTRL: 63 writel_relaxed((u32)val, timer->base + CNTP_CTL); 64 return; 65 case ARCH_TIMER_REG_CVAL: 66 /* 67 * Not guaranteed to be atomic, so the timer 68 * must be disabled at this point. 69 */ 70 writeq_relaxed(val, timer->base + CNTP_CVAL_LO); 71 return; 72 } 73 break; 74 case VIRT_ACCESS: 75 switch (reg) { 76 case ARCH_TIMER_REG_CTRL: 77 writel_relaxed((u32)val, timer->base + CNTV_CTL); 78 return; 79 case ARCH_TIMER_REG_CVAL: 80 /* Same restriction as above */ 81 writeq_relaxed(val, timer->base + CNTV_CVAL_LO); 82 return; 83 } 84 break; 85 } 86 87 /* Should never be here */ 88 WARN_ON_ONCE(1); 89 } 90 91 static u32 arch_timer_mmio_read(struct arch_timer *timer, enum arch_timer_reg reg) 92 { 93 switch (timer->access) { 94 case PHYS_ACCESS: 95 switch (reg) { 96 case ARCH_TIMER_REG_CTRL: 97 return readl_relaxed(timer->base + CNTP_CTL); 98 default: 99 break; 100 } 101 break; 102 case VIRT_ACCESS: 103 switch (reg) { 104 case ARCH_TIMER_REG_CTRL: 105 return readl_relaxed(timer->base + CNTV_CTL); 106 default: 107 break; 108 } 109 break; 110 } 111 112 /* Should never be here */ 113 WARN_ON_ONCE(1); 114 return 0; 115 } 116 117 static noinstr u64 arch_counter_mmio_get_cnt(struct arch_timer *t) 118 { 119 int offset_lo = t->access == VIRT_ACCESS ? CNTVCT_LO : CNTPCT_LO; 120 u32 cnt_lo, cnt_hi, tmp_hi; 121 122 do { 123 cnt_hi = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo + 4)); 124 cnt_lo = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo)); 125 tmp_hi = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo + 4)); 126 } while (cnt_hi != tmp_hi); 127 128 return ((u64) cnt_hi << 32) | cnt_lo; 129 } 130 131 static int arch_timer_mmio_shutdown(struct clock_event_device *clk) 132 { 133 struct arch_timer *at = evt_to_arch_timer(clk); 134 unsigned long ctrl; 135 136 ctrl = arch_timer_mmio_read(at, ARCH_TIMER_REG_CTRL); 137 ctrl &= ~ARCH_TIMER_CTRL_ENABLE; 138 arch_timer_mmio_write(at, ARCH_TIMER_REG_CTRL, ctrl); 139 140 return 0; 141 } 142 143 static int arch_timer_mmio_set_next_event(unsigned long evt, 144 struct clock_event_device *clk) 145 { 146 struct arch_timer *timer = evt_to_arch_timer(clk); 147 unsigned long ctrl; 148 u64 cnt; 149 150 ctrl = arch_timer_mmio_read(timer, ARCH_TIMER_REG_CTRL); 151 152 /* Timer must be disabled before programming CVAL */ 153 if (ctrl & ARCH_TIMER_CTRL_ENABLE) { 154 ctrl &= ~ARCH_TIMER_CTRL_ENABLE; 155 arch_timer_mmio_write(timer, ARCH_TIMER_REG_CTRL, ctrl); 156 } 157 158 ctrl |= ARCH_TIMER_CTRL_ENABLE; 159 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; 160 161 cnt = arch_counter_mmio_get_cnt(timer); 162 163 arch_timer_mmio_write(timer, ARCH_TIMER_REG_CVAL, evt + cnt); 164 arch_timer_mmio_write(timer, ARCH_TIMER_REG_CTRL, ctrl); 165 return 0; 166 } 167 168 static irqreturn_t arch_timer_mmio_handler(int irq, void *dev_id) 169 { 170 struct clock_event_device *evt = dev_id; 171 struct arch_timer *at = evt_to_arch_timer(evt); 172 unsigned long ctrl; 173 174 ctrl = arch_timer_mmio_read(at, ARCH_TIMER_REG_CTRL); 175 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { 176 ctrl |= ARCH_TIMER_CTRL_IT_MASK; 177 arch_timer_mmio_write(at, ARCH_TIMER_REG_CTRL, ctrl); 178 evt->event_handler(evt); 179 return IRQ_HANDLED; 180 } 181 182 return IRQ_NONE; 183 } 184 185 static struct arch_timer_mem_frame *find_best_frame(struct platform_device *pdev) 186 { 187 struct arch_timer_mem_frame *frame, *best_frame = NULL; 188 struct arch_timer *at = platform_get_drvdata(pdev); 189 void __iomem *cntctlbase; 190 u32 cnttidr; 191 192 cntctlbase = ioremap(at->gt_block->cntctlbase, at->gt_block->size); 193 if (!cntctlbase) { 194 dev_err(&pdev->dev, "Can't map CNTCTLBase @ %pa\n", 195 &at->gt_block->cntctlbase); 196 return NULL; 197 } 198 199 cnttidr = readl_relaxed(cntctlbase + CNTTIDR); 200 201 /* 202 * Try to find a virtual capable frame. Otherwise fall back to a 203 * physical capable frame. 204 */ 205 for (int i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) { 206 u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT | 207 CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT; 208 209 frame = &at->gt_block->frame[i]; 210 if (!frame->valid) 211 continue; 212 213 /* Try enabling everything, and see what sticks */ 214 writel_relaxed(cntacr, cntctlbase + CNTACR(i)); 215 cntacr = readl_relaxed(cntctlbase + CNTACR(i)); 216 217 /* Pick a suitable frame for which we have an IRQ */ 218 if ((cnttidr & CNTTIDR_VIRT(i)) && 219 !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT)) && 220 frame->virt_irq) { 221 best_frame = frame; 222 at->access = VIRT_ACCESS; 223 break; 224 } 225 226 if ((~cntacr & (CNTACR_RWPT | CNTACR_RPCT)) || 227 !frame->phys_irq) 228 continue; 229 230 at->access = PHYS_ACCESS; 231 best_frame = frame; 232 } 233 234 iounmap(cntctlbase); 235 236 return best_frame; 237 } 238 239 static void arch_timer_mmio_setup(struct arch_timer *at, int irq) 240 { 241 at->evt = (struct clock_event_device) { 242 .features = (CLOCK_EVT_FEAT_ONESHOT | 243 CLOCK_EVT_FEAT_DYNIRQ), 244 .name = "arch_mem_timer", 245 .rating = 400, 246 .cpumask = cpu_possible_mask, 247 .irq = irq, 248 .set_next_event = arch_timer_mmio_set_next_event, 249 .set_state_oneshot_stopped = arch_timer_mmio_shutdown, 250 .set_state_shutdown = arch_timer_mmio_shutdown, 251 }; 252 253 at->evt.set_state_shutdown(&at->evt); 254 255 clockevents_config_and_register(&at->evt, at->rate, 0xf, 256 (unsigned long)CLOCKSOURCE_MASK(56)); 257 258 enable_irq(at->evt.irq); 259 } 260 261 static int arch_timer_mmio_frame_register(struct platform_device *pdev, 262 struct arch_timer_mem_frame *frame) 263 { 264 struct arch_timer *at = platform_get_drvdata(pdev); 265 struct device_node *np = pdev->dev.of_node; 266 int ret, irq; 267 u32 rate; 268 269 if (!devm_request_mem_region(&pdev->dev, frame->cntbase, frame->size, 270 "arch_mem_timer")) 271 return -EBUSY; 272 273 at->base = devm_ioremap(&pdev->dev, frame->cntbase, frame->size); 274 if (!at->base) { 275 dev_err(&pdev->dev, "Can't map frame's registers\n"); 276 return -ENXIO; 277 } 278 279 /* 280 * Allow "clock-frequency" to override the probed rate. If neither 281 * lead to something useful, use the CPU timer frequency as the 282 * fallback. The nice thing about that last point is that we woudn't 283 * made it here if we didn't have a valid frequency. 284 */ 285 rate = readl_relaxed(at->base + CNTFRQ); 286 287 if (!np || of_property_read_u32(np, "clock-frequency", &at->rate)) 288 at->rate = rate; 289 290 if (!at->rate) 291 at->rate = arch_timer_get_rate(); 292 293 irq = at->access == VIRT_ACCESS ? frame->virt_irq : frame->phys_irq; 294 ret = devm_request_irq(&pdev->dev, irq, arch_timer_mmio_handler, 295 IRQF_TIMER | IRQF_NO_AUTOEN, "arch_mem_timer", 296 &at->evt); 297 if (ret) { 298 dev_err(&pdev->dev, "Failed to request mem timer irq\n"); 299 return ret; 300 } 301 302 /* Afer this point, we're not allowed to fail anymore */ 303 arch_timer_mmio_setup(at, irq); 304 return 0; 305 } 306 307 static int of_populate_gt_block(struct platform_device *pdev, 308 struct arch_timer *at) 309 { 310 struct resource res; 311 312 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) 313 return -EINVAL; 314 315 at->gt_block->cntctlbase = res.start; 316 at->gt_block->size = resource_size(&res); 317 318 for_each_available_child_of_node_scoped(pdev->dev.of_node, frame_node) { 319 struct arch_timer_mem_frame *frame; 320 u32 n; 321 322 if (of_property_read_u32(frame_node, "frame-number", &n)) { 323 dev_err(&pdev->dev, FW_BUG "Missing frame-number\n"); 324 return -EINVAL; 325 } 326 if (n >= ARCH_TIMER_MEM_MAX_FRAMES) { 327 dev_err(&pdev->dev, 328 FW_BUG "Wrong frame-number, only 0-%u are permitted\n", 329 ARCH_TIMER_MEM_MAX_FRAMES - 1); 330 return -EINVAL; 331 } 332 333 frame = &at->gt_block->frame[n]; 334 335 if (frame->valid) { 336 dev_err(&pdev->dev, FW_BUG "Duplicated frame-number\n"); 337 return -EINVAL; 338 } 339 340 if (of_address_to_resource(frame_node, 0, &res)) 341 return -EINVAL; 342 343 frame->cntbase = res.start; 344 frame->size = resource_size(&res); 345 346 frame->phys_irq = irq_of_parse_and_map(frame_node, 0); 347 frame->virt_irq = irq_of_parse_and_map(frame_node, 1); 348 349 frame->valid = true; 350 } 351 352 return 0; 353 } 354 355 static int arch_timer_mmio_probe(struct platform_device *pdev) 356 { 357 struct arch_timer_mem_frame *frame; 358 struct arch_timer *at; 359 struct device_node *np; 360 int ret; 361 362 np = pdev->dev.of_node; 363 364 at = devm_kmalloc(&pdev->dev, sizeof(*at), GFP_KERNEL | __GFP_ZERO); 365 if (!at) 366 return -ENOMEM; 367 368 if (np) { 369 at->gt_block = devm_kmalloc(&pdev->dev, sizeof(*at->gt_block), 370 GFP_KERNEL | __GFP_ZERO); 371 if (!at->gt_block) 372 return -ENOMEM; 373 ret = of_populate_gt_block(pdev, at); 374 if (ret) 375 return ret; 376 } else { 377 at->gt_block = dev_get_platdata(&pdev->dev); 378 } 379 380 platform_set_drvdata(pdev, at); 381 382 frame = find_best_frame(pdev); 383 if (!frame) { 384 dev_err(&pdev->dev, 385 "Unable to find a suitable frame in timer @ %pa\n", 386 &at->gt_block->cntctlbase); 387 return -EINVAL; 388 } 389 390 ret = arch_timer_mmio_frame_register(pdev, frame); 391 if (!ret) 392 dev_info(&pdev->dev, 393 "mmio timer running at %lu.%02luMHz (%s)\n", 394 (unsigned long)at->rate / 1000000, 395 (unsigned long)(at->rate / 10000) % 100, 396 at->access == VIRT_ACCESS ? "virt" : "phys"); 397 398 return ret; 399 } 400 401 static const struct of_device_id arch_timer_mmio_of_table[] = { 402 { .compatible = "arm,armv7-timer-mem", }, 403 {} 404 }; 405 406 static struct platform_driver arch_timer_mmio_drv = { 407 .driver = { 408 .name = "arch-timer-mmio", 409 .of_match_table = arch_timer_mmio_of_table, 410 }, 411 .probe = arch_timer_mmio_probe, 412 }; 413 builtin_platform_driver(arch_timer_mmio_drv); 414 415 static struct platform_driver arch_timer_mmio_acpi_drv = { 416 .driver = { 417 .name = "gtdt-arm-mmio-timer", 418 }, 419 .probe = arch_timer_mmio_probe, 420 }; 421 builtin_platform_driver(arch_timer_mmio_acpi_drv); 422