1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com) 4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 5 */ 6 7 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be 8 * programmed to go from @count to @limit and optionally interrupt. 9 * We've designated TIMER0 for clockevents and TIMER1 for clocksource 10 * 11 * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP) 12 * which are suitable for UP and SMP based clocksources respectively 13 */ 14 15 #include <linux/interrupt.h> 16 #include <linux/clk.h> 17 #include <linux/clk-provider.h> 18 #include <linux/clocksource.h> 19 #include <linux/clockchips.h> 20 #include <linux/cpu.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/sched_clock.h> 24 25 #include <soc/arc/timers.h> 26 #include <soc/arc/mcip.h> 27 28 29 static unsigned long arc_timer_freq; 30 31 static int noinline arc_get_timer_clk(struct device_node *node) 32 { 33 struct clk *clk; 34 int ret; 35 36 clk = of_clk_get(node, 0); 37 if (IS_ERR(clk)) { 38 pr_err("timer missing clk\n"); 39 return PTR_ERR(clk); 40 } 41 42 ret = clk_prepare_enable(clk); 43 if (ret) { 44 pr_err("Couldn't enable parent clk\n"); 45 return ret; 46 } 47 48 arc_timer_freq = clk_get_rate(clk); 49 50 return 0; 51 } 52 53 /********** Clock Source Device *********/ 54 55 #ifdef CONFIG_ARC_TIMERS_64BIT 56 57 static u64 arc_read_gfrc(struct clocksource *cs) 58 { 59 unsigned long flags; 60 u32 l, h; 61 62 /* 63 * From a programming model pov, there seems to be just one instance of 64 * MCIP_CMD/MCIP_READBACK however micro-architecturally there's 65 * an instance PER ARC CORE (not per cluster), and there are dedicated 66 * hardware decode logic (per core) inside ARConnect to handle 67 * simultaneous read/write accesses from cores via those two registers. 68 * So several concurrent commands to ARConnect are OK if they are 69 * trying to access two different sub-components (like GFRC, 70 * inter-core interrupt, etc...). HW also supports simultaneously 71 * accessing GFRC by multiple cores. 72 * That's why it is safe to disable hard interrupts on the local CPU 73 * before access to GFRC instead of taking global MCIP spinlock 74 * defined in arch/arc/kernel/mcip.c 75 */ 76 local_irq_save(flags); 77 78 __mcip_cmd(CMD_GFRC_READ_LO, 0); 79 l = read_aux_reg(ARC_REG_MCIP_READBACK); 80 81 __mcip_cmd(CMD_GFRC_READ_HI, 0); 82 h = read_aux_reg(ARC_REG_MCIP_READBACK); 83 84 local_irq_restore(flags); 85 86 return (((u64)h) << 32) | l; 87 } 88 89 static notrace u64 arc_gfrc_clock_read(void) 90 { 91 return arc_read_gfrc(NULL); 92 } 93 94 static struct clocksource arc_counter_gfrc = { 95 .name = "ARConnect GFRC", 96 .rating = 400, 97 .read = arc_read_gfrc, 98 .mask = CLOCKSOURCE_MASK(64), 99 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 100 }; 101 102 static int __init arc_cs_setup_gfrc(struct device_node *node) 103 { 104 struct mcip_bcr mp; 105 int ret; 106 107 READ_BCR(ARC_REG_MCIP_BCR, mp); 108 if (!mp.gfrc) { 109 pr_warn("Global-64-bit-Ctr clocksource not detected\n"); 110 return -ENXIO; 111 } 112 113 ret = arc_get_timer_clk(node); 114 if (ret) 115 return ret; 116 117 sched_clock_register(arc_gfrc_clock_read, 64, arc_timer_freq); 118 119 return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq); 120 } 121 TIMER_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc); 122 123 #define AUX_RTC_CTRL 0x103 124 #define AUX_RTC_LOW 0x104 125 #define AUX_RTC_HIGH 0x105 126 127 static u64 arc_read_rtc(struct clocksource *cs) 128 { 129 unsigned long status; 130 u32 l, h; 131 132 /* 133 * hardware has an internal state machine which tracks readout of 134 * low/high and updates the CTRL.status if 135 * - interrupt/exception taken between the two reads 136 * - high increments after low has been read 137 */ 138 do { 139 l = read_aux_reg(AUX_RTC_LOW); 140 h = read_aux_reg(AUX_RTC_HIGH); 141 status = read_aux_reg(AUX_RTC_CTRL); 142 } while (!(status & _BITUL(31))); 143 144 return (((u64)h) << 32) | l; 145 } 146 147 static notrace u64 arc_rtc_clock_read(void) 148 { 149 return arc_read_rtc(NULL); 150 } 151 152 static struct clocksource arc_counter_rtc = { 153 .name = "ARCv2 RTC", 154 .rating = 350, 155 .read = arc_read_rtc, 156 .mask = CLOCKSOURCE_MASK(64), 157 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 158 }; 159 160 static int __init arc_cs_setup_rtc(struct device_node *node) 161 { 162 struct bcr_timer timer; 163 int ret; 164 165 READ_BCR(ARC_REG_TIMERS_BCR, timer); 166 if (!timer.rtc) { 167 pr_warn("Local-64-bit-Ctr clocksource not detected\n"); 168 return -ENXIO; 169 } 170 171 /* Local to CPU hence not usable in SMP */ 172 if (IS_ENABLED(CONFIG_SMP)) { 173 pr_warn("Local-64-bit-Ctr not usable in SMP\n"); 174 return -EINVAL; 175 } 176 177 ret = arc_get_timer_clk(node); 178 if (ret) 179 return ret; 180 181 write_aux_reg(AUX_RTC_CTRL, 1); 182 183 sched_clock_register(arc_rtc_clock_read, 64, arc_timer_freq); 184 185 return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq); 186 } 187 TIMER_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc); 188 189 #endif 190 191 /* 192 * 32bit TIMER1 to keep counting monotonically and wraparound 193 */ 194 195 static u64 arc_read_timer1(struct clocksource *cs) 196 { 197 return (u64) read_aux_reg(ARC_REG_TIMER1_CNT); 198 } 199 200 static notrace u64 arc_timer1_clock_read(void) 201 { 202 return arc_read_timer1(NULL); 203 } 204 205 static struct clocksource arc_counter_timer1 = { 206 .name = "ARC Timer1", 207 .rating = 300, 208 .read = arc_read_timer1, 209 .mask = CLOCKSOURCE_MASK(32), 210 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 211 }; 212 213 static int __init arc_cs_setup_timer1(struct device_node *node) 214 { 215 int ret; 216 217 /* Local to CPU hence not usable in SMP */ 218 if (IS_ENABLED(CONFIG_SMP)) 219 return -EINVAL; 220 221 ret = arc_get_timer_clk(node); 222 if (ret) 223 return ret; 224 225 write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX); 226 write_aux_reg(ARC_REG_TIMER1_CNT, 0); 227 write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); 228 229 sched_clock_register(arc_timer1_clock_read, 32, arc_timer_freq); 230 231 return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq); 232 } 233 234 /********** Clock Event Device *********/ 235 236 static int arc_timer_irq; 237 238 /* 239 * Arm the timer to interrupt after @cycles 240 * The distinction for oneshot/periodic is done in arc_event_timer_ack() below 241 */ 242 static void arc_timer_event_setup(unsigned int cycles) 243 { 244 write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles); 245 write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ 246 247 write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); 248 } 249 250 251 static int arc_clkevent_set_next_event(unsigned long delta, 252 struct clock_event_device *dev) 253 { 254 arc_timer_event_setup(delta); 255 return 0; 256 } 257 258 static int arc_clkevent_set_periodic(struct clock_event_device *dev) 259 { 260 /* 261 * At X Hz, 1 sec = 1000ms -> X cycles; 262 * 10ms -> X / 100 cycles 263 */ 264 arc_timer_event_setup(arc_timer_freq / HZ); 265 return 0; 266 } 267 268 static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = { 269 .name = "ARC Timer0", 270 .features = CLOCK_EVT_FEAT_ONESHOT | 271 CLOCK_EVT_FEAT_PERIODIC, 272 .rating = 300, 273 .set_next_event = arc_clkevent_set_next_event, 274 .set_state_periodic = arc_clkevent_set_periodic, 275 }; 276 277 static irqreturn_t timer_irq_handler(int irq, void *dev_id) 278 { 279 /* 280 * Note that generic IRQ core could have passed @evt for @dev_id if 281 * irq_set_chip_and_handler() asked for handle_percpu_devid_irq() 282 */ 283 struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); 284 int irq_reenable = clockevent_state_periodic(evt); 285 286 /* 287 * 1. ACK the interrupt 288 * - For ARC700, any write to CTRL reg ACKs it, so just rewrite 289 * Count when [N]ot [H]alted bit. 290 * - For HS3x, it is a bit subtle. On taken count-down interrupt, 291 * IP bit [3] is set, which needs to be cleared for ACK'ing. 292 * The write below can only update the other two bits, hence 293 * explicitly clears IP bit 294 * 2. Re-arm interrupt if periodic by writing to IE bit [0] 295 */ 296 write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); 297 298 evt->event_handler(evt); 299 300 return IRQ_HANDLED; 301 } 302 303 304 static int arc_timer_starting_cpu(unsigned int cpu) 305 { 306 struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); 307 308 evt->cpumask = cpumask_of(smp_processor_id()); 309 310 clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX); 311 enable_percpu_irq(arc_timer_irq, 0); 312 return 0; 313 } 314 315 static int arc_timer_dying_cpu(unsigned int cpu) 316 { 317 disable_percpu_irq(arc_timer_irq); 318 return 0; 319 } 320 321 /* 322 * clockevent setup for boot CPU 323 */ 324 static int __init arc_clockevent_setup(struct device_node *node) 325 { 326 struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device); 327 int ret; 328 329 arc_timer_irq = irq_of_parse_and_map(node, 0); 330 if (arc_timer_irq <= 0) { 331 pr_err("clockevent: missing irq\n"); 332 return -EINVAL; 333 } 334 335 ret = arc_get_timer_clk(node); 336 if (ret) { 337 pr_err("clockevent: missing clk\n"); 338 return ret; 339 } 340 341 /* Needs apriori irq_set_percpu_devid() done in intc map function */ 342 ret = request_percpu_irq(arc_timer_irq, timer_irq_handler, 343 "Timer0 (per-cpu-tick)", evt); 344 if (ret) { 345 pr_err("clockevent: unable to request irq\n"); 346 return ret; 347 } 348 349 ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING, 350 "clockevents/arc/timer:starting", 351 arc_timer_starting_cpu, 352 arc_timer_dying_cpu); 353 if (ret) { 354 pr_err("Failed to setup hotplug state\n"); 355 return ret; 356 } 357 return 0; 358 } 359 360 static int __init arc_of_timer_init(struct device_node *np) 361 { 362 static int init_count = 0; 363 int ret; 364 365 if (!init_count) { 366 init_count = 1; 367 ret = arc_clockevent_setup(np); 368 } else { 369 ret = arc_cs_setup_timer1(np); 370 } 371 372 return ret; 373 } 374 TIMER_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init); 375