1 /* 2 * linux/drivers/clocksource/acpi_pm.c 3 * 4 * This file contains the ACPI PM based clocksource. 5 * 6 * This code was largely moved from the i386 timer_pm.c file 7 * which was (C) Dominik Brodowski <linux@brodo.de> 2003 8 * and contained the following comments: 9 * 10 * Driver to use the Power Management Timer (PMTMR) available in some 11 * southbridges as primary timing source for the Linux kernel. 12 * 13 * Based on parts of linux/drivers/acpi/hardware/hwtimer.c, timer_pit.c, 14 * timer_hpet.c, and on Arjan van de Ven's implementation for 2.4. 15 * 16 * This file is licensed under the GPL v2. 17 */ 18 19 #include <linux/acpi_pmtmr.h> 20 #include <linux/clocksource.h> 21 #include <linux/timex.h> 22 #include <linux/errno.h> 23 #include <linux/init.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/async.h> 27 #include <asm/io.h> 28 29 /* 30 * The I/O port the PMTMR resides at. 31 * The location is detected during setup_arch(), 32 * in arch/i386/kernel/acpi/boot.c 33 */ 34 u32 pmtmr_ioport __read_mostly; 35 36 static inline u32 read_pmtmr(void) 37 { 38 /* mask the output to 24 bits */ 39 return inl(pmtmr_ioport) & ACPI_PM_MASK; 40 } 41 42 u32 acpi_pm_read_verified(void) 43 { 44 u32 v1 = 0, v2 = 0, v3 = 0; 45 46 /* 47 * It has been reported that because of various broken 48 * chipsets (ICH4, PIIX4 and PIIX4E) where the ACPI PM clock 49 * source is not latched, you must read it multiple 50 * times to ensure a safe value is read: 51 */ 52 do { 53 v1 = read_pmtmr(); 54 v2 = read_pmtmr(); 55 v3 = read_pmtmr(); 56 } while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1) 57 || (v3 > v1 && v3 < v2))); 58 59 return v2; 60 } 61 62 static cycle_t acpi_pm_read(struct clocksource *cs) 63 { 64 return (cycle_t)read_pmtmr(); 65 } 66 67 static struct clocksource clocksource_acpi_pm = { 68 .name = "acpi_pm", 69 .rating = 200, 70 .read = acpi_pm_read, 71 .mask = (cycle_t)ACPI_PM_MASK, 72 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 73 }; 74 75 76 #ifdef CONFIG_PCI 77 static int __devinitdata acpi_pm_good; 78 static int __init acpi_pm_good_setup(char *__str) 79 { 80 acpi_pm_good = 1; 81 return 1; 82 } 83 __setup("acpi_pm_good", acpi_pm_good_setup); 84 85 static cycle_t acpi_pm_read_slow(struct clocksource *cs) 86 { 87 return (cycle_t)acpi_pm_read_verified(); 88 } 89 90 static inline void acpi_pm_need_workaround(void) 91 { 92 clocksource_acpi_pm.read = acpi_pm_read_slow; 93 clocksource_acpi_pm.rating = 120; 94 } 95 96 /* 97 * PIIX4 Errata: 98 * 99 * The power management timer may return improper results when read. 100 * Although the timer value settles properly after incrementing, 101 * while incrementing there is a 3 ns window every 69.8 ns where the 102 * timer value is indeterminate (a 4.2% chance that the data will be 103 * incorrect when read). As a result, the ACPI free running count up 104 * timer specification is violated due to erroneous reads. 105 */ 106 static void __devinit acpi_pm_check_blacklist(struct pci_dev *dev) 107 { 108 if (acpi_pm_good) 109 return; 110 111 /* the bug has been fixed in PIIX4M */ 112 if (dev->revision < 3) { 113 printk(KERN_WARNING "* Found PM-Timer Bug on the chipset." 114 " Due to workarounds for a bug,\n" 115 "* this clock source is slow. Consider trying" 116 " other clock sources\n"); 117 118 acpi_pm_need_workaround(); 119 } 120 } 121 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, 122 acpi_pm_check_blacklist); 123 124 static void __devinit acpi_pm_check_graylist(struct pci_dev *dev) 125 { 126 if (acpi_pm_good) 127 return; 128 129 printk(KERN_WARNING "* The chipset may have PM-Timer Bug. Due to" 130 " workarounds for a bug,\n" 131 "* this clock source is slow. If you are sure your timer" 132 " does not have\n" 133 "* this bug, please use \"acpi_pm_good\" to disable the" 134 " workaround\n"); 135 136 acpi_pm_need_workaround(); 137 } 138 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, 139 acpi_pm_check_graylist); 140 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE, 141 acpi_pm_check_graylist); 142 #endif 143 144 #ifndef CONFIG_X86_64 145 #include <asm/mach_timer.h> 146 #define PMTMR_EXPECTED_RATE \ 147 ((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (PIT_TICK_RATE>>10)) 148 /* 149 * Some boards have the PMTMR running way too fast. We check 150 * the PMTMR rate against PIT channel 2 to catch these cases. 151 */ 152 static int verify_pmtmr_rate(void) 153 { 154 cycle_t value1, value2; 155 unsigned long count, delta; 156 157 mach_prepare_counter(); 158 value1 = clocksource_acpi_pm.read(&clocksource_acpi_pm); 159 mach_countup(&count); 160 value2 = clocksource_acpi_pm.read(&clocksource_acpi_pm); 161 delta = (value2 - value1) & ACPI_PM_MASK; 162 163 /* Check that the PMTMR delta is within 5% of what we expect */ 164 if (delta < (PMTMR_EXPECTED_RATE * 19) / 20 || 165 delta > (PMTMR_EXPECTED_RATE * 21) / 20) { 166 printk(KERN_INFO "PM-Timer running at invalid rate: %lu%% " 167 "of normal - aborting.\n", 168 100UL * delta / PMTMR_EXPECTED_RATE); 169 return -1; 170 } 171 172 return 0; 173 } 174 #else 175 #define verify_pmtmr_rate() (0) 176 #endif 177 178 /* Number of monotonicity checks to perform during initialization */ 179 #define ACPI_PM_MONOTONICITY_CHECKS 10 180 /* Number of reads we try to get two different values */ 181 #define ACPI_PM_READ_CHECKS 10000 182 183 static void __init acpi_pm_clocksource_async(void *unused, async_cookie_t cookie) 184 { 185 cycle_t value1, value2; 186 unsigned int i, j = 0; 187 188 189 /* "verify" this timing source: */ 190 for (j = 0; j < ACPI_PM_MONOTONICITY_CHECKS; j++) { 191 usleep_range(100 * j, 100 * j + 100); 192 value1 = clocksource_acpi_pm.read(&clocksource_acpi_pm); 193 for (i = 0; i < ACPI_PM_READ_CHECKS; i++) { 194 value2 = clocksource_acpi_pm.read(&clocksource_acpi_pm); 195 if (value2 == value1) 196 continue; 197 if (value2 > value1) 198 break; 199 if ((value2 < value1) && ((value2) < 0xFFF)) 200 break; 201 printk(KERN_INFO "PM-Timer had inconsistent results:" 202 " 0x%#llx, 0x%#llx - aborting.\n", 203 value1, value2); 204 pmtmr_ioport = 0; 205 return; 206 } 207 if (i == ACPI_PM_READ_CHECKS) { 208 printk(KERN_INFO "PM-Timer failed consistency check " 209 " (0x%#llx) - aborting.\n", value1); 210 pmtmr_ioport = 0; 211 return; 212 } 213 } 214 215 if (verify_pmtmr_rate() != 0){ 216 pmtmr_ioport = 0; 217 return; 218 } 219 220 clocksource_register_hz(&clocksource_acpi_pm, 221 PMTMR_TICKS_PER_SEC); 222 } 223 224 static int __init init_acpi_pm_clocksource(void) 225 { 226 if (!pmtmr_ioport) 227 return -ENODEV; 228 229 async_schedule(acpi_pm_clocksource_async, NULL); 230 return 0; 231 } 232 233 /* We use fs_initcall because we want the PCI fixups to have run 234 * but we still need to load before device_initcall 235 */ 236 fs_initcall(init_acpi_pm_clocksource); 237 238 /* 239 * Allow an override of the IOPort. Stupid BIOSes do not tell us about 240 * the PMTimer, but we might know where it is. 241 */ 242 static int __init parse_pmtmr(char *arg) 243 { 244 unsigned long base; 245 246 if (strict_strtoul(arg, 16, &base)) 247 return -EINVAL; 248 #ifdef CONFIG_X86_64 249 if (base > UINT_MAX) 250 return -ERANGE; 251 #endif 252 printk(KERN_INFO "PMTMR IOPort override: 0x%04x -> 0x%04lx\n", 253 pmtmr_ioport, base); 254 pmtmr_ioport = base; 255 256 return 1; 257 } 258 __setup("pmtmr=", parse_pmtmr); 259