13fde0e16SJolly Shah // SPDX-License-Identifier: GPL-2.0 23fde0e16SJolly Shah /* 33fde0e16SJolly Shah * Zynq UltraScale+ MPSoC Divider support 43fde0e16SJolly Shah * 53fde0e16SJolly Shah * Copyright (C) 2016-2018 Xilinx 63fde0e16SJolly Shah * 73fde0e16SJolly Shah * Adjustable divider clock implementation 83fde0e16SJolly Shah */ 93fde0e16SJolly Shah 103fde0e16SJolly Shah #include <linux/clk.h> 113fde0e16SJolly Shah #include <linux/clk-provider.h> 123fde0e16SJolly Shah #include <linux/slab.h> 133fde0e16SJolly Shah #include "clk-zynqmp.h" 143fde0e16SJolly Shah 153fde0e16SJolly Shah /* 163fde0e16SJolly Shah * DOC: basic adjustable divider clock that cannot gate 173fde0e16SJolly Shah * 183fde0e16SJolly Shah * Traits of this clock: 193fde0e16SJolly Shah * prepare - clk_prepare only ensures that parents are prepared 203fde0e16SJolly Shah * enable - clk_enable only ensures that parents are enabled 213fde0e16SJolly Shah * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor) 223fde0e16SJolly Shah * parent - fixed parent. No clk_set_parent support 233fde0e16SJolly Shah */ 243fde0e16SJolly Shah 253fde0e16SJolly Shah #define to_zynqmp_clk_divider(_hw) \ 263fde0e16SJolly Shah container_of(_hw, struct zynqmp_clk_divider, hw) 273fde0e16SJolly Shah 283fde0e16SJolly Shah #define CLK_FRAC BIT(13) /* has a fractional parent */ 293fde0e16SJolly Shah 303fde0e16SJolly Shah /** 313fde0e16SJolly Shah * struct zynqmp_clk_divider - adjustable divider clock 323fde0e16SJolly Shah * @hw: handle between common and hardware-specific interfaces 333fde0e16SJolly Shah * @flags: Hardware specific flags 34*c06e6440SMichael Tretter * @is_frac: The divider is a fractional divider 353fde0e16SJolly Shah * @clk_id: Id of clock 363fde0e16SJolly Shah * @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2) 373fde0e16SJolly Shah */ 383fde0e16SJolly Shah struct zynqmp_clk_divider { 393fde0e16SJolly Shah struct clk_hw hw; 403fde0e16SJolly Shah u8 flags; 41*c06e6440SMichael Tretter bool is_frac; 423fde0e16SJolly Shah u32 clk_id; 433fde0e16SJolly Shah u32 div_type; 443fde0e16SJolly Shah }; 453fde0e16SJolly Shah 463fde0e16SJolly Shah static inline int zynqmp_divider_get_val(unsigned long parent_rate, 473fde0e16SJolly Shah unsigned long rate) 483fde0e16SJolly Shah { 493fde0e16SJolly Shah return DIV_ROUND_CLOSEST(parent_rate, rate); 503fde0e16SJolly Shah } 513fde0e16SJolly Shah 523fde0e16SJolly Shah /** 533fde0e16SJolly Shah * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock 543fde0e16SJolly Shah * @hw: handle between common and hardware-specific interfaces 553fde0e16SJolly Shah * @parent_rate: rate of parent clock 563fde0e16SJolly Shah * 573fde0e16SJolly Shah * Return: 0 on success else error+reason 583fde0e16SJolly Shah */ 593fde0e16SJolly Shah static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, 603fde0e16SJolly Shah unsigned long parent_rate) 613fde0e16SJolly Shah { 623fde0e16SJolly Shah struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 633fde0e16SJolly Shah const char *clk_name = clk_hw_get_name(hw); 643fde0e16SJolly Shah u32 clk_id = divider->clk_id; 653fde0e16SJolly Shah u32 div_type = divider->div_type; 663fde0e16SJolly Shah u32 div, value; 673fde0e16SJolly Shah int ret; 683fde0e16SJolly Shah const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 693fde0e16SJolly Shah 703fde0e16SJolly Shah ret = eemi_ops->clock_getdivider(clk_id, &div); 713fde0e16SJolly Shah 723fde0e16SJolly Shah if (ret) 733fde0e16SJolly Shah pr_warn_once("%s() get divider failed for %s, ret = %d\n", 743fde0e16SJolly Shah __func__, clk_name, ret); 753fde0e16SJolly Shah 763fde0e16SJolly Shah if (div_type == TYPE_DIV1) 773fde0e16SJolly Shah value = div & 0xFFFF; 783fde0e16SJolly Shah else 793fde0e16SJolly Shah value = div >> 16; 803fde0e16SJolly Shah 8160d74e01SRajan Vaja if (!value) { 8260d74e01SRajan Vaja WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), 8360d74e01SRajan Vaja "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", 8460d74e01SRajan Vaja clk_name); 8560d74e01SRajan Vaja return parent_rate; 8660d74e01SRajan Vaja } 8760d74e01SRajan Vaja 883fde0e16SJolly Shah return DIV_ROUND_UP_ULL(parent_rate, value); 893fde0e16SJolly Shah } 903fde0e16SJolly Shah 913fde0e16SJolly Shah /** 923fde0e16SJolly Shah * zynqmp_clk_divider_round_rate() - Round rate of divider clock 933fde0e16SJolly Shah * @hw: handle between common and hardware-specific interfaces 943fde0e16SJolly Shah * @rate: rate of clock to be set 953fde0e16SJolly Shah * @prate: rate of parent clock 963fde0e16SJolly Shah * 973fde0e16SJolly Shah * Return: 0 on success else error+reason 983fde0e16SJolly Shah */ 993fde0e16SJolly Shah static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, 1003fde0e16SJolly Shah unsigned long rate, 1013fde0e16SJolly Shah unsigned long *prate) 1023fde0e16SJolly Shah { 1033fde0e16SJolly Shah struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 1043fde0e16SJolly Shah const char *clk_name = clk_hw_get_name(hw); 1053fde0e16SJolly Shah u32 clk_id = divider->clk_id; 1063fde0e16SJolly Shah u32 div_type = divider->div_type; 1073fde0e16SJolly Shah u32 bestdiv; 1083fde0e16SJolly Shah int ret; 1093fde0e16SJolly Shah const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 1103fde0e16SJolly Shah 1113fde0e16SJolly Shah /* if read only, just return current value */ 1123fde0e16SJolly Shah if (divider->flags & CLK_DIVIDER_READ_ONLY) { 1133fde0e16SJolly Shah ret = eemi_ops->clock_getdivider(clk_id, &bestdiv); 1143fde0e16SJolly Shah 1153fde0e16SJolly Shah if (ret) 1163fde0e16SJolly Shah pr_warn_once("%s() get divider failed for %s, ret = %d\n", 1173fde0e16SJolly Shah __func__, clk_name, ret); 1183fde0e16SJolly Shah if (div_type == TYPE_DIV1) 1193fde0e16SJolly Shah bestdiv = bestdiv & 0xFFFF; 1203fde0e16SJolly Shah else 1213fde0e16SJolly Shah bestdiv = bestdiv >> 16; 1223fde0e16SJolly Shah 1233fde0e16SJolly Shah return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); 1243fde0e16SJolly Shah } 1253fde0e16SJolly Shah 1263fde0e16SJolly Shah bestdiv = zynqmp_divider_get_val(*prate, rate); 1273fde0e16SJolly Shah 128*c06e6440SMichael Tretter if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) 1293fde0e16SJolly Shah bestdiv = rate % *prate ? 1 : bestdiv; 1303fde0e16SJolly Shah *prate = rate * bestdiv; 1313fde0e16SJolly Shah 1323fde0e16SJolly Shah return rate; 1333fde0e16SJolly Shah } 1343fde0e16SJolly Shah 1353fde0e16SJolly Shah /** 1363fde0e16SJolly Shah * zynqmp_clk_divider_set_rate() - Set rate of divider clock 1373fde0e16SJolly Shah * @hw: handle between common and hardware-specific interfaces 1383fde0e16SJolly Shah * @rate: rate of clock to be set 1393fde0e16SJolly Shah * @parent_rate: rate of parent clock 1403fde0e16SJolly Shah * 1413fde0e16SJolly Shah * Return: 0 on success else error+reason 1423fde0e16SJolly Shah */ 1433fde0e16SJolly Shah static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 1443fde0e16SJolly Shah unsigned long parent_rate) 1453fde0e16SJolly Shah { 1463fde0e16SJolly Shah struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 1473fde0e16SJolly Shah const char *clk_name = clk_hw_get_name(hw); 1483fde0e16SJolly Shah u32 clk_id = divider->clk_id; 1493fde0e16SJolly Shah u32 div_type = divider->div_type; 1503fde0e16SJolly Shah u32 value, div; 1513fde0e16SJolly Shah int ret; 1523fde0e16SJolly Shah const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 1533fde0e16SJolly Shah 1543fde0e16SJolly Shah value = zynqmp_divider_get_val(parent_rate, rate); 1553fde0e16SJolly Shah if (div_type == TYPE_DIV1) { 1563fde0e16SJolly Shah div = value & 0xFFFF; 1573fde0e16SJolly Shah div |= 0xffff << 16; 1583fde0e16SJolly Shah } else { 1593fde0e16SJolly Shah div = 0xffff; 1603fde0e16SJolly Shah div |= value << 16; 1613fde0e16SJolly Shah } 1623fde0e16SJolly Shah 1633fde0e16SJolly Shah ret = eemi_ops->clock_setdivider(clk_id, div); 1643fde0e16SJolly Shah 1653fde0e16SJolly Shah if (ret) 1663fde0e16SJolly Shah pr_warn_once("%s() set divider failed for %s, ret = %d\n", 1673fde0e16SJolly Shah __func__, clk_name, ret); 1683fde0e16SJolly Shah 1693fde0e16SJolly Shah return ret; 1703fde0e16SJolly Shah } 1713fde0e16SJolly Shah 1723fde0e16SJolly Shah static const struct clk_ops zynqmp_clk_divider_ops = { 1733fde0e16SJolly Shah .recalc_rate = zynqmp_clk_divider_recalc_rate, 1743fde0e16SJolly Shah .round_rate = zynqmp_clk_divider_round_rate, 1753fde0e16SJolly Shah .set_rate = zynqmp_clk_divider_set_rate, 1763fde0e16SJolly Shah }; 1773fde0e16SJolly Shah 1783fde0e16SJolly Shah /** 1793fde0e16SJolly Shah * zynqmp_clk_register_divider() - Register a divider clock 1803fde0e16SJolly Shah * @name: Name of this clock 1813fde0e16SJolly Shah * @clk_id: Id of clock 1823fde0e16SJolly Shah * @parents: Name of this clock's parents 1833fde0e16SJolly Shah * @num_parents: Number of parents 1843fde0e16SJolly Shah * @nodes: Clock topology node 1853fde0e16SJolly Shah * 1863fde0e16SJolly Shah * Return: clock hardware to registered clock divider 1873fde0e16SJolly Shah */ 1883fde0e16SJolly Shah struct clk_hw *zynqmp_clk_register_divider(const char *name, 1893fde0e16SJolly Shah u32 clk_id, 1903fde0e16SJolly Shah const char * const *parents, 1913fde0e16SJolly Shah u8 num_parents, 1923fde0e16SJolly Shah const struct clock_topology *nodes) 1933fde0e16SJolly Shah { 1943fde0e16SJolly Shah struct zynqmp_clk_divider *div; 1953fde0e16SJolly Shah struct clk_hw *hw; 1963fde0e16SJolly Shah struct clk_init_data init; 1973fde0e16SJolly Shah int ret; 1983fde0e16SJolly Shah 1993fde0e16SJolly Shah /* allocate the divider */ 2003fde0e16SJolly Shah div = kzalloc(sizeof(*div), GFP_KERNEL); 2013fde0e16SJolly Shah if (!div) 2023fde0e16SJolly Shah return ERR_PTR(-ENOMEM); 2033fde0e16SJolly Shah 2043fde0e16SJolly Shah init.name = name; 2053fde0e16SJolly Shah init.ops = &zynqmp_clk_divider_ops; 206*c06e6440SMichael Tretter /* CLK_FRAC is not defined in the common clk framework */ 207*c06e6440SMichael Tretter init.flags = nodes->flag & ~CLK_FRAC; 2083fde0e16SJolly Shah init.parent_names = parents; 2093fde0e16SJolly Shah init.num_parents = 1; 2103fde0e16SJolly Shah 2113fde0e16SJolly Shah /* struct clk_divider assignments */ 212*c06e6440SMichael Tretter div->is_frac = !!(nodes->flag & CLK_FRAC); 2133fde0e16SJolly Shah div->flags = nodes->type_flag; 2143fde0e16SJolly Shah div->hw.init = &init; 2153fde0e16SJolly Shah div->clk_id = clk_id; 2163fde0e16SJolly Shah div->div_type = nodes->type; 2173fde0e16SJolly Shah 2183fde0e16SJolly Shah hw = &div->hw; 2193fde0e16SJolly Shah ret = clk_hw_register(NULL, hw); 2203fde0e16SJolly Shah if (ret) { 2213fde0e16SJolly Shah kfree(div); 2223fde0e16SJolly Shah hw = ERR_PTR(ret); 2233fde0e16SJolly Shah } 2243fde0e16SJolly Shah 2253fde0e16SJolly Shah return hw; 2263fde0e16SJolly Shah } 227