13fde0e16SJolly Shah // SPDX-License-Identifier: GPL-2.0 23fde0e16SJolly Shah /* 33fde0e16SJolly Shah * Zynq UltraScale+ MPSoC Divider support 43fde0e16SJolly Shah * 53fde0e16SJolly Shah * Copyright (C) 2016-2018 Xilinx 63fde0e16SJolly Shah * 73fde0e16SJolly Shah * Adjustable divider clock implementation 83fde0e16SJolly Shah */ 93fde0e16SJolly Shah 103fde0e16SJolly Shah #include <linux/clk.h> 113fde0e16SJolly Shah #include <linux/clk-provider.h> 123fde0e16SJolly Shah #include <linux/slab.h> 133fde0e16SJolly Shah #include "clk-zynqmp.h" 143fde0e16SJolly Shah 153fde0e16SJolly Shah /* 163fde0e16SJolly Shah * DOC: basic adjustable divider clock that cannot gate 173fde0e16SJolly Shah * 183fde0e16SJolly Shah * Traits of this clock: 193fde0e16SJolly Shah * prepare - clk_prepare only ensures that parents are prepared 203fde0e16SJolly Shah * enable - clk_enable only ensures that parents are enabled 213fde0e16SJolly Shah * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor) 223fde0e16SJolly Shah * parent - fixed parent. No clk_set_parent support 233fde0e16SJolly Shah */ 243fde0e16SJolly Shah 253fde0e16SJolly Shah #define to_zynqmp_clk_divider(_hw) \ 263fde0e16SJolly Shah container_of(_hw, struct zynqmp_clk_divider, hw) 273fde0e16SJolly Shah 283fde0e16SJolly Shah #define CLK_FRAC BIT(13) /* has a fractional parent */ 293fde0e16SJolly Shah 303fde0e16SJolly Shah /** 313fde0e16SJolly Shah * struct zynqmp_clk_divider - adjustable divider clock 323fde0e16SJolly Shah * @hw: handle between common and hardware-specific interfaces 333fde0e16SJolly Shah * @flags: Hardware specific flags 34c06e6440SMichael Tretter * @is_frac: The divider is a fractional divider 353fde0e16SJolly Shah * @clk_id: Id of clock 363fde0e16SJolly Shah * @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2) 373fde0e16SJolly Shah */ 383fde0e16SJolly Shah struct zynqmp_clk_divider { 393fde0e16SJolly Shah struct clk_hw hw; 403fde0e16SJolly Shah u8 flags; 41c06e6440SMichael Tretter bool is_frac; 423fde0e16SJolly Shah u32 clk_id; 433fde0e16SJolly Shah u32 div_type; 44e942171bSRajan Vaja u16 max_div; 453fde0e16SJolly Shah }; 463fde0e16SJolly Shah 473fde0e16SJolly Shah static inline int zynqmp_divider_get_val(unsigned long parent_rate, 483fde0e16SJolly Shah unsigned long rate) 493fde0e16SJolly Shah { 503fde0e16SJolly Shah return DIV_ROUND_CLOSEST(parent_rate, rate); 513fde0e16SJolly Shah } 523fde0e16SJolly Shah 533fde0e16SJolly Shah /** 543fde0e16SJolly Shah * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock 553fde0e16SJolly Shah * @hw: handle between common and hardware-specific interfaces 563fde0e16SJolly Shah * @parent_rate: rate of parent clock 573fde0e16SJolly Shah * 583fde0e16SJolly Shah * Return: 0 on success else error+reason 593fde0e16SJolly Shah */ 603fde0e16SJolly Shah static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, 613fde0e16SJolly Shah unsigned long parent_rate) 623fde0e16SJolly Shah { 633fde0e16SJolly Shah struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 643fde0e16SJolly Shah const char *clk_name = clk_hw_get_name(hw); 653fde0e16SJolly Shah u32 clk_id = divider->clk_id; 663fde0e16SJolly Shah u32 div_type = divider->div_type; 673fde0e16SJolly Shah u32 div, value; 683fde0e16SJolly Shah int ret; 693fde0e16SJolly Shah const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 703fde0e16SJolly Shah 713fde0e16SJolly Shah ret = eemi_ops->clock_getdivider(clk_id, &div); 723fde0e16SJolly Shah 733fde0e16SJolly Shah if (ret) 743fde0e16SJolly Shah pr_warn_once("%s() get divider failed for %s, ret = %d\n", 753fde0e16SJolly Shah __func__, clk_name, ret); 763fde0e16SJolly Shah 773fde0e16SJolly Shah if (div_type == TYPE_DIV1) 783fde0e16SJolly Shah value = div & 0xFFFF; 793fde0e16SJolly Shah else 803fde0e16SJolly Shah value = div >> 16; 813fde0e16SJolly Shah 8260d74e01SRajan Vaja if (!value) { 8360d74e01SRajan Vaja WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), 8460d74e01SRajan Vaja "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", 8560d74e01SRajan Vaja clk_name); 8660d74e01SRajan Vaja return parent_rate; 8760d74e01SRajan Vaja } 8860d74e01SRajan Vaja 893fde0e16SJolly Shah return DIV_ROUND_UP_ULL(parent_rate, value); 903fde0e16SJolly Shah } 913fde0e16SJolly Shah 92*4ebd92d2SRajan Vaja static void zynqmp_get_divider2_val(struct clk_hw *hw, 93*4ebd92d2SRajan Vaja unsigned long rate, 94*4ebd92d2SRajan Vaja unsigned long parent_rate, 95*4ebd92d2SRajan Vaja struct zynqmp_clk_divider *divider, 96*4ebd92d2SRajan Vaja int *bestdiv) 97*4ebd92d2SRajan Vaja { 98*4ebd92d2SRajan Vaja int div1; 99*4ebd92d2SRajan Vaja int div2; 100*4ebd92d2SRajan Vaja long error = LONG_MAX; 101*4ebd92d2SRajan Vaja struct clk_hw *parent_hw = clk_hw_get_parent(hw); 102*4ebd92d2SRajan Vaja struct zynqmp_clk_divider *pdivider = to_zynqmp_clk_divider(parent_hw); 103*4ebd92d2SRajan Vaja 104*4ebd92d2SRajan Vaja if (!pdivider) 105*4ebd92d2SRajan Vaja return; 106*4ebd92d2SRajan Vaja 107*4ebd92d2SRajan Vaja *bestdiv = 1; 108*4ebd92d2SRajan Vaja for (div1 = 1; div1 <= pdivider->max_div;) { 109*4ebd92d2SRajan Vaja for (div2 = 1; div2 <= divider->max_div;) { 110*4ebd92d2SRajan Vaja long new_error = ((parent_rate / div1) / div2) - rate; 111*4ebd92d2SRajan Vaja 112*4ebd92d2SRajan Vaja if (abs(new_error) < abs(error)) { 113*4ebd92d2SRajan Vaja *bestdiv = div2; 114*4ebd92d2SRajan Vaja error = new_error; 115*4ebd92d2SRajan Vaja } 116*4ebd92d2SRajan Vaja if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 117*4ebd92d2SRajan Vaja div2 = div2 << 1; 118*4ebd92d2SRajan Vaja else 119*4ebd92d2SRajan Vaja div2++; 120*4ebd92d2SRajan Vaja } 121*4ebd92d2SRajan Vaja if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO) 122*4ebd92d2SRajan Vaja div1 = div1 << 1; 123*4ebd92d2SRajan Vaja else 124*4ebd92d2SRajan Vaja div1++; 125*4ebd92d2SRajan Vaja } 126*4ebd92d2SRajan Vaja } 127*4ebd92d2SRajan Vaja 1283fde0e16SJolly Shah /** 1293fde0e16SJolly Shah * zynqmp_clk_divider_round_rate() - Round rate of divider clock 1303fde0e16SJolly Shah * @hw: handle between common and hardware-specific interfaces 1313fde0e16SJolly Shah * @rate: rate of clock to be set 1323fde0e16SJolly Shah * @prate: rate of parent clock 1333fde0e16SJolly Shah * 1343fde0e16SJolly Shah * Return: 0 on success else error+reason 1353fde0e16SJolly Shah */ 1363fde0e16SJolly Shah static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, 1373fde0e16SJolly Shah unsigned long rate, 1383fde0e16SJolly Shah unsigned long *prate) 1393fde0e16SJolly Shah { 1403fde0e16SJolly Shah struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 1413fde0e16SJolly Shah const char *clk_name = clk_hw_get_name(hw); 1423fde0e16SJolly Shah u32 clk_id = divider->clk_id; 1433fde0e16SJolly Shah u32 div_type = divider->div_type; 1443fde0e16SJolly Shah u32 bestdiv; 1453fde0e16SJolly Shah int ret; 1463fde0e16SJolly Shah const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 1473fde0e16SJolly Shah 1483fde0e16SJolly Shah /* if read only, just return current value */ 1493fde0e16SJolly Shah if (divider->flags & CLK_DIVIDER_READ_ONLY) { 1503fde0e16SJolly Shah ret = eemi_ops->clock_getdivider(clk_id, &bestdiv); 1513fde0e16SJolly Shah 1523fde0e16SJolly Shah if (ret) 1533fde0e16SJolly Shah pr_warn_once("%s() get divider failed for %s, ret = %d\n", 1543fde0e16SJolly Shah __func__, clk_name, ret); 1553fde0e16SJolly Shah if (div_type == TYPE_DIV1) 1563fde0e16SJolly Shah bestdiv = bestdiv & 0xFFFF; 1573fde0e16SJolly Shah else 1583fde0e16SJolly Shah bestdiv = bestdiv >> 16; 1593fde0e16SJolly Shah 1603fde0e16SJolly Shah return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); 1613fde0e16SJolly Shah } 1623fde0e16SJolly Shah 1633fde0e16SJolly Shah bestdiv = zynqmp_divider_get_val(*prate, rate); 1643fde0e16SJolly Shah 165*4ebd92d2SRajan Vaja /* 166*4ebd92d2SRajan Vaja * In case of two divisors, compute best divider values and return 167*4ebd92d2SRajan Vaja * divider2 value based on compute value. div1 will be automatically 168*4ebd92d2SRajan Vaja * set to optimum based on required total divider value. 169*4ebd92d2SRajan Vaja */ 170*4ebd92d2SRajan Vaja if (div_type == TYPE_DIV2 && 171*4ebd92d2SRajan Vaja (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { 172*4ebd92d2SRajan Vaja zynqmp_get_divider2_val(hw, rate, *prate, divider, &bestdiv); 173*4ebd92d2SRajan Vaja } 174*4ebd92d2SRajan Vaja 175c06e6440SMichael Tretter if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) 1763fde0e16SJolly Shah bestdiv = rate % *prate ? 1 : bestdiv; 1773fde0e16SJolly Shah *prate = rate * bestdiv; 1783fde0e16SJolly Shah 1793fde0e16SJolly Shah return rate; 1803fde0e16SJolly Shah } 1813fde0e16SJolly Shah 1823fde0e16SJolly Shah /** 1833fde0e16SJolly Shah * zynqmp_clk_divider_set_rate() - Set rate of divider clock 1843fde0e16SJolly Shah * @hw: handle between common and hardware-specific interfaces 1853fde0e16SJolly Shah * @rate: rate of clock to be set 1863fde0e16SJolly Shah * @parent_rate: rate of parent clock 1873fde0e16SJolly Shah * 1883fde0e16SJolly Shah * Return: 0 on success else error+reason 1893fde0e16SJolly Shah */ 1903fde0e16SJolly Shah static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 1913fde0e16SJolly Shah unsigned long parent_rate) 1923fde0e16SJolly Shah { 1933fde0e16SJolly Shah struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 1943fde0e16SJolly Shah const char *clk_name = clk_hw_get_name(hw); 1953fde0e16SJolly Shah u32 clk_id = divider->clk_id; 1963fde0e16SJolly Shah u32 div_type = divider->div_type; 1973fde0e16SJolly Shah u32 value, div; 1983fde0e16SJolly Shah int ret; 1993fde0e16SJolly Shah const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 2003fde0e16SJolly Shah 2013fde0e16SJolly Shah value = zynqmp_divider_get_val(parent_rate, rate); 2023fde0e16SJolly Shah if (div_type == TYPE_DIV1) { 2033fde0e16SJolly Shah div = value & 0xFFFF; 2043fde0e16SJolly Shah div |= 0xffff << 16; 2053fde0e16SJolly Shah } else { 2063fde0e16SJolly Shah div = 0xffff; 2073fde0e16SJolly Shah div |= value << 16; 2083fde0e16SJolly Shah } 2093fde0e16SJolly Shah 2103fde0e16SJolly Shah ret = eemi_ops->clock_setdivider(clk_id, div); 2113fde0e16SJolly Shah 2123fde0e16SJolly Shah if (ret) 2133fde0e16SJolly Shah pr_warn_once("%s() set divider failed for %s, ret = %d\n", 2143fde0e16SJolly Shah __func__, clk_name, ret); 2153fde0e16SJolly Shah 2163fde0e16SJolly Shah return ret; 2173fde0e16SJolly Shah } 2183fde0e16SJolly Shah 2193fde0e16SJolly Shah static const struct clk_ops zynqmp_clk_divider_ops = { 2203fde0e16SJolly Shah .recalc_rate = zynqmp_clk_divider_recalc_rate, 2213fde0e16SJolly Shah .round_rate = zynqmp_clk_divider_round_rate, 2223fde0e16SJolly Shah .set_rate = zynqmp_clk_divider_set_rate, 2233fde0e16SJolly Shah }; 2243fde0e16SJolly Shah 2253fde0e16SJolly Shah /** 226e942171bSRajan Vaja * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware. 227e942171bSRajan Vaja * @clk_id: Id of clock 228e942171bSRajan Vaja * @type: Divider type 229e942171bSRajan Vaja * 230e942171bSRajan Vaja * Return: Maximum divisor of a clock if query data is successful 231e942171bSRajan Vaja * U16_MAX in case of query data is not success 232e942171bSRajan Vaja */ 233e942171bSRajan Vaja u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) 234e942171bSRajan Vaja { 235e942171bSRajan Vaja const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 236e942171bSRajan Vaja struct zynqmp_pm_query_data qdata = {0}; 237e942171bSRajan Vaja u32 ret_payload[PAYLOAD_ARG_CNT]; 238e942171bSRajan Vaja int ret; 239e942171bSRajan Vaja 240e942171bSRajan Vaja qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR; 241e942171bSRajan Vaja qdata.arg1 = clk_id; 242e942171bSRajan Vaja qdata.arg2 = type; 243e942171bSRajan Vaja ret = eemi_ops->query_data(qdata, ret_payload); 244e942171bSRajan Vaja /* 245e942171bSRajan Vaja * To maintain backward compatibility return maximum possible value 246e942171bSRajan Vaja * (0xFFFF) if query for max divisor is not successful. 247e942171bSRajan Vaja */ 248e942171bSRajan Vaja if (ret) 249e942171bSRajan Vaja return U16_MAX; 250e942171bSRajan Vaja 251e942171bSRajan Vaja return ret_payload[1]; 252e942171bSRajan Vaja } 253e942171bSRajan Vaja 254e942171bSRajan Vaja /** 2553fde0e16SJolly Shah * zynqmp_clk_register_divider() - Register a divider clock 2563fde0e16SJolly Shah * @name: Name of this clock 2573fde0e16SJolly Shah * @clk_id: Id of clock 2583fde0e16SJolly Shah * @parents: Name of this clock's parents 2593fde0e16SJolly Shah * @num_parents: Number of parents 2603fde0e16SJolly Shah * @nodes: Clock topology node 2613fde0e16SJolly Shah * 2623fde0e16SJolly Shah * Return: clock hardware to registered clock divider 2633fde0e16SJolly Shah */ 2643fde0e16SJolly Shah struct clk_hw *zynqmp_clk_register_divider(const char *name, 2653fde0e16SJolly Shah u32 clk_id, 2663fde0e16SJolly Shah const char * const *parents, 2673fde0e16SJolly Shah u8 num_parents, 2683fde0e16SJolly Shah const struct clock_topology *nodes) 2693fde0e16SJolly Shah { 2703fde0e16SJolly Shah struct zynqmp_clk_divider *div; 2713fde0e16SJolly Shah struct clk_hw *hw; 2723fde0e16SJolly Shah struct clk_init_data init; 2733fde0e16SJolly Shah int ret; 2743fde0e16SJolly Shah 2753fde0e16SJolly Shah /* allocate the divider */ 2763fde0e16SJolly Shah div = kzalloc(sizeof(*div), GFP_KERNEL); 2773fde0e16SJolly Shah if (!div) 2783fde0e16SJolly Shah return ERR_PTR(-ENOMEM); 2793fde0e16SJolly Shah 2803fde0e16SJolly Shah init.name = name; 2813fde0e16SJolly Shah init.ops = &zynqmp_clk_divider_ops; 282c06e6440SMichael Tretter /* CLK_FRAC is not defined in the common clk framework */ 283c06e6440SMichael Tretter init.flags = nodes->flag & ~CLK_FRAC; 2843fde0e16SJolly Shah init.parent_names = parents; 2853fde0e16SJolly Shah init.num_parents = 1; 2863fde0e16SJolly Shah 2873fde0e16SJolly Shah /* struct clk_divider assignments */ 288c06e6440SMichael Tretter div->is_frac = !!(nodes->flag & CLK_FRAC); 2893fde0e16SJolly Shah div->flags = nodes->type_flag; 2903fde0e16SJolly Shah div->hw.init = &init; 2913fde0e16SJolly Shah div->clk_id = clk_id; 2923fde0e16SJolly Shah div->div_type = nodes->type; 2933fde0e16SJolly Shah 294e942171bSRajan Vaja /* 295e942171bSRajan Vaja * To achieve best possible rate, maximum limit of divider is required 296e942171bSRajan Vaja * while computation. 297e942171bSRajan Vaja */ 298e942171bSRajan Vaja div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type); 299e942171bSRajan Vaja 3003fde0e16SJolly Shah hw = &div->hw; 3013fde0e16SJolly Shah ret = clk_hw_register(NULL, hw); 3023fde0e16SJolly Shah if (ret) { 3033fde0e16SJolly Shah kfree(div); 3043fde0e16SJolly Shah hw = ERR_PTR(ret); 3053fde0e16SJolly Shah } 3063fde0e16SJolly Shah 3073fde0e16SJolly Shah return hw; 3083fde0e16SJolly Shah } 309