13fde0e16SJolly Shah // SPDX-License-Identifier: GPL-2.0 23fde0e16SJolly Shah /* 33fde0e16SJolly Shah * Zynq UltraScale+ MPSoC Divider support 43fde0e16SJolly Shah * 5*34bbe036STejas Patel * Copyright (C) 2016-2019 Xilinx 63fde0e16SJolly Shah * 73fde0e16SJolly Shah * Adjustable divider clock implementation 83fde0e16SJolly Shah */ 93fde0e16SJolly Shah 103fde0e16SJolly Shah #include <linux/clk.h> 113fde0e16SJolly Shah #include <linux/clk-provider.h> 123fde0e16SJolly Shah #include <linux/slab.h> 133fde0e16SJolly Shah #include "clk-zynqmp.h" 143fde0e16SJolly Shah 153fde0e16SJolly Shah /* 163fde0e16SJolly Shah * DOC: basic adjustable divider clock that cannot gate 173fde0e16SJolly Shah * 183fde0e16SJolly Shah * Traits of this clock: 193fde0e16SJolly Shah * prepare - clk_prepare only ensures that parents are prepared 203fde0e16SJolly Shah * enable - clk_enable only ensures that parents are enabled 213fde0e16SJolly Shah * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor) 223fde0e16SJolly Shah * parent - fixed parent. No clk_set_parent support 233fde0e16SJolly Shah */ 243fde0e16SJolly Shah 253fde0e16SJolly Shah #define to_zynqmp_clk_divider(_hw) \ 263fde0e16SJolly Shah container_of(_hw, struct zynqmp_clk_divider, hw) 273fde0e16SJolly Shah 283fde0e16SJolly Shah #define CLK_FRAC BIT(13) /* has a fractional parent */ 293fde0e16SJolly Shah 303fde0e16SJolly Shah /** 313fde0e16SJolly Shah * struct zynqmp_clk_divider - adjustable divider clock 323fde0e16SJolly Shah * @hw: handle between common and hardware-specific interfaces 333fde0e16SJolly Shah * @flags: Hardware specific flags 34c06e6440SMichael Tretter * @is_frac: The divider is a fractional divider 353fde0e16SJolly Shah * @clk_id: Id of clock 363fde0e16SJolly Shah * @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2) 373fde0e16SJolly Shah */ 383fde0e16SJolly Shah struct zynqmp_clk_divider { 393fde0e16SJolly Shah struct clk_hw hw; 403fde0e16SJolly Shah u8 flags; 41c06e6440SMichael Tretter bool is_frac; 423fde0e16SJolly Shah u32 clk_id; 433fde0e16SJolly Shah u32 div_type; 44e942171bSRajan Vaja u16 max_div; 453fde0e16SJolly Shah }; 463fde0e16SJolly Shah 473fde0e16SJolly Shah static inline int zynqmp_divider_get_val(unsigned long parent_rate, 48*34bbe036STejas Patel unsigned long rate, u16 flags) 493fde0e16SJolly Shah { 50*34bbe036STejas Patel int up, down; 51*34bbe036STejas Patel unsigned long up_rate, down_rate; 52*34bbe036STejas Patel 53*34bbe036STejas Patel if (flags & CLK_DIVIDER_POWER_OF_TWO) { 54*34bbe036STejas Patel up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 55*34bbe036STejas Patel down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate); 56*34bbe036STejas Patel 57*34bbe036STejas Patel up = __roundup_pow_of_two(up); 58*34bbe036STejas Patel down = __rounddown_pow_of_two(down); 59*34bbe036STejas Patel 60*34bbe036STejas Patel up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up); 61*34bbe036STejas Patel down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down); 62*34bbe036STejas Patel 63*34bbe036STejas Patel return (rate - up_rate) <= (down_rate - rate) ? up : down; 64*34bbe036STejas Patel 65*34bbe036STejas Patel } else { 663fde0e16SJolly Shah return DIV_ROUND_CLOSEST(parent_rate, rate); 673fde0e16SJolly Shah } 68*34bbe036STejas Patel } 693fde0e16SJolly Shah 703fde0e16SJolly Shah /** 713fde0e16SJolly Shah * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock 723fde0e16SJolly Shah * @hw: handle between common and hardware-specific interfaces 733fde0e16SJolly Shah * @parent_rate: rate of parent clock 743fde0e16SJolly Shah * 753fde0e16SJolly Shah * Return: 0 on success else error+reason 763fde0e16SJolly Shah */ 773fde0e16SJolly Shah static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, 783fde0e16SJolly Shah unsigned long parent_rate) 793fde0e16SJolly Shah { 803fde0e16SJolly Shah struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 813fde0e16SJolly Shah const char *clk_name = clk_hw_get_name(hw); 823fde0e16SJolly Shah u32 clk_id = divider->clk_id; 833fde0e16SJolly Shah u32 div_type = divider->div_type; 843fde0e16SJolly Shah u32 div, value; 853fde0e16SJolly Shah int ret; 863fde0e16SJolly Shah const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 873fde0e16SJolly Shah 883fde0e16SJolly Shah ret = eemi_ops->clock_getdivider(clk_id, &div); 893fde0e16SJolly Shah 903fde0e16SJolly Shah if (ret) 913fde0e16SJolly Shah pr_warn_once("%s() get divider failed for %s, ret = %d\n", 923fde0e16SJolly Shah __func__, clk_name, ret); 933fde0e16SJolly Shah 943fde0e16SJolly Shah if (div_type == TYPE_DIV1) 953fde0e16SJolly Shah value = div & 0xFFFF; 963fde0e16SJolly Shah else 973fde0e16SJolly Shah value = div >> 16; 983fde0e16SJolly Shah 99*34bbe036STejas Patel if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 100*34bbe036STejas Patel value = 1 << value; 101*34bbe036STejas Patel 10260d74e01SRajan Vaja if (!value) { 10360d74e01SRajan Vaja WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), 10460d74e01SRajan Vaja "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", 10560d74e01SRajan Vaja clk_name); 10660d74e01SRajan Vaja return parent_rate; 10760d74e01SRajan Vaja } 10860d74e01SRajan Vaja 1093fde0e16SJolly Shah return DIV_ROUND_UP_ULL(parent_rate, value); 1103fde0e16SJolly Shah } 1113fde0e16SJolly Shah 1124ebd92d2SRajan Vaja static void zynqmp_get_divider2_val(struct clk_hw *hw, 1134ebd92d2SRajan Vaja unsigned long rate, 1144ebd92d2SRajan Vaja unsigned long parent_rate, 1154ebd92d2SRajan Vaja struct zynqmp_clk_divider *divider, 1164ebd92d2SRajan Vaja int *bestdiv) 1174ebd92d2SRajan Vaja { 1184ebd92d2SRajan Vaja int div1; 1194ebd92d2SRajan Vaja int div2; 1204ebd92d2SRajan Vaja long error = LONG_MAX; 1214ebd92d2SRajan Vaja struct clk_hw *parent_hw = clk_hw_get_parent(hw); 1224ebd92d2SRajan Vaja struct zynqmp_clk_divider *pdivider = to_zynqmp_clk_divider(parent_hw); 1234ebd92d2SRajan Vaja 1244ebd92d2SRajan Vaja if (!pdivider) 1254ebd92d2SRajan Vaja return; 1264ebd92d2SRajan Vaja 1274ebd92d2SRajan Vaja *bestdiv = 1; 1284ebd92d2SRajan Vaja for (div1 = 1; div1 <= pdivider->max_div;) { 1294ebd92d2SRajan Vaja for (div2 = 1; div2 <= divider->max_div;) { 1304ebd92d2SRajan Vaja long new_error = ((parent_rate / div1) / div2) - rate; 1314ebd92d2SRajan Vaja 1324ebd92d2SRajan Vaja if (abs(new_error) < abs(error)) { 1334ebd92d2SRajan Vaja *bestdiv = div2; 1344ebd92d2SRajan Vaja error = new_error; 1354ebd92d2SRajan Vaja } 1364ebd92d2SRajan Vaja if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 1374ebd92d2SRajan Vaja div2 = div2 << 1; 1384ebd92d2SRajan Vaja else 1394ebd92d2SRajan Vaja div2++; 1404ebd92d2SRajan Vaja } 1414ebd92d2SRajan Vaja if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO) 1424ebd92d2SRajan Vaja div1 = div1 << 1; 1434ebd92d2SRajan Vaja else 1444ebd92d2SRajan Vaja div1++; 1454ebd92d2SRajan Vaja } 1464ebd92d2SRajan Vaja } 1474ebd92d2SRajan Vaja 1483fde0e16SJolly Shah /** 1493fde0e16SJolly Shah * zynqmp_clk_divider_round_rate() - Round rate of divider clock 1503fde0e16SJolly Shah * @hw: handle between common and hardware-specific interfaces 1513fde0e16SJolly Shah * @rate: rate of clock to be set 1523fde0e16SJolly Shah * @prate: rate of parent clock 1533fde0e16SJolly Shah * 1543fde0e16SJolly Shah * Return: 0 on success else error+reason 1553fde0e16SJolly Shah */ 1563fde0e16SJolly Shah static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, 1573fde0e16SJolly Shah unsigned long rate, 1583fde0e16SJolly Shah unsigned long *prate) 1593fde0e16SJolly Shah { 1603fde0e16SJolly Shah struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 1613fde0e16SJolly Shah const char *clk_name = clk_hw_get_name(hw); 1623fde0e16SJolly Shah u32 clk_id = divider->clk_id; 1633fde0e16SJolly Shah u32 div_type = divider->div_type; 1643fde0e16SJolly Shah u32 bestdiv; 1653fde0e16SJolly Shah int ret; 1663fde0e16SJolly Shah const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 1673fde0e16SJolly Shah 1683fde0e16SJolly Shah /* if read only, just return current value */ 1693fde0e16SJolly Shah if (divider->flags & CLK_DIVIDER_READ_ONLY) { 1703fde0e16SJolly Shah ret = eemi_ops->clock_getdivider(clk_id, &bestdiv); 1713fde0e16SJolly Shah 1723fde0e16SJolly Shah if (ret) 1733fde0e16SJolly Shah pr_warn_once("%s() get divider failed for %s, ret = %d\n", 1743fde0e16SJolly Shah __func__, clk_name, ret); 1753fde0e16SJolly Shah if (div_type == TYPE_DIV1) 1763fde0e16SJolly Shah bestdiv = bestdiv & 0xFFFF; 1773fde0e16SJolly Shah else 1783fde0e16SJolly Shah bestdiv = bestdiv >> 16; 1793fde0e16SJolly Shah 180*34bbe036STejas Patel if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 181*34bbe036STejas Patel bestdiv = 1 << bestdiv; 182*34bbe036STejas Patel 1833fde0e16SJolly Shah return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); 1843fde0e16SJolly Shah } 1853fde0e16SJolly Shah 186*34bbe036STejas Patel bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags); 1873fde0e16SJolly Shah 1884ebd92d2SRajan Vaja /* 1894ebd92d2SRajan Vaja * In case of two divisors, compute best divider values and return 1904ebd92d2SRajan Vaja * divider2 value based on compute value. div1 will be automatically 1914ebd92d2SRajan Vaja * set to optimum based on required total divider value. 1924ebd92d2SRajan Vaja */ 1934ebd92d2SRajan Vaja if (div_type == TYPE_DIV2 && 1944ebd92d2SRajan Vaja (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { 1954ebd92d2SRajan Vaja zynqmp_get_divider2_val(hw, rate, *prate, divider, &bestdiv); 1964ebd92d2SRajan Vaja } 1974ebd92d2SRajan Vaja 198c06e6440SMichael Tretter if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) 1993fde0e16SJolly Shah bestdiv = rate % *prate ? 1 : bestdiv; 2003fde0e16SJolly Shah *prate = rate * bestdiv; 2013fde0e16SJolly Shah 2023fde0e16SJolly Shah return rate; 2033fde0e16SJolly Shah } 2043fde0e16SJolly Shah 2053fde0e16SJolly Shah /** 2063fde0e16SJolly Shah * zynqmp_clk_divider_set_rate() - Set rate of divider clock 2073fde0e16SJolly Shah * @hw: handle between common and hardware-specific interfaces 2083fde0e16SJolly Shah * @rate: rate of clock to be set 2093fde0e16SJolly Shah * @parent_rate: rate of parent clock 2103fde0e16SJolly Shah * 2113fde0e16SJolly Shah * Return: 0 on success else error+reason 2123fde0e16SJolly Shah */ 2133fde0e16SJolly Shah static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 2143fde0e16SJolly Shah unsigned long parent_rate) 2153fde0e16SJolly Shah { 2163fde0e16SJolly Shah struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 2173fde0e16SJolly Shah const char *clk_name = clk_hw_get_name(hw); 2183fde0e16SJolly Shah u32 clk_id = divider->clk_id; 2193fde0e16SJolly Shah u32 div_type = divider->div_type; 2203fde0e16SJolly Shah u32 value, div; 2213fde0e16SJolly Shah int ret; 2223fde0e16SJolly Shah const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 2233fde0e16SJolly Shah 224*34bbe036STejas Patel value = zynqmp_divider_get_val(parent_rate, rate, divider->flags); 2253fde0e16SJolly Shah if (div_type == TYPE_DIV1) { 2263fde0e16SJolly Shah div = value & 0xFFFF; 2273fde0e16SJolly Shah div |= 0xffff << 16; 2283fde0e16SJolly Shah } else { 2293fde0e16SJolly Shah div = 0xffff; 2303fde0e16SJolly Shah div |= value << 16; 2313fde0e16SJolly Shah } 2323fde0e16SJolly Shah 233*34bbe036STejas Patel if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 234*34bbe036STejas Patel div = __ffs(div); 235*34bbe036STejas Patel 2363fde0e16SJolly Shah ret = eemi_ops->clock_setdivider(clk_id, div); 2373fde0e16SJolly Shah 2383fde0e16SJolly Shah if (ret) 2393fde0e16SJolly Shah pr_warn_once("%s() set divider failed for %s, ret = %d\n", 2403fde0e16SJolly Shah __func__, clk_name, ret); 2413fde0e16SJolly Shah 2423fde0e16SJolly Shah return ret; 2433fde0e16SJolly Shah } 2443fde0e16SJolly Shah 2453fde0e16SJolly Shah static const struct clk_ops zynqmp_clk_divider_ops = { 2463fde0e16SJolly Shah .recalc_rate = zynqmp_clk_divider_recalc_rate, 2473fde0e16SJolly Shah .round_rate = zynqmp_clk_divider_round_rate, 2483fde0e16SJolly Shah .set_rate = zynqmp_clk_divider_set_rate, 2493fde0e16SJolly Shah }; 2503fde0e16SJolly Shah 2513fde0e16SJolly Shah /** 252e942171bSRajan Vaja * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware. 253e942171bSRajan Vaja * @clk_id: Id of clock 254e942171bSRajan Vaja * @type: Divider type 255e942171bSRajan Vaja * 256e942171bSRajan Vaja * Return: Maximum divisor of a clock if query data is successful 257e942171bSRajan Vaja * U16_MAX in case of query data is not success 258e942171bSRajan Vaja */ 259e942171bSRajan Vaja u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) 260e942171bSRajan Vaja { 261e942171bSRajan Vaja const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); 262e942171bSRajan Vaja struct zynqmp_pm_query_data qdata = {0}; 263e942171bSRajan Vaja u32 ret_payload[PAYLOAD_ARG_CNT]; 264e942171bSRajan Vaja int ret; 265e942171bSRajan Vaja 266e942171bSRajan Vaja qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR; 267e942171bSRajan Vaja qdata.arg1 = clk_id; 268e942171bSRajan Vaja qdata.arg2 = type; 269e942171bSRajan Vaja ret = eemi_ops->query_data(qdata, ret_payload); 270e942171bSRajan Vaja /* 271e942171bSRajan Vaja * To maintain backward compatibility return maximum possible value 272e942171bSRajan Vaja * (0xFFFF) if query for max divisor is not successful. 273e942171bSRajan Vaja */ 274e942171bSRajan Vaja if (ret) 275e942171bSRajan Vaja return U16_MAX; 276e942171bSRajan Vaja 277e942171bSRajan Vaja return ret_payload[1]; 278e942171bSRajan Vaja } 279e942171bSRajan Vaja 280e942171bSRajan Vaja /** 2813fde0e16SJolly Shah * zynqmp_clk_register_divider() - Register a divider clock 2823fde0e16SJolly Shah * @name: Name of this clock 2833fde0e16SJolly Shah * @clk_id: Id of clock 2843fde0e16SJolly Shah * @parents: Name of this clock's parents 2853fde0e16SJolly Shah * @num_parents: Number of parents 2863fde0e16SJolly Shah * @nodes: Clock topology node 2873fde0e16SJolly Shah * 2883fde0e16SJolly Shah * Return: clock hardware to registered clock divider 2893fde0e16SJolly Shah */ 2903fde0e16SJolly Shah struct clk_hw *zynqmp_clk_register_divider(const char *name, 2913fde0e16SJolly Shah u32 clk_id, 2923fde0e16SJolly Shah const char * const *parents, 2933fde0e16SJolly Shah u8 num_parents, 2943fde0e16SJolly Shah const struct clock_topology *nodes) 2953fde0e16SJolly Shah { 2963fde0e16SJolly Shah struct zynqmp_clk_divider *div; 2973fde0e16SJolly Shah struct clk_hw *hw; 2983fde0e16SJolly Shah struct clk_init_data init; 2993fde0e16SJolly Shah int ret; 3003fde0e16SJolly Shah 3013fde0e16SJolly Shah /* allocate the divider */ 3023fde0e16SJolly Shah div = kzalloc(sizeof(*div), GFP_KERNEL); 3033fde0e16SJolly Shah if (!div) 3043fde0e16SJolly Shah return ERR_PTR(-ENOMEM); 3053fde0e16SJolly Shah 3063fde0e16SJolly Shah init.name = name; 3073fde0e16SJolly Shah init.ops = &zynqmp_clk_divider_ops; 308c06e6440SMichael Tretter /* CLK_FRAC is not defined in the common clk framework */ 309c06e6440SMichael Tretter init.flags = nodes->flag & ~CLK_FRAC; 3103fde0e16SJolly Shah init.parent_names = parents; 3113fde0e16SJolly Shah init.num_parents = 1; 3123fde0e16SJolly Shah 3133fde0e16SJolly Shah /* struct clk_divider assignments */ 314c06e6440SMichael Tretter div->is_frac = !!(nodes->flag & CLK_FRAC); 3153fde0e16SJolly Shah div->flags = nodes->type_flag; 3163fde0e16SJolly Shah div->hw.init = &init; 3173fde0e16SJolly Shah div->clk_id = clk_id; 3183fde0e16SJolly Shah div->div_type = nodes->type; 3193fde0e16SJolly Shah 320e942171bSRajan Vaja /* 321e942171bSRajan Vaja * To achieve best possible rate, maximum limit of divider is required 322e942171bSRajan Vaja * while computation. 323e942171bSRajan Vaja */ 324e942171bSRajan Vaja div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type); 325e942171bSRajan Vaja 3263fde0e16SJolly Shah hw = &div->hw; 3273fde0e16SJolly Shah ret = clk_hw_register(NULL, hw); 3283fde0e16SJolly Shah if (ret) { 3293fde0e16SJolly Shah kfree(div); 3303fde0e16SJolly Shah hw = ERR_PTR(ret); 3313fde0e16SJolly Shah } 3323fde0e16SJolly Shah 3333fde0e16SJolly Shah return hw; 3343fde0e16SJolly Shah } 335