13fde0e16SJolly Shah // SPDX-License-Identifier: GPL-2.0
23fde0e16SJolly Shah /*
33fde0e16SJolly Shah * Zynq UltraScale+ MPSoC Divider support
43fde0e16SJolly Shah *
534bbe036STejas Patel * Copyright (C) 2016-2019 Xilinx
63fde0e16SJolly Shah *
73fde0e16SJolly Shah * Adjustable divider clock implementation
83fde0e16SJolly Shah */
93fde0e16SJolly Shah
103fde0e16SJolly Shah #include <linux/clk.h>
113fde0e16SJolly Shah #include <linux/clk-provider.h>
123fde0e16SJolly Shah #include <linux/slab.h>
133fde0e16SJolly Shah #include "clk-zynqmp.h"
143fde0e16SJolly Shah
153fde0e16SJolly Shah /*
163fde0e16SJolly Shah * DOC: basic adjustable divider clock that cannot gate
173fde0e16SJolly Shah *
183fde0e16SJolly Shah * Traits of this clock:
193fde0e16SJolly Shah * prepare - clk_prepare only ensures that parents are prepared
203fde0e16SJolly Shah * enable - clk_enable only ensures that parents are enabled
213fde0e16SJolly Shah * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
223fde0e16SJolly Shah * parent - fixed parent. No clk_set_parent support
233fde0e16SJolly Shah */
243fde0e16SJolly Shah
253fde0e16SJolly Shah #define to_zynqmp_clk_divider(_hw) \
263fde0e16SJolly Shah container_of(_hw, struct zynqmp_clk_divider, hw)
273fde0e16SJolly Shah
283fde0e16SJolly Shah #define CLK_FRAC BIT(13) /* has a fractional parent */
292ce7e495STejas Patel #define CUSTOM_FLAG_CLK_FRAC BIT(0) /* has a fractional parent in custom type flag */
303fde0e16SJolly Shah
313fde0e16SJolly Shah /**
323fde0e16SJolly Shah * struct zynqmp_clk_divider - adjustable divider clock
333fde0e16SJolly Shah * @hw: handle between common and hardware-specific interfaces
343fde0e16SJolly Shah * @flags: Hardware specific flags
35c06e6440SMichael Tretter * @is_frac: The divider is a fractional divider
363fde0e16SJolly Shah * @clk_id: Id of clock
373fde0e16SJolly Shah * @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2)
387db20bc1SLee Jones * @max_div: maximum supported divisor (fetched from firmware)
393fde0e16SJolly Shah */
403fde0e16SJolly Shah struct zynqmp_clk_divider {
413fde0e16SJolly Shah struct clk_hw hw;
423fde0e16SJolly Shah u8 flags;
43c06e6440SMichael Tretter bool is_frac;
443fde0e16SJolly Shah u32 clk_id;
453fde0e16SJolly Shah u32 div_type;
46e942171bSRajan Vaja u16 max_div;
473fde0e16SJolly Shah };
483fde0e16SJolly Shah
zynqmp_divider_get_val(unsigned long parent_rate,unsigned long rate,u16 flags)493fde0e16SJolly Shah static inline int zynqmp_divider_get_val(unsigned long parent_rate,
5034bbe036STejas Patel unsigned long rate, u16 flags)
513fde0e16SJolly Shah {
5234bbe036STejas Patel int up, down;
5334bbe036STejas Patel unsigned long up_rate, down_rate;
5434bbe036STejas Patel
5534bbe036STejas Patel if (flags & CLK_DIVIDER_POWER_OF_TWO) {
5634bbe036STejas Patel up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
5734bbe036STejas Patel down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate);
5834bbe036STejas Patel
5934bbe036STejas Patel up = __roundup_pow_of_two(up);
6034bbe036STejas Patel down = __rounddown_pow_of_two(down);
6134bbe036STejas Patel
6234bbe036STejas Patel up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up);
6334bbe036STejas Patel down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down);
6434bbe036STejas Patel
6534bbe036STejas Patel return (rate - up_rate) <= (down_rate - rate) ? up : down;
6634bbe036STejas Patel
6734bbe036STejas Patel } else {
683fde0e16SJolly Shah return DIV_ROUND_CLOSEST(parent_rate, rate);
693fde0e16SJolly Shah }
7034bbe036STejas Patel }
713fde0e16SJolly Shah
723fde0e16SJolly Shah /**
733fde0e16SJolly Shah * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
743fde0e16SJolly Shah * @hw: handle between common and hardware-specific interfaces
753fde0e16SJolly Shah * @parent_rate: rate of parent clock
763fde0e16SJolly Shah *
773fde0e16SJolly Shah * Return: 0 on success else error+reason
783fde0e16SJolly Shah */
zynqmp_clk_divider_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)793fde0e16SJolly Shah static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
803fde0e16SJolly Shah unsigned long parent_rate)
813fde0e16SJolly Shah {
823fde0e16SJolly Shah struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
833fde0e16SJolly Shah const char *clk_name = clk_hw_get_name(hw);
843fde0e16SJolly Shah u32 clk_id = divider->clk_id;
853fde0e16SJolly Shah u32 div_type = divider->div_type;
863fde0e16SJolly Shah u32 div, value;
873fde0e16SJolly Shah int ret;
883fde0e16SJolly Shah
890667a8d1SRajan Vaja ret = zynqmp_pm_clock_getdivider(clk_id, &div);
903fde0e16SJolly Shah
913fde0e16SJolly Shah if (ret)
924917394eSMichael Tretter pr_debug("%s() get divider failed for %s, ret = %d\n",
933fde0e16SJolly Shah __func__, clk_name, ret);
943fde0e16SJolly Shah
953fde0e16SJolly Shah if (div_type == TYPE_DIV1)
963fde0e16SJolly Shah value = div & 0xFFFF;
973fde0e16SJolly Shah else
983fde0e16SJolly Shah value = div >> 16;
993fde0e16SJolly Shah
10034bbe036STejas Patel if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
10134bbe036STejas Patel value = 1 << value;
10234bbe036STejas Patel
10360d74e01SRajan Vaja if (!value) {
10460d74e01SRajan Vaja WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
10560d74e01SRajan Vaja "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
10660d74e01SRajan Vaja clk_name);
10760d74e01SRajan Vaja return parent_rate;
10860d74e01SRajan Vaja }
10960d74e01SRajan Vaja
1103fde0e16SJolly Shah return DIV_ROUND_UP_ULL(parent_rate, value);
1113fde0e16SJolly Shah }
1123fde0e16SJolly Shah
1133fde0e16SJolly Shah /**
1143fde0e16SJolly Shah * zynqmp_clk_divider_round_rate() - Round rate of divider clock
1153fde0e16SJolly Shah * @hw: handle between common and hardware-specific interfaces
1163fde0e16SJolly Shah * @rate: rate of clock to be set
1173fde0e16SJolly Shah * @prate: rate of parent clock
1183fde0e16SJolly Shah *
1193fde0e16SJolly Shah * Return: 0 on success else error+reason
1203fde0e16SJolly Shah */
zynqmp_clk_divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)1213fde0e16SJolly Shah static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
1223fde0e16SJolly Shah unsigned long rate,
1233fde0e16SJolly Shah unsigned long *prate)
1243fde0e16SJolly Shah {
1253fde0e16SJolly Shah struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
1263fde0e16SJolly Shah const char *clk_name = clk_hw_get_name(hw);
1273fde0e16SJolly Shah u32 clk_id = divider->clk_id;
1283fde0e16SJolly Shah u32 div_type = divider->div_type;
1293fde0e16SJolly Shah u32 bestdiv;
1303fde0e16SJolly Shah int ret;
131*1fe15be1SJay Buddhabhatti u8 width;
1323fde0e16SJolly Shah
1333fde0e16SJolly Shah /* if read only, just return current value */
1343fde0e16SJolly Shah if (divider->flags & CLK_DIVIDER_READ_ONLY) {
1350667a8d1SRajan Vaja ret = zynqmp_pm_clock_getdivider(clk_id, &bestdiv);
1363fde0e16SJolly Shah
1373fde0e16SJolly Shah if (ret)
1384917394eSMichael Tretter pr_debug("%s() get divider failed for %s, ret = %d\n",
1393fde0e16SJolly Shah __func__, clk_name, ret);
1403fde0e16SJolly Shah if (div_type == TYPE_DIV1)
1413fde0e16SJolly Shah bestdiv = bestdiv & 0xFFFF;
1423fde0e16SJolly Shah else
1433fde0e16SJolly Shah bestdiv = bestdiv >> 16;
1443fde0e16SJolly Shah
14534bbe036STejas Patel if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
14634bbe036STejas Patel bestdiv = 1 << bestdiv;
14734bbe036STejas Patel
1483fde0e16SJolly Shah return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
1493fde0e16SJolly Shah }
1503fde0e16SJolly Shah
151*1fe15be1SJay Buddhabhatti width = fls(divider->max_div);
1523fde0e16SJolly Shah
153*1fe15be1SJay Buddhabhatti rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags);
1544ebd92d2SRajan Vaja
155*1fe15be1SJay Buddhabhatti if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate))
156*1fe15be1SJay Buddhabhatti *prate = rate;
1573fde0e16SJolly Shah
1583fde0e16SJolly Shah return rate;
1593fde0e16SJolly Shah }
1603fde0e16SJolly Shah
1613fde0e16SJolly Shah /**
1623fde0e16SJolly Shah * zynqmp_clk_divider_set_rate() - Set rate of divider clock
1633fde0e16SJolly Shah * @hw: handle between common and hardware-specific interfaces
1643fde0e16SJolly Shah * @rate: rate of clock to be set
1653fde0e16SJolly Shah * @parent_rate: rate of parent clock
1663fde0e16SJolly Shah *
1673fde0e16SJolly Shah * Return: 0 on success else error+reason
1683fde0e16SJolly Shah */
zynqmp_clk_divider_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1693fde0e16SJolly Shah static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
1703fde0e16SJolly Shah unsigned long parent_rate)
1713fde0e16SJolly Shah {
1723fde0e16SJolly Shah struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
1733fde0e16SJolly Shah const char *clk_name = clk_hw_get_name(hw);
1743fde0e16SJolly Shah u32 clk_id = divider->clk_id;
1753fde0e16SJolly Shah u32 div_type = divider->div_type;
1763fde0e16SJolly Shah u32 value, div;
1773fde0e16SJolly Shah int ret;
1783fde0e16SJolly Shah
17934bbe036STejas Patel value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);
1803fde0e16SJolly Shah if (div_type == TYPE_DIV1) {
1813fde0e16SJolly Shah div = value & 0xFFFF;
1823fde0e16SJolly Shah div |= 0xffff << 16;
1833fde0e16SJolly Shah } else {
1843fde0e16SJolly Shah div = 0xffff;
1853fde0e16SJolly Shah div |= value << 16;
1863fde0e16SJolly Shah }
1873fde0e16SJolly Shah
18834bbe036STejas Patel if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
18934bbe036STejas Patel div = __ffs(div);
19034bbe036STejas Patel
191fc9fb8fbSRajan Vaja ret = zynqmp_pm_clock_setdivider(clk_id, div);
1923fde0e16SJolly Shah
1933fde0e16SJolly Shah if (ret)
1944917394eSMichael Tretter pr_debug("%s() set divider failed for %s, ret = %d\n",
1953fde0e16SJolly Shah __func__, clk_name, ret);
1963fde0e16SJolly Shah
1973fde0e16SJolly Shah return ret;
1983fde0e16SJolly Shah }
1993fde0e16SJolly Shah
2003fde0e16SJolly Shah static const struct clk_ops zynqmp_clk_divider_ops = {
2013fde0e16SJolly Shah .recalc_rate = zynqmp_clk_divider_recalc_rate,
2023fde0e16SJolly Shah .round_rate = zynqmp_clk_divider_round_rate,
2033fde0e16SJolly Shah .set_rate = zynqmp_clk_divider_set_rate,
2043fde0e16SJolly Shah };
2053fde0e16SJolly Shah
20603aea91bSRajan Vaja static const struct clk_ops zynqmp_clk_divider_ro_ops = {
20703aea91bSRajan Vaja .recalc_rate = zynqmp_clk_divider_recalc_rate,
20803aea91bSRajan Vaja .round_rate = zynqmp_clk_divider_round_rate,
20903aea91bSRajan Vaja };
21003aea91bSRajan Vaja
2113fde0e16SJolly Shah /**
212e942171bSRajan Vaja * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware.
213e942171bSRajan Vaja * @clk_id: Id of clock
214e942171bSRajan Vaja * @type: Divider type
215e942171bSRajan Vaja *
216e942171bSRajan Vaja * Return: Maximum divisor of a clock if query data is successful
217e942171bSRajan Vaja * U16_MAX in case of query data is not success
218e942171bSRajan Vaja */
zynqmp_clk_get_max_divisor(u32 clk_id,u32 type)2199d66e857SYueHaibing static u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type)
220e942171bSRajan Vaja {
221e942171bSRajan Vaja struct zynqmp_pm_query_data qdata = {0};
222e942171bSRajan Vaja u32 ret_payload[PAYLOAD_ARG_CNT];
223e942171bSRajan Vaja int ret;
224e942171bSRajan Vaja
225e942171bSRajan Vaja qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR;
226e942171bSRajan Vaja qdata.arg1 = clk_id;
227e942171bSRajan Vaja qdata.arg2 = type;
2286366c1baSRajan Vaja ret = zynqmp_pm_query_data(qdata, ret_payload);
229e942171bSRajan Vaja /*
230e942171bSRajan Vaja * To maintain backward compatibility return maximum possible value
231e942171bSRajan Vaja * (0xFFFF) if query for max divisor is not successful.
232e942171bSRajan Vaja */
233e942171bSRajan Vaja if (ret)
234e942171bSRajan Vaja return U16_MAX;
235e942171bSRajan Vaja
236e942171bSRajan Vaja return ret_payload[1];
237e942171bSRajan Vaja }
238e942171bSRajan Vaja
zynqmp_clk_map_divider_ccf_flags(const u32 zynqmp_type_flag)2391b09c308SRajan Vaja static inline unsigned long zynqmp_clk_map_divider_ccf_flags(
2401b09c308SRajan Vaja const u32 zynqmp_type_flag)
2411b09c308SRajan Vaja {
2421b09c308SRajan Vaja unsigned long ccf_flag = 0;
2431b09c308SRajan Vaja
2441b09c308SRajan Vaja if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED)
2451b09c308SRajan Vaja ccf_flag |= CLK_DIVIDER_ONE_BASED;
2461b09c308SRajan Vaja if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO)
2471b09c308SRajan Vaja ccf_flag |= CLK_DIVIDER_POWER_OF_TWO;
2481b09c308SRajan Vaja if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO)
2491b09c308SRajan Vaja ccf_flag |= CLK_DIVIDER_ALLOW_ZERO;
2501b09c308SRajan Vaja if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO)
2511b09c308SRajan Vaja ccf_flag |= CLK_DIVIDER_HIWORD_MASK;
2521b09c308SRajan Vaja if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST)
2531b09c308SRajan Vaja ccf_flag |= CLK_DIVIDER_ROUND_CLOSEST;
2541b09c308SRajan Vaja if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY)
2551b09c308SRajan Vaja ccf_flag |= CLK_DIVIDER_READ_ONLY;
2561b09c308SRajan Vaja if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO)
2571b09c308SRajan Vaja ccf_flag |= CLK_DIVIDER_MAX_AT_ZERO;
2581b09c308SRajan Vaja
2591b09c308SRajan Vaja return ccf_flag;
2601b09c308SRajan Vaja }
2611b09c308SRajan Vaja
262e942171bSRajan Vaja /**
2633fde0e16SJolly Shah * zynqmp_clk_register_divider() - Register a divider clock
2643fde0e16SJolly Shah * @name: Name of this clock
2653fde0e16SJolly Shah * @clk_id: Id of clock
2663fde0e16SJolly Shah * @parents: Name of this clock's parents
2673fde0e16SJolly Shah * @num_parents: Number of parents
2683fde0e16SJolly Shah * @nodes: Clock topology node
2693fde0e16SJolly Shah *
2703fde0e16SJolly Shah * Return: clock hardware to registered clock divider
2713fde0e16SJolly Shah */
zynqmp_clk_register_divider(const char * name,u32 clk_id,const char * const * parents,u8 num_parents,const struct clock_topology * nodes)2723fde0e16SJolly Shah struct clk_hw *zynqmp_clk_register_divider(const char *name,
2733fde0e16SJolly Shah u32 clk_id,
2743fde0e16SJolly Shah const char * const *parents,
2753fde0e16SJolly Shah u8 num_parents,
2763fde0e16SJolly Shah const struct clock_topology *nodes)
2773fde0e16SJolly Shah {
2783fde0e16SJolly Shah struct zynqmp_clk_divider *div;
2793fde0e16SJolly Shah struct clk_hw *hw;
2803fde0e16SJolly Shah struct clk_init_data init;
2813fde0e16SJolly Shah int ret;
2823fde0e16SJolly Shah
2833fde0e16SJolly Shah /* allocate the divider */
2843fde0e16SJolly Shah div = kzalloc(sizeof(*div), GFP_KERNEL);
2853fde0e16SJolly Shah if (!div)
2863fde0e16SJolly Shah return ERR_PTR(-ENOMEM);
2873fde0e16SJolly Shah
2883fde0e16SJolly Shah init.name = name;
28903aea91bSRajan Vaja if (nodes->type_flag & CLK_DIVIDER_READ_ONLY)
29003aea91bSRajan Vaja init.ops = &zynqmp_clk_divider_ro_ops;
29103aea91bSRajan Vaja else
2923fde0e16SJolly Shah init.ops = &zynqmp_clk_divider_ops;
293610a5d83SRajan Vaja
294610a5d83SRajan Vaja init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);
295610a5d83SRajan Vaja
2963fde0e16SJolly Shah init.parent_names = parents;
2973fde0e16SJolly Shah init.num_parents = 1;
2983fde0e16SJolly Shah
2993fde0e16SJolly Shah /* struct clk_divider assignments */
3002ce7e495STejas Patel div->is_frac = !!((nodes->flag & CLK_FRAC) |
3012ce7e495STejas Patel (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));
3021b09c308SRajan Vaja div->flags = zynqmp_clk_map_divider_ccf_flags(nodes->type_flag);
3033fde0e16SJolly Shah div->hw.init = &init;
3043fde0e16SJolly Shah div->clk_id = clk_id;
3053fde0e16SJolly Shah div->div_type = nodes->type;
3063fde0e16SJolly Shah
307e942171bSRajan Vaja /*
308e942171bSRajan Vaja * To achieve best possible rate, maximum limit of divider is required
309e942171bSRajan Vaja * while computation.
310e942171bSRajan Vaja */
311e942171bSRajan Vaja div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type);
312e942171bSRajan Vaja
3133fde0e16SJolly Shah hw = &div->hw;
3143fde0e16SJolly Shah ret = clk_hw_register(NULL, hw);
3153fde0e16SJolly Shah if (ret) {
3163fde0e16SJolly Shah kfree(div);
3173fde0e16SJolly Shah hw = ERR_PTR(ret);
3183fde0e16SJolly Shah }
3193fde0e16SJolly Shah
3203fde0e16SJolly Shah return hw;
3213fde0e16SJolly Shah }
322