1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Zynq clock controller 4 * 5 * Copyright (C) 2012 - 2013 Xilinx 6 * 7 * Sören Brinkmann <soren.brinkmann@xilinx.com> 8 */ 9 10 #include <linux/clk/zynq.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/slab.h> 16 #include <linux/string.h> 17 #include <linux/io.h> 18 19 static void __iomem *zynq_clkc_base; 20 21 #define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00) 22 #define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04) 23 #define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08) 24 #define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c) 25 #define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20) 26 #define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24) 27 #define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28) 28 #define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c) 29 #define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40) 30 #define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44) 31 #define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48) 32 #define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c) 33 #define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50) 34 #define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54) 35 #define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58) 36 #define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c) 37 #define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60) 38 #define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64) 39 #define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68) 40 #define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70) 41 #define SLCR_621_TRUE (zynq_clkc_base + 0xc4) 42 #define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204) 43 44 #define NUM_MIO_PINS 54 45 #define CLK_NAME_LEN 16 46 47 #define DBG_CLK_CTRL_CLKACT_TRC BIT(0) 48 #define DBG_CLK_CTRL_CPU_1XCLKACT BIT(1) 49 50 enum zynq_clk { 51 armpll, ddrpll, iopll, 52 cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x, 53 ddr2x, ddr3x, dci, 54 lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1, 55 sdio0, sdio1, uart0, uart1, spi0, spi1, dma, 56 usb0_aper, usb1_aper, gem0_aper, gem1_aper, 57 sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper, 58 i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper, 59 smc_aper, swdt, dbg_trc, dbg_apb, clk_max}; 60 61 static struct clk *ps_clk; 62 static struct clk *clks[clk_max]; 63 static struct clk_onecell_data clk_data; 64 65 static DEFINE_SPINLOCK(armpll_lock); 66 static DEFINE_SPINLOCK(ddrpll_lock); 67 static DEFINE_SPINLOCK(iopll_lock); 68 static DEFINE_SPINLOCK(armclk_lock); 69 static DEFINE_SPINLOCK(swdtclk_lock); 70 static DEFINE_SPINLOCK(ddrclk_lock); 71 static DEFINE_SPINLOCK(dciclk_lock); 72 static DEFINE_SPINLOCK(gem0clk_lock); 73 static DEFINE_SPINLOCK(gem1clk_lock); 74 static DEFINE_SPINLOCK(canclk_lock); 75 static DEFINE_SPINLOCK(canmioclk_lock); 76 static DEFINE_SPINLOCK(dbgclk_lock); 77 static DEFINE_SPINLOCK(aperclk_lock); 78 79 static const char *const armpll_parents[] __initconst = {"armpll_int", 80 "ps_clk"}; 81 static const char *const ddrpll_parents[] __initconst = {"ddrpll_int", 82 "ps_clk"}; 83 static const char *const iopll_parents[] __initconst = {"iopll_int", 84 "ps_clk"}; 85 static const char *gem0_mux_parents[] __initdata = {"gem0_div1", "dummy_name"}; 86 static const char *gem1_mux_parents[] __initdata = {"gem1_div1", "dummy_name"}; 87 static const char *const can0_mio_mux2_parents[] __initconst = {"can0_gate", 88 "can0_mio_mux"}; 89 static const char *const can1_mio_mux2_parents[] __initconst = {"can1_gate", 90 "can1_mio_mux"}; 91 static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div", 92 "dummy_name"}; 93 94 static const char *const dbgtrc_emio_input_names[] __initconst = { 95 "trace_emio_clk"}; 96 static const char *const gem0_emio_input_names[] __initconst = { 97 "gem0_emio_clk"}; 98 static const char *const gem1_emio_input_names[] __initconst = { 99 "gem1_emio_clk"}; 100 static const char *const swdt_ext_clk_input_names[] __initconst = { 101 "swdt_ext_clk"}; 102 103 static void __init zynq_clk_register_fclk(enum zynq_clk fclk, 104 const char *clk_name, void __iomem *fclk_ctrl_reg, 105 const char **parents, int enable) 106 { 107 u32 enable_reg; 108 char *mux_name; 109 char *div0_name; 110 char *div1_name; 111 spinlock_t *fclk_lock; 112 spinlock_t *fclk_gate_lock; 113 void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8; 114 115 fclk_lock = kmalloc_obj(*fclk_lock); 116 if (!fclk_lock) 117 goto err; 118 fclk_gate_lock = kmalloc_obj(*fclk_gate_lock); 119 if (!fclk_gate_lock) 120 goto err_fclk_gate_lock; 121 spin_lock_init(fclk_lock); 122 spin_lock_init(fclk_gate_lock); 123 124 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name); 125 if (!mux_name) 126 goto err_mux_name; 127 div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); 128 if (!div0_name) 129 goto err_div0_name; 130 div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); 131 if (!div1_name) 132 goto err_div1_name; 133 134 clk_register_mux(NULL, mux_name, parents, 4, 135 CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0, 136 fclk_lock); 137 138 clk_register_divider(NULL, div0_name, mux_name, 139 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | 140 CLK_DIVIDER_ALLOW_ZERO, fclk_lock); 141 142 clk_register_divider(NULL, div1_name, div0_name, 143 CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6, 144 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 145 fclk_lock); 146 147 clks[fclk] = clk_register_gate(NULL, clk_name, 148 div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, 149 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); 150 enable_reg = readl(fclk_gate_reg) & 1; 151 if (enable && !enable_reg) { 152 if (clk_prepare_enable(clks[fclk])) 153 pr_warn("%s: FCLK%u enable failed\n", __func__, 154 fclk - fclk0); 155 } 156 kfree(mux_name); 157 kfree(div0_name); 158 kfree(div1_name); 159 160 return; 161 162 err_div1_name: 163 kfree(div0_name); 164 err_div0_name: 165 kfree(mux_name); 166 err_mux_name: 167 kfree(fclk_gate_lock); 168 err_fclk_gate_lock: 169 kfree(fclk_lock); 170 err: 171 clks[fclk] = ERR_PTR(-ENOMEM); 172 } 173 174 static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, 175 enum zynq_clk clk1, const char *clk_name0, 176 const char *clk_name1, void __iomem *clk_ctrl, 177 const char **parents, unsigned int two_gates) 178 { 179 char *mux_name; 180 char *div_name; 181 spinlock_t *lock; 182 183 lock = kmalloc_obj(*lock); 184 if (!lock) 185 goto err; 186 spin_lock_init(lock); 187 188 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0); 189 if (!mux_name) 190 goto err_mux_name; 191 div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0); 192 if (!div_name) 193 goto err_div_name; 194 195 clk_register_mux(NULL, mux_name, parents, 4, 196 CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock); 197 198 clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, 199 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); 200 201 clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, 202 CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); 203 if (two_gates) 204 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, 205 CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); 206 207 kfree(mux_name); 208 kfree(div_name); 209 210 return; 211 212 err_div_name: 213 kfree(mux_name); 214 err_mux_name: 215 kfree(lock); 216 err: 217 clks[clk0] = ERR_PTR(-ENOMEM); 218 if (two_gates) 219 clks[clk1] = ERR_PTR(-ENOMEM); 220 } 221 222 static void __init zynq_clk_setup(struct device_node *np) 223 { 224 int i; 225 u32 tmp; 226 int ret; 227 char clk_name[CLK_NAME_LEN]; 228 unsigned int fclk_enable = 0; 229 const char *clk_output_name[clk_max]; 230 const char *cpu_parents[4]; 231 const char *periph_parents[4]; 232 const char *swdt_ext_clk_mux_parents[2]; 233 const char *can_mio_mux_parents[NUM_MIO_PINS]; 234 const char *dummy_nm = "dummy_name"; 235 236 pr_info("Zynq clock init\n"); 237 238 /* get clock output names from DT */ 239 for (i = 0; i < clk_max; i++) { 240 if (of_property_read_string_index(np, "clock-output-names", 241 i, &clk_output_name[i])) { 242 pr_err("%s: clock output name not in DT\n", __func__); 243 BUG(); 244 } 245 } 246 cpu_parents[0] = clk_output_name[armpll]; 247 cpu_parents[1] = clk_output_name[armpll]; 248 cpu_parents[2] = clk_output_name[ddrpll]; 249 cpu_parents[3] = clk_output_name[iopll]; 250 periph_parents[0] = clk_output_name[iopll]; 251 periph_parents[1] = clk_output_name[iopll]; 252 periph_parents[2] = clk_output_name[armpll]; 253 periph_parents[3] = clk_output_name[ddrpll]; 254 255 of_property_read_u32(np, "fclk-enable", &fclk_enable); 256 257 /* ps_clk */ 258 ret = of_property_read_u32(np, "ps-clk-frequency", &tmp); 259 if (ret) { 260 pr_warn("ps_clk frequency not specified, using 33 MHz.\n"); 261 tmp = 33333333; 262 } 263 ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, 0, tmp); 264 265 /* PLLs */ 266 clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, 267 SLCR_PLL_STATUS, 0, &armpll_lock); 268 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], 269 armpll_parents, 2, CLK_SET_RATE_NO_REPARENT, 270 SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock); 271 272 clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, 273 SLCR_PLL_STATUS, 1, &ddrpll_lock); 274 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], 275 ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT, 276 SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock); 277 278 clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, 279 SLCR_PLL_STATUS, 2, &iopll_lock); 280 clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll], 281 iopll_parents, 2, CLK_SET_RATE_NO_REPARENT, 282 SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock); 283 284 /* CPU clocks */ 285 tmp = readl(SLCR_621_TRUE) & 1; 286 clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 287 CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0, 288 &armclk_lock); 289 clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, 290 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 291 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); 292 293 clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x], 294 "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 295 SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock); 296 297 clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0, 298 1, 2); 299 clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x], 300 "cpu_3or2x_div", CLK_IGNORE_UNUSED, 301 SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock); 302 303 clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1, 304 2 + tmp); 305 clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x], 306 "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 307 26, 0, &armclk_lock); 308 clk_prepare_enable(clks[cpu_2x]); 309 310 clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1, 311 4 + 2 * tmp); 312 clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x], 313 "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27, 314 0, &armclk_lock); 315 316 /* Timers */ 317 swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x]; 318 for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) { 319 int idx = of_property_match_string(np, "clock-names", 320 swdt_ext_clk_input_names[i]); 321 if (idx >= 0) 322 swdt_ext_clk_mux_parents[i + 1] = 323 of_clk_get_parent_name(np, idx); 324 else 325 swdt_ext_clk_mux_parents[i + 1] = dummy_nm; 326 } 327 clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], 328 swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT | 329 CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0, 330 &swdtclk_lock); 331 332 /* DDR clocks */ 333 clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, 334 SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | 335 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); 336 clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], 337 "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); 338 clk_prepare_enable(clks[ddr2x]); 339 clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, 340 SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | 341 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); 342 clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], 343 "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); 344 clk_prepare_enable(clks[ddr3x]); 345 346 clk_register_divider(NULL, "dci_div0", "ddrpll", 0, 347 SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 348 CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); 349 clk_register_divider(NULL, "dci_div1", "dci_div0", 350 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6, 351 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 352 &dciclk_lock); 353 clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", 354 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, 355 &dciclk_lock); 356 clk_prepare_enable(clks[dci]); 357 358 /* Peripheral clocks */ 359 for (i = fclk0; i <= fclk3; i++) { 360 int enable = !!(fclk_enable & BIT(i - fclk0)); 361 362 zynq_clk_register_fclk(i, clk_output_name[i], 363 SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), 364 periph_parents, enable); 365 } 366 367 zynq_clk_register_periph_clk(lqspi, clk_max, clk_output_name[lqspi], NULL, 368 SLCR_LQSPI_CLK_CTRL, periph_parents, 0); 369 370 zynq_clk_register_periph_clk(smc, clk_max, clk_output_name[smc], NULL, 371 SLCR_SMC_CLK_CTRL, periph_parents, 0); 372 373 zynq_clk_register_periph_clk(pcap, clk_max, clk_output_name[pcap], NULL, 374 SLCR_PCAP_CLK_CTRL, periph_parents, 0); 375 376 zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0], 377 clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL, 378 periph_parents, 1); 379 380 zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0], 381 clk_output_name[uart1], SLCR_UART_CLK_CTRL, 382 periph_parents, 1); 383 384 zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0], 385 clk_output_name[spi1], SLCR_SPI_CLK_CTRL, 386 periph_parents, 1); 387 388 for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) { 389 int idx = of_property_match_string(np, "clock-names", 390 gem0_emio_input_names[i]); 391 if (idx >= 0) 392 gem0_mux_parents[i + 1] = of_clk_get_parent_name(np, 393 idx); 394 } 395 clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 396 CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0, 397 &gem0clk_lock); 398 clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, 399 SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 400 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); 401 clk_register_divider(NULL, "gem0_div1", "gem0_div0", 402 CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, 403 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 404 &gem0clk_lock); 405 clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 406 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 407 SLCR_GEM0_CLK_CTRL, 6, 1, 0, 408 &gem0clk_lock); 409 clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], 410 "gem0_emio_mux", CLK_SET_RATE_PARENT, 411 SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock); 412 413 for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) { 414 int idx = of_property_match_string(np, "clock-names", 415 gem1_emio_input_names[i]); 416 if (idx >= 0) 417 gem1_mux_parents[i + 1] = of_clk_get_parent_name(np, 418 idx); 419 } 420 clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 421 CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0, 422 &gem1clk_lock); 423 clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, 424 SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 425 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); 426 clk_register_divider(NULL, "gem1_div1", "gem1_div0", 427 CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6, 428 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 429 &gem1clk_lock); 430 clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 431 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 432 SLCR_GEM1_CLK_CTRL, 6, 1, 0, 433 &gem1clk_lock); 434 clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], 435 "gem1_emio_mux", CLK_SET_RATE_PARENT, 436 SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock); 437 438 for (i = 0; i < NUM_MIO_PINS; i++) { 439 int idx; 440 441 snprintf(clk_name, CLK_NAME_LEN, "mio_clk_%2.2d", i); 442 idx = of_property_match_string(np, "clock-names", clk_name); 443 if (idx >= 0) 444 can_mio_mux_parents[i] = of_clk_get_parent_name(np, 445 idx); 446 else 447 can_mio_mux_parents[i] = dummy_nm; 448 } 449 clk_register_mux(NULL, "can_mux", periph_parents, 4, 450 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0, 451 &canclk_lock); 452 clk_register_divider(NULL, "can_div0", "can_mux", 0, 453 SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 454 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); 455 clk_register_divider(NULL, "can_div1", "can_div0", 456 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6, 457 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 458 &canclk_lock); 459 clk_register_gate(NULL, "can0_gate", "can_div1", 460 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0, 461 &canclk_lock); 462 clk_register_gate(NULL, "can1_gate", "can_div1", 463 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0, 464 &canclk_lock); 465 clk_register_mux(NULL, "can0_mio_mux", 466 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | 467 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, 468 &canmioclk_lock); 469 clk_register_mux(NULL, "can1_mio_mux", 470 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | 471 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6, 472 0, &canmioclk_lock); 473 clks[can0] = clk_register_mux(NULL, clk_output_name[can0], 474 can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | 475 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, 476 &canmioclk_lock); 477 clks[can1] = clk_register_mux(NULL, clk_output_name[can1], 478 can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | 479 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1, 480 0, &canmioclk_lock); 481 482 for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) { 483 int idx = of_property_match_string(np, "clock-names", 484 dbgtrc_emio_input_names[i]); 485 if (idx >= 0) 486 dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np, 487 idx); 488 } 489 clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 490 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0, 491 &dbgclk_lock); 492 clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, 493 SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 494 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); 495 clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 496 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0, 497 &dbgclk_lock); 498 clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc], 499 "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL, 500 0, 0, &dbgclk_lock); 501 clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb], 502 clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0, 503 &dbgclk_lock); 504 505 /* leave debug clocks in the state the bootloader set them up to */ 506 tmp = readl(SLCR_DBG_CLK_CTRL); 507 if (tmp & DBG_CLK_CTRL_CLKACT_TRC) 508 if (clk_prepare_enable(clks[dbg_trc])) 509 pr_warn("%s: trace clk enable failed\n", __func__); 510 if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT) 511 if (clk_prepare_enable(clks[dbg_apb])) 512 pr_warn("%s: debug APB clk enable failed\n", __func__); 513 514 /* One gated clock for all APER clocks. */ 515 clks[dma] = clk_register_gate(NULL, clk_output_name[dma], 516 clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0, 517 &aperclk_lock); 518 clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper], 519 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0, 520 &aperclk_lock); 521 clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper], 522 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0, 523 &aperclk_lock); 524 clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper], 525 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0, 526 &aperclk_lock); 527 clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper], 528 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0, 529 &aperclk_lock); 530 clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper], 531 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0, 532 &aperclk_lock); 533 clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper], 534 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0, 535 &aperclk_lock); 536 clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper], 537 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0, 538 &aperclk_lock); 539 clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper], 540 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0, 541 &aperclk_lock); 542 clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper], 543 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0, 544 &aperclk_lock); 545 clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper], 546 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0, 547 &aperclk_lock); 548 clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper], 549 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0, 550 &aperclk_lock); 551 clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper], 552 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0, 553 &aperclk_lock); 554 clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper], 555 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0, 556 &aperclk_lock); 557 clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper], 558 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0, 559 &aperclk_lock); 560 clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper], 561 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0, 562 &aperclk_lock); 563 clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper], 564 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0, 565 &aperclk_lock); 566 clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper], 567 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0, 568 &aperclk_lock); 569 570 for (i = 0; i < ARRAY_SIZE(clks); i++) { 571 if (IS_ERR(clks[i])) { 572 pr_err("Zynq clk %d: register failed with %ld\n", 573 i, PTR_ERR(clks[i])); 574 BUG(); 575 } 576 } 577 578 clk_data.clks = clks; 579 clk_data.clk_num = ARRAY_SIZE(clks); 580 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 581 } 582 583 CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup); 584 585 void __init zynq_clock_init(void) 586 { 587 struct device_node *np; 588 struct device_node *slcr; 589 struct resource res; 590 591 np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc"); 592 if (!np) { 593 pr_err("%s: clkc node not found\n", __func__); 594 goto np_err; 595 } 596 597 if (of_address_to_resource(np, 0, &res)) { 598 pr_err("%pOFn: failed to get resource\n", np); 599 goto np_err; 600 } 601 602 slcr = of_get_parent(np); 603 604 if (slcr->data) { 605 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; 606 } else { 607 pr_err("%pOFn: Unable to get I/O memory\n", np); 608 of_node_put(slcr); 609 goto np_err; 610 } 611 612 pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base); 613 614 of_node_put(slcr); 615 of_node_put(np); 616 617 return; 618 619 np_err: 620 of_node_put(np); 621 BUG(); 622 } 623