1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Xilinx 'Clocking Wizard' driver 4 * 5 * Copyright (C) 2013 - 2021 Xilinx 6 * 7 * Sören Brinkmann <soren.brinkmann@xilinx.com> 8 * 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/platform_device.h> 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/slab.h> 16 #include <linux/io.h> 17 #include <linux/of.h> 18 #include <linux/math64.h> 19 #include <linux/module.h> 20 #include <linux/err.h> 21 #include <linux/iopoll.h> 22 23 #define WZRD_NUM_OUTPUTS 7 24 #define WZRD_ACLK_MAX_FREQ 250000000UL 25 26 #define WZRD_CLK_CFG_REG(n) (0x200 + 4 * (n)) 27 28 #define WZRD_CLKOUT0_FRAC_EN BIT(18) 29 #define WZRD_CLKFBOUT_FRAC_EN BIT(26) 30 31 #define WZRD_CLKFBOUT_MULT_SHIFT 8 32 #define WZRD_CLKFBOUT_MULT_MASK (0xff << WZRD_CLKFBOUT_MULT_SHIFT) 33 #define WZRD_CLKFBOUT_FRAC_SHIFT 16 34 #define WZRD_CLKFBOUT_FRAC_MASK (0x3ff << WZRD_CLKFBOUT_FRAC_SHIFT) 35 #define WZRD_DIVCLK_DIVIDE_SHIFT 0 36 #define WZRD_DIVCLK_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT) 37 #define WZRD_CLKOUT_DIVIDE_SHIFT 0 38 #define WZRD_CLKOUT_DIVIDE_WIDTH 8 39 #define WZRD_CLKOUT_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT) 40 #define WZRD_CLKOUT_FRAC_SHIFT 8 41 #define WZRD_CLKOUT_FRAC_MASK 0x3ff 42 #define WZRD_CLKOUT0_FRAC_MASK GENMASK(17, 8) 43 44 #define WZRD_DR_MAX_INT_DIV_VALUE 255 45 #define WZRD_DR_STATUS_REG_OFFSET 0x04 46 #define WZRD_DR_LOCK_BIT_MASK 0x00000001 47 #define WZRD_DR_INIT_REG_OFFSET 0x25C 48 #define WZRD_DR_DIV_TO_PHASE_OFFSET 4 49 #define WZRD_DR_BEGIN_DYNA_RECONF 0x03 50 #define WZRD_DR_BEGIN_DYNA_RECONF_5_2 0x07 51 #define WZRD_DR_BEGIN_DYNA_RECONF1_5_2 0x02 52 53 #define WZRD_USEC_POLL 10 54 #define WZRD_TIMEOUT_POLL 1000 55 56 /* Divider limits, from UG572 Table 3-4 for Ultrascale+ */ 57 #define DIV_O 0x01 58 #define DIV_ALL 0x03 59 60 #define WZRD_M_MIN 2 61 #define WZRD_M_MAX 128 62 #define WZRD_D_MIN 1 63 #define WZRD_D_MAX 106 64 #define WZRD_VCO_MIN 800000000 65 #define WZRD_VCO_MAX 1600000000 66 #define WZRD_O_MIN 1 67 #define WZRD_O_MAX 128 68 #define WZRD_MIN_ERR 20000 69 #define WZRD_FRAC_POINTS 1000 70 71 /* Get the mask from width */ 72 #define div_mask(width) ((1 << (width)) - 1) 73 74 /* Extract divider instance from clock hardware instance */ 75 #define to_clk_wzrd_divider(_hw) container_of(_hw, struct clk_wzrd_divider, hw) 76 77 enum clk_wzrd_int_clks { 78 wzrd_clk_mul, 79 wzrd_clk_mul_div, 80 wzrd_clk_mul_frac, 81 wzrd_clk_int_max 82 }; 83 84 /** 85 * struct clk_wzrd - Clock wizard private data structure 86 * 87 * @clk_data: Clock data 88 * @nb: Notifier block 89 * @base: Memory base 90 * @clk_in1: Handle to input clock 'clk_in1' 91 * @axi_clk: Handle to input clock 's_axi_aclk' 92 * @clks_internal: Internal clocks 93 * @clkout: Output clocks 94 * @speed_grade: Speed grade of the device 95 * @suspended: Flag indicating power state of the device 96 */ 97 struct clk_wzrd { 98 struct clk_onecell_data clk_data; 99 struct notifier_block nb; 100 void __iomem *base; 101 struct clk *clk_in1; 102 struct clk *axi_clk; 103 struct clk *clks_internal[wzrd_clk_int_max]; 104 struct clk *clkout[WZRD_NUM_OUTPUTS]; 105 unsigned int speed_grade; 106 bool suspended; 107 }; 108 109 /** 110 * struct clk_wzrd_divider - clock divider specific to clk_wzrd 111 * 112 * @hw: handle between common and hardware-specific interfaces 113 * @base: base address of register containing the divider 114 * @offset: offset address of register containing the divider 115 * @shift: shift to the divider bit field 116 * @width: width of the divider bit field 117 * @flags: clk_wzrd divider flags 118 * @table: array of value/divider pairs, last entry should have div = 0 119 * @m: value of the multiplier 120 * @d: value of the common divider 121 * @o: value of the leaf divider 122 * @lock: register lock 123 */ 124 struct clk_wzrd_divider { 125 struct clk_hw hw; 126 void __iomem *base; 127 u16 offset; 128 u8 shift; 129 u8 width; 130 u8 flags; 131 const struct clk_div_table *table; 132 u32 m; 133 u32 d; 134 u32 o; 135 spinlock_t *lock; /* divider lock */ 136 }; 137 138 #define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb) 139 140 /* maximum frequencies for input/output clocks per speed grade */ 141 static const unsigned long clk_wzrd_max_freq[] = { 142 800000000UL, 143 933000000UL, 144 1066000000UL 145 }; 146 147 /* spin lock variable for clk_wzrd */ 148 static DEFINE_SPINLOCK(clkwzrd_lock); 149 150 static unsigned long clk_wzrd_recalc_rate(struct clk_hw *hw, 151 unsigned long parent_rate) 152 { 153 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); 154 void __iomem *div_addr = divider->base + divider->offset; 155 unsigned int val; 156 157 val = readl(div_addr) >> divider->shift; 158 val &= div_mask(divider->width); 159 160 return divider_recalc_rate(hw, parent_rate, val, divider->table, 161 divider->flags, divider->width); 162 } 163 164 static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate, 165 unsigned long parent_rate) 166 { 167 int err; 168 u32 value; 169 unsigned long flags = 0; 170 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); 171 void __iomem *div_addr = divider->base + divider->offset; 172 173 if (divider->lock) 174 spin_lock_irqsave(divider->lock, flags); 175 else 176 __acquire(divider->lock); 177 178 value = DIV_ROUND_CLOSEST(parent_rate, rate); 179 180 /* Cap the value to max */ 181 min_t(u32, value, WZRD_DR_MAX_INT_DIV_VALUE); 182 183 /* Set divisor and clear phase offset */ 184 writel(value, div_addr); 185 writel(0x00, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET); 186 187 /* Check status register */ 188 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, 189 value, value & WZRD_DR_LOCK_BIT_MASK, 190 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); 191 if (err) 192 goto err_reconfig; 193 194 /* Initiate reconfiguration */ 195 writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2, 196 divider->base + WZRD_DR_INIT_REG_OFFSET); 197 writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2, 198 divider->base + WZRD_DR_INIT_REG_OFFSET); 199 200 /* Check status register */ 201 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, 202 value, value & WZRD_DR_LOCK_BIT_MASK, 203 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); 204 err_reconfig: 205 if (divider->lock) 206 spin_unlock_irqrestore(divider->lock, flags); 207 else 208 __release(divider->lock); 209 return err; 210 } 211 212 static long clk_wzrd_round_rate(struct clk_hw *hw, unsigned long rate, 213 unsigned long *prate) 214 { 215 u8 div; 216 217 /* 218 * since we don't change parent rate we just round rate to closest 219 * achievable 220 */ 221 div = DIV_ROUND_CLOSEST(*prate, rate); 222 223 return *prate / div; 224 } 225 226 static int clk_wzrd_get_divisors(struct clk_hw *hw, unsigned long rate, 227 unsigned long parent_rate) 228 { 229 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); 230 unsigned long vco_freq, freq, diff; 231 u32 m, d, o; 232 233 for (m = WZRD_M_MIN; m <= WZRD_M_MAX; m++) { 234 for (d = WZRD_D_MIN; d <= WZRD_D_MAX; d++) { 235 vco_freq = DIV_ROUND_CLOSEST((parent_rate * m), d); 236 if (vco_freq >= WZRD_VCO_MIN && vco_freq <= WZRD_VCO_MAX) { 237 for (o = WZRD_O_MIN; o <= WZRD_O_MAX; o++) { 238 freq = DIV_ROUND_CLOSEST_ULL(vco_freq, o); 239 diff = abs(freq - rate); 240 241 if (diff < WZRD_MIN_ERR) { 242 divider->m = m; 243 divider->d = d; 244 divider->o = o; 245 return 0; 246 } 247 } 248 } 249 } 250 } 251 return -EBUSY; 252 } 253 254 static int clk_wzrd_dynamic_all_nolock(struct clk_hw *hw, unsigned long rate, 255 unsigned long parent_rate) 256 { 257 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); 258 unsigned long vco_freq, rate_div, clockout0_div; 259 u32 reg, pre, value, f; 260 int err; 261 262 err = clk_wzrd_get_divisors(hw, rate, parent_rate); 263 if (err) 264 return err; 265 266 vco_freq = DIV_ROUND_CLOSEST(parent_rate * divider->m, divider->d); 267 rate_div = DIV_ROUND_CLOSEST_ULL((vco_freq * WZRD_FRAC_POINTS), rate); 268 269 clockout0_div = div_u64(rate_div, WZRD_FRAC_POINTS); 270 271 pre = DIV_ROUND_CLOSEST_ULL(vco_freq * WZRD_FRAC_POINTS, rate); 272 f = (pre - (clockout0_div * WZRD_FRAC_POINTS)); 273 f &= WZRD_CLKOUT_FRAC_MASK; 274 275 reg = FIELD_PREP(WZRD_CLKOUT_DIVIDE_MASK, clockout0_div) | 276 FIELD_PREP(WZRD_CLKOUT0_FRAC_MASK, f); 277 278 writel(reg, divider->base + WZRD_CLK_CFG_REG(2)); 279 /* Set divisor and clear phase offset */ 280 reg = FIELD_PREP(WZRD_CLKFBOUT_MULT_MASK, divider->m) | 281 FIELD_PREP(WZRD_DIVCLK_DIVIDE_MASK, divider->d); 282 writel(reg, divider->base + WZRD_CLK_CFG_REG(0)); 283 writel(divider->o, divider->base + WZRD_CLK_CFG_REG(2)); 284 writel(0, divider->base + WZRD_CLK_CFG_REG(3)); 285 /* Check status register */ 286 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value, 287 value & WZRD_DR_LOCK_BIT_MASK, 288 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); 289 if (err) 290 return -ETIMEDOUT; 291 292 /* Initiate reconfiguration */ 293 writel(WZRD_DR_BEGIN_DYNA_RECONF, 294 divider->base + WZRD_DR_INIT_REG_OFFSET); 295 296 /* Check status register */ 297 return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value, 298 value & WZRD_DR_LOCK_BIT_MASK, 299 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); 300 } 301 302 static int clk_wzrd_dynamic_all(struct clk_hw *hw, unsigned long rate, 303 unsigned long parent_rate) 304 { 305 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); 306 unsigned long flags = 0; 307 int ret; 308 309 spin_lock_irqsave(divider->lock, flags); 310 311 ret = clk_wzrd_dynamic_all_nolock(hw, rate, parent_rate); 312 313 spin_unlock_irqrestore(divider->lock, flags); 314 315 return ret; 316 } 317 318 static unsigned long clk_wzrd_recalc_rate_all(struct clk_hw *hw, 319 unsigned long parent_rate) 320 { 321 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); 322 u32 m, d, o, div, reg, f; 323 324 reg = readl(divider->base + WZRD_CLK_CFG_REG(0)); 325 d = FIELD_GET(WZRD_DIVCLK_DIVIDE_MASK, reg); 326 m = FIELD_GET(WZRD_CLKFBOUT_MULT_MASK, reg); 327 reg = readl(divider->base + WZRD_CLK_CFG_REG(2)); 328 o = FIELD_GET(WZRD_DIVCLK_DIVIDE_MASK, reg); 329 f = FIELD_GET(WZRD_CLKOUT0_FRAC_MASK, reg); 330 331 div = DIV_ROUND_CLOSEST(d * (WZRD_FRAC_POINTS * o + f), WZRD_FRAC_POINTS); 332 return divider_recalc_rate(hw, parent_rate * m, div, divider->table, 333 divider->flags, divider->width); 334 } 335 336 static long clk_wzrd_round_rate_all(struct clk_hw *hw, unsigned long rate, 337 unsigned long *prate) 338 { 339 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); 340 unsigned long int_freq; 341 u32 m, d, o, div, f; 342 int err; 343 344 err = clk_wzrd_get_divisors(hw, rate, *prate); 345 if (err) 346 return err; 347 348 m = divider->m; 349 d = divider->d; 350 o = divider->o; 351 352 div = d * o; 353 int_freq = divider_recalc_rate(hw, *prate * m, div, divider->table, 354 divider->flags, divider->width); 355 356 if (rate > int_freq) { 357 f = DIV_ROUND_CLOSEST_ULL(rate * WZRD_FRAC_POINTS, int_freq); 358 rate = DIV_ROUND_CLOSEST(int_freq * f, WZRD_FRAC_POINTS); 359 } 360 return rate; 361 } 362 363 static const struct clk_ops clk_wzrd_clk_divider_ops = { 364 .round_rate = clk_wzrd_round_rate, 365 .set_rate = clk_wzrd_dynamic_reconfig, 366 .recalc_rate = clk_wzrd_recalc_rate, 367 }; 368 369 static const struct clk_ops clk_wzrd_clk_div_all_ops = { 370 .round_rate = clk_wzrd_round_rate_all, 371 .set_rate = clk_wzrd_dynamic_all, 372 .recalc_rate = clk_wzrd_recalc_rate_all, 373 }; 374 375 static unsigned long clk_wzrd_recalc_ratef(struct clk_hw *hw, 376 unsigned long parent_rate) 377 { 378 unsigned int val; 379 u32 div, frac; 380 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); 381 void __iomem *div_addr = divider->base + divider->offset; 382 383 val = readl(div_addr); 384 div = val & div_mask(divider->width); 385 frac = (val >> WZRD_CLKOUT_FRAC_SHIFT) & WZRD_CLKOUT_FRAC_MASK; 386 387 return mult_frac(parent_rate, 1000, (div * 1000) + frac); 388 } 389 390 static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate, 391 unsigned long parent_rate) 392 { 393 int err; 394 u32 value, pre; 395 unsigned long rate_div, f, clockout0_div; 396 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); 397 void __iomem *div_addr = divider->base + divider->offset; 398 399 rate_div = DIV_ROUND_DOWN_ULL(parent_rate * 1000, rate); 400 clockout0_div = rate_div / 1000; 401 402 pre = DIV_ROUND_CLOSEST((parent_rate * 1000), rate); 403 f = (u32)(pre - (clockout0_div * 1000)); 404 f = f & WZRD_CLKOUT_FRAC_MASK; 405 f = f << WZRD_CLKOUT_DIVIDE_WIDTH; 406 407 value = (f | (clockout0_div & WZRD_CLKOUT_DIVIDE_MASK)); 408 409 /* Set divisor and clear phase offset */ 410 writel(value, div_addr); 411 writel(0x0, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET); 412 413 /* Check status register */ 414 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value, 415 value & WZRD_DR_LOCK_BIT_MASK, 416 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); 417 if (err) 418 return err; 419 420 /* Initiate reconfiguration */ 421 writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2, 422 divider->base + WZRD_DR_INIT_REG_OFFSET); 423 writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2, 424 divider->base + WZRD_DR_INIT_REG_OFFSET); 425 426 /* Check status register */ 427 return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value, 428 value & WZRD_DR_LOCK_BIT_MASK, 429 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL); 430 } 431 432 static long clk_wzrd_round_rate_f(struct clk_hw *hw, unsigned long rate, 433 unsigned long *prate) 434 { 435 return rate; 436 } 437 438 static const struct clk_ops clk_wzrd_clk_divider_ops_f = { 439 .round_rate = clk_wzrd_round_rate_f, 440 .set_rate = clk_wzrd_dynamic_reconfig_f, 441 .recalc_rate = clk_wzrd_recalc_ratef, 442 }; 443 444 static struct clk *clk_wzrd_register_divf(struct device *dev, 445 const char *name, 446 const char *parent_name, 447 unsigned long flags, 448 void __iomem *base, u16 offset, 449 u8 shift, u8 width, 450 u8 clk_divider_flags, 451 u32 div_type, 452 spinlock_t *lock) 453 { 454 struct clk_wzrd_divider *div; 455 struct clk_hw *hw; 456 struct clk_init_data init; 457 int ret; 458 459 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); 460 if (!div) 461 return ERR_PTR(-ENOMEM); 462 463 init.name = name; 464 465 init.ops = &clk_wzrd_clk_divider_ops_f; 466 467 init.flags = flags; 468 init.parent_names = &parent_name; 469 init.num_parents = 1; 470 471 div->base = base; 472 div->offset = offset; 473 div->shift = shift; 474 div->width = width; 475 div->flags = clk_divider_flags; 476 div->lock = lock; 477 div->hw.init = &init; 478 479 hw = &div->hw; 480 ret = devm_clk_hw_register(dev, hw); 481 if (ret) 482 return ERR_PTR(ret); 483 484 return hw->clk; 485 } 486 487 static struct clk *clk_wzrd_register_divider(struct device *dev, 488 const char *name, 489 const char *parent_name, 490 unsigned long flags, 491 void __iomem *base, u16 offset, 492 u8 shift, u8 width, 493 u8 clk_divider_flags, 494 u32 div_type, 495 spinlock_t *lock) 496 { 497 struct clk_wzrd_divider *div; 498 struct clk_hw *hw; 499 struct clk_init_data init; 500 int ret; 501 502 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); 503 if (!div) 504 return ERR_PTR(-ENOMEM); 505 506 init.name = name; 507 if (clk_divider_flags & CLK_DIVIDER_READ_ONLY) 508 init.ops = &clk_divider_ro_ops; 509 else if (div_type == DIV_O) 510 init.ops = &clk_wzrd_clk_divider_ops; 511 else 512 init.ops = &clk_wzrd_clk_div_all_ops; 513 init.flags = flags; 514 init.parent_names = &parent_name; 515 init.num_parents = 1; 516 517 div->base = base; 518 div->offset = offset; 519 div->shift = shift; 520 div->width = width; 521 div->flags = clk_divider_flags; 522 div->lock = lock; 523 div->hw.init = &init; 524 525 hw = &div->hw; 526 ret = devm_clk_hw_register(dev, hw); 527 if (ret) 528 hw = ERR_PTR(ret); 529 530 return hw->clk; 531 } 532 533 static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event, 534 void *data) 535 { 536 unsigned long max; 537 struct clk_notifier_data *ndata = data; 538 struct clk_wzrd *clk_wzrd = to_clk_wzrd(nb); 539 540 if (clk_wzrd->suspended) 541 return NOTIFY_OK; 542 543 if (ndata->clk == clk_wzrd->clk_in1) 544 max = clk_wzrd_max_freq[clk_wzrd->speed_grade - 1]; 545 else if (ndata->clk == clk_wzrd->axi_clk) 546 max = WZRD_ACLK_MAX_FREQ; 547 else 548 return NOTIFY_DONE; /* should never happen */ 549 550 switch (event) { 551 case PRE_RATE_CHANGE: 552 if (ndata->new_rate > max) 553 return NOTIFY_BAD; 554 return NOTIFY_OK; 555 case POST_RATE_CHANGE: 556 case ABORT_RATE_CHANGE: 557 default: 558 return NOTIFY_DONE; 559 } 560 } 561 562 static int __maybe_unused clk_wzrd_suspend(struct device *dev) 563 { 564 struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev); 565 566 clk_disable_unprepare(clk_wzrd->axi_clk); 567 clk_wzrd->suspended = true; 568 569 return 0; 570 } 571 572 static int __maybe_unused clk_wzrd_resume(struct device *dev) 573 { 574 int ret; 575 struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev); 576 577 ret = clk_prepare_enable(clk_wzrd->axi_clk); 578 if (ret) { 579 dev_err(dev, "unable to enable s_axi_aclk\n"); 580 return ret; 581 } 582 583 clk_wzrd->suspended = false; 584 585 return 0; 586 } 587 588 static SIMPLE_DEV_PM_OPS(clk_wzrd_dev_pm_ops, clk_wzrd_suspend, 589 clk_wzrd_resume); 590 591 static int clk_wzrd_probe(struct platform_device *pdev) 592 { 593 int i, ret; 594 u32 reg, reg_f, mult; 595 unsigned long rate; 596 const char *clk_name; 597 void __iomem *ctrl_reg; 598 struct clk_wzrd *clk_wzrd; 599 const char *clkout_name; 600 struct device_node *np = pdev->dev.of_node; 601 int nr_outputs; 602 unsigned long flags = 0; 603 604 clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL); 605 if (!clk_wzrd) 606 return -ENOMEM; 607 platform_set_drvdata(pdev, clk_wzrd); 608 609 clk_wzrd->base = devm_platform_ioremap_resource(pdev, 0); 610 if (IS_ERR(clk_wzrd->base)) 611 return PTR_ERR(clk_wzrd->base); 612 613 ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade); 614 if (!ret) { 615 if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) { 616 dev_warn(&pdev->dev, "invalid speed grade '%d'\n", 617 clk_wzrd->speed_grade); 618 clk_wzrd->speed_grade = 0; 619 } 620 } 621 622 clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1"); 623 if (IS_ERR(clk_wzrd->clk_in1)) 624 return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1), 625 "clk_in1 not found\n"); 626 627 clk_wzrd->axi_clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); 628 if (IS_ERR(clk_wzrd->axi_clk)) 629 return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk), 630 "s_axi_aclk not found\n"); 631 ret = clk_prepare_enable(clk_wzrd->axi_clk); 632 if (ret) { 633 dev_err(&pdev->dev, "enabling s_axi_aclk failed\n"); 634 return ret; 635 } 636 rate = clk_get_rate(clk_wzrd->axi_clk); 637 if (rate > WZRD_ACLK_MAX_FREQ) { 638 dev_err(&pdev->dev, "s_axi_aclk frequency (%lu) too high\n", 639 rate); 640 ret = -EINVAL; 641 goto err_disable_clk; 642 } 643 644 ret = of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs); 645 if (ret || nr_outputs > WZRD_NUM_OUTPUTS) { 646 ret = -EINVAL; 647 goto err_disable_clk; 648 } 649 650 clkout_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_out0", dev_name(&pdev->dev)); 651 if (nr_outputs == 1) { 652 clk_wzrd->clkout[0] = clk_wzrd_register_divider 653 (&pdev->dev, clkout_name, 654 __clk_get_name(clk_wzrd->clk_in1), 0, 655 clk_wzrd->base, WZRD_CLK_CFG_REG(3), 656 WZRD_CLKOUT_DIVIDE_SHIFT, 657 WZRD_CLKOUT_DIVIDE_WIDTH, 658 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 659 DIV_ALL, &clkwzrd_lock); 660 661 goto out; 662 } 663 664 reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)); 665 reg_f = reg & WZRD_CLKFBOUT_FRAC_MASK; 666 reg_f = reg_f >> WZRD_CLKFBOUT_FRAC_SHIFT; 667 668 reg = reg & WZRD_CLKFBOUT_MULT_MASK; 669 reg = reg >> WZRD_CLKFBOUT_MULT_SHIFT; 670 mult = (reg * 1000) + reg_f; 671 clk_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_mul", dev_name(&pdev->dev)); 672 if (!clk_name) { 673 ret = -ENOMEM; 674 goto err_disable_clk; 675 } 676 clk_wzrd->clks_internal[wzrd_clk_mul] = clk_register_fixed_factor 677 (&pdev->dev, clk_name, 678 __clk_get_name(clk_wzrd->clk_in1), 679 0, mult, 1000); 680 if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul])) { 681 dev_err(&pdev->dev, "unable to register fixed-factor clock\n"); 682 ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul]); 683 goto err_disable_clk; 684 } 685 686 clk_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev)); 687 if (!clk_name) { 688 ret = -ENOMEM; 689 goto err_rm_int_clk; 690 } 691 692 ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(0); 693 /* register div */ 694 clk_wzrd->clks_internal[wzrd_clk_mul_div] = clk_register_divider 695 (&pdev->dev, clk_name, 696 __clk_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]), 697 flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED | 698 CLK_DIVIDER_ALLOW_ZERO, &clkwzrd_lock); 699 if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) { 700 dev_err(&pdev->dev, "unable to register divider clock\n"); 701 ret = PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]); 702 goto err_rm_int_clk; 703 } 704 705 /* register div per output */ 706 for (i = nr_outputs - 1; i >= 0 ; i--) { 707 clkout_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, 708 "%s_out%d", dev_name(&pdev->dev), i); 709 if (!clkout_name) { 710 ret = -ENOMEM; 711 goto err_rm_int_clk; 712 } 713 714 if (!i) 715 clk_wzrd->clkout[i] = clk_wzrd_register_divf 716 (&pdev->dev, clkout_name, 717 clk_name, flags, 718 clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12), 719 WZRD_CLKOUT_DIVIDE_SHIFT, 720 WZRD_CLKOUT_DIVIDE_WIDTH, 721 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 722 DIV_O, &clkwzrd_lock); 723 else 724 clk_wzrd->clkout[i] = clk_wzrd_register_divider 725 (&pdev->dev, clkout_name, 726 clk_name, 0, 727 clk_wzrd->base, (WZRD_CLK_CFG_REG(2) + i * 12), 728 WZRD_CLKOUT_DIVIDE_SHIFT, 729 WZRD_CLKOUT_DIVIDE_WIDTH, 730 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 731 DIV_O, &clkwzrd_lock); 732 if (IS_ERR(clk_wzrd->clkout[i])) { 733 int j; 734 735 for (j = i + 1; j < nr_outputs; j++) 736 clk_unregister(clk_wzrd->clkout[j]); 737 dev_err(&pdev->dev, 738 "unable to register divider clock\n"); 739 ret = PTR_ERR(clk_wzrd->clkout[i]); 740 goto err_rm_int_clks; 741 } 742 } 743 744 out: 745 clk_wzrd->clk_data.clks = clk_wzrd->clkout; 746 clk_wzrd->clk_data.clk_num = ARRAY_SIZE(clk_wzrd->clkout); 747 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_wzrd->clk_data); 748 749 if (clk_wzrd->speed_grade) { 750 clk_wzrd->nb.notifier_call = clk_wzrd_clk_notifier; 751 752 ret = clk_notifier_register(clk_wzrd->clk_in1, 753 &clk_wzrd->nb); 754 if (ret) 755 dev_warn(&pdev->dev, 756 "unable to register clock notifier\n"); 757 758 ret = clk_notifier_register(clk_wzrd->axi_clk, &clk_wzrd->nb); 759 if (ret) 760 dev_warn(&pdev->dev, 761 "unable to register clock notifier\n"); 762 } 763 764 return 0; 765 766 err_rm_int_clks: 767 clk_unregister(clk_wzrd->clks_internal[1]); 768 err_rm_int_clk: 769 clk_unregister(clk_wzrd->clks_internal[0]); 770 err_disable_clk: 771 clk_disable_unprepare(clk_wzrd->axi_clk); 772 773 return ret; 774 } 775 776 static void clk_wzrd_remove(struct platform_device *pdev) 777 { 778 int i; 779 struct clk_wzrd *clk_wzrd = platform_get_drvdata(pdev); 780 781 of_clk_del_provider(pdev->dev.of_node); 782 783 for (i = 0; i < WZRD_NUM_OUTPUTS; i++) 784 clk_unregister(clk_wzrd->clkout[i]); 785 for (i = 0; i < wzrd_clk_int_max; i++) 786 clk_unregister(clk_wzrd->clks_internal[i]); 787 788 if (clk_wzrd->speed_grade) { 789 clk_notifier_unregister(clk_wzrd->axi_clk, &clk_wzrd->nb); 790 clk_notifier_unregister(clk_wzrd->clk_in1, &clk_wzrd->nb); 791 } 792 793 clk_disable_unprepare(clk_wzrd->axi_clk); 794 } 795 796 static const struct of_device_id clk_wzrd_ids[] = { 797 { .compatible = "xlnx,clocking-wizard" }, 798 { .compatible = "xlnx,clocking-wizard-v5.2" }, 799 { .compatible = "xlnx,clocking-wizard-v6.0" }, 800 { }, 801 }; 802 MODULE_DEVICE_TABLE(of, clk_wzrd_ids); 803 804 static struct platform_driver clk_wzrd_driver = { 805 .driver = { 806 .name = "clk-wizard", 807 .of_match_table = clk_wzrd_ids, 808 .pm = &clk_wzrd_dev_pm_ops, 809 }, 810 .probe = clk_wzrd_probe, 811 .remove_new = clk_wzrd_remove, 812 }; 813 module_platform_driver(clk_wzrd_driver); 814 815 MODULE_LICENSE("GPL"); 816 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com"); 817 MODULE_DESCRIPTION("Driver for the Xilinx Clocking Wizard IP core"); 818