1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 Socionext Inc. 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/init.h> 9 #include <linux/mfd/syscon.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 14 #include "clk-uniphier.h" 15 16 static struct clk_hw *uniphier_clk_register(struct device *dev, 17 struct regmap *regmap, 18 const struct uniphier_clk_data *data) 19 { 20 switch (data->type) { 21 case UNIPHIER_CLK_TYPE_CPUGEAR: 22 return uniphier_clk_register_cpugear(dev, regmap, data->name, 23 &data->data.cpugear); 24 case UNIPHIER_CLK_TYPE_FIXED_FACTOR: 25 return uniphier_clk_register_fixed_factor(dev, data->name, 26 &data->data.factor); 27 case UNIPHIER_CLK_TYPE_FIXED_RATE: 28 return uniphier_clk_register_fixed_rate(dev, data->name, 29 &data->data.rate); 30 case UNIPHIER_CLK_TYPE_GATE: 31 return uniphier_clk_register_gate(dev, regmap, data->name, 32 &data->data.gate); 33 case UNIPHIER_CLK_TYPE_MUX: 34 return uniphier_clk_register_mux(dev, regmap, data->name, 35 &data->data.mux); 36 default: 37 dev_err(dev, "unsupported clock type\n"); 38 return ERR_PTR(-EINVAL); 39 } 40 } 41 42 static int uniphier_clk_probe(struct platform_device *pdev) 43 { 44 struct device *dev = &pdev->dev; 45 struct clk_hw_onecell_data *hw_data; 46 const struct uniphier_clk_data *p, *data; 47 struct regmap *regmap; 48 struct device_node *parent; 49 int clk_num = 0; 50 51 data = of_device_get_match_data(dev); 52 if (WARN_ON(!data)) 53 return -EINVAL; 54 55 parent = of_get_parent(dev->of_node); /* parent should be syscon node */ 56 regmap = syscon_node_to_regmap(parent); 57 of_node_put(parent); 58 if (IS_ERR(regmap)) { 59 dev_err(dev, "failed to get regmap (error %ld)\n", 60 PTR_ERR(regmap)); 61 return PTR_ERR(regmap); 62 } 63 64 for (p = data; p->name; p++) 65 clk_num = max(clk_num, p->idx + 1); 66 67 hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, clk_num), 68 GFP_KERNEL); 69 if (!hw_data) 70 return -ENOMEM; 71 72 hw_data->num = clk_num; 73 74 /* avoid returning NULL for unused idx */ 75 while (--clk_num >= 0) 76 hw_data->hws[clk_num] = ERR_PTR(-EINVAL); 77 78 for (p = data; p->name; p++) { 79 struct clk_hw *hw; 80 81 dev_dbg(dev, "register %s (index=%d)\n", p->name, p->idx); 82 hw = uniphier_clk_register(dev, regmap, p); 83 if (WARN(IS_ERR(hw), "failed to register %s", p->name)) 84 continue; 85 86 if (p->idx >= 0) 87 hw_data->hws[p->idx] = hw; 88 } 89 90 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, 91 hw_data); 92 } 93 94 static int uniphier_clk_remove(struct platform_device *pdev) 95 { 96 of_clk_del_provider(pdev->dev.of_node); 97 98 return 0; 99 } 100 101 static const struct of_device_id uniphier_clk_match[] = { 102 /* System clock */ 103 { 104 .compatible = "socionext,uniphier-ld4-clock", 105 .data = uniphier_ld4_sys_clk_data, 106 }, 107 { 108 .compatible = "socionext,uniphier-pro4-clock", 109 .data = uniphier_pro4_sys_clk_data, 110 }, 111 { 112 .compatible = "socionext,uniphier-sld8-clock", 113 .data = uniphier_sld8_sys_clk_data, 114 }, 115 { 116 .compatible = "socionext,uniphier-pro5-clock", 117 .data = uniphier_pro5_sys_clk_data, 118 }, 119 { 120 .compatible = "socionext,uniphier-pxs2-clock", 121 .data = uniphier_pxs2_sys_clk_data, 122 }, 123 { 124 .compatible = "socionext,uniphier-ld11-clock", 125 .data = uniphier_ld11_sys_clk_data, 126 }, 127 { 128 .compatible = "socionext,uniphier-ld20-clock", 129 .data = uniphier_ld20_sys_clk_data, 130 }, 131 { 132 .compatible = "socionext,uniphier-pxs3-clock", 133 .data = uniphier_pxs3_sys_clk_data, 134 }, 135 /* Media I/O clock, SD clock */ 136 { 137 .compatible = "socionext,uniphier-ld4-mio-clock", 138 .data = uniphier_ld4_mio_clk_data, 139 }, 140 { 141 .compatible = "socionext,uniphier-pro4-mio-clock", 142 .data = uniphier_ld4_mio_clk_data, 143 }, 144 { 145 .compatible = "socionext,uniphier-sld8-mio-clock", 146 .data = uniphier_ld4_mio_clk_data, 147 }, 148 { 149 .compatible = "socionext,uniphier-pro5-sd-clock", 150 .data = uniphier_pro5_sd_clk_data, 151 }, 152 { 153 .compatible = "socionext,uniphier-pxs2-sd-clock", 154 .data = uniphier_pro5_sd_clk_data, 155 }, 156 { 157 .compatible = "socionext,uniphier-ld11-mio-clock", 158 .data = uniphier_ld4_mio_clk_data, 159 }, 160 { 161 .compatible = "socionext,uniphier-ld20-sd-clock", 162 .data = uniphier_pro5_sd_clk_data, 163 }, 164 { 165 .compatible = "socionext,uniphier-pxs3-sd-clock", 166 .data = uniphier_pro5_sd_clk_data, 167 }, 168 /* Peripheral clock */ 169 { 170 .compatible = "socionext,uniphier-ld4-peri-clock", 171 .data = uniphier_ld4_peri_clk_data, 172 }, 173 { 174 .compatible = "socionext,uniphier-pro4-peri-clock", 175 .data = uniphier_pro4_peri_clk_data, 176 }, 177 { 178 .compatible = "socionext,uniphier-sld8-peri-clock", 179 .data = uniphier_ld4_peri_clk_data, 180 }, 181 { 182 .compatible = "socionext,uniphier-pro5-peri-clock", 183 .data = uniphier_pro4_peri_clk_data, 184 }, 185 { 186 .compatible = "socionext,uniphier-pxs2-peri-clock", 187 .data = uniphier_pro4_peri_clk_data, 188 }, 189 { 190 .compatible = "socionext,uniphier-ld11-peri-clock", 191 .data = uniphier_pro4_peri_clk_data, 192 }, 193 { 194 .compatible = "socionext,uniphier-ld20-peri-clock", 195 .data = uniphier_pro4_peri_clk_data, 196 }, 197 { 198 .compatible = "socionext,uniphier-pxs3-peri-clock", 199 .data = uniphier_pro4_peri_clk_data, 200 }, 201 { /* sentinel */ } 202 }; 203 204 static struct platform_driver uniphier_clk_driver = { 205 .probe = uniphier_clk_probe, 206 .remove = uniphier_clk_remove, 207 .driver = { 208 .name = "uniphier-clk", 209 .of_match_table = uniphier_clk_match, 210 }, 211 }; 212 builtin_platform_driver(uniphier_clk_driver); 213