1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * OMAP gate clock support 4 * 5 * Copyright (C) 2013 Texas Instruments, Inc. 6 * 7 * Tero Kristo <t-kristo@ti.com> 8 */ 9 10 #include <linux/clk-provider.h> 11 #include <linux/slab.h> 12 #include <linux/io.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/clk/ti.h> 16 17 #include "clock.h" 18 19 #undef pr_fmt 20 #define pr_fmt(fmt) "%s: " fmt, __func__ 21 22 static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk); 23 24 static const struct clk_ops omap_gate_clkdm_clk_ops = { 25 .init = &omap2_init_clk_clkdm, 26 .enable = &omap2_clkops_enable_clkdm, 27 .disable = &omap2_clkops_disable_clkdm, 28 .restore_context = clk_gate_restore_context, 29 }; 30 31 const struct clk_ops omap_gate_clk_ops = { 32 .init = &omap2_init_clk_clkdm, 33 .enable = &omap2_dflt_clk_enable, 34 .disable = &omap2_dflt_clk_disable, 35 .is_enabled = &omap2_dflt_clk_is_enabled, 36 .restore_context = clk_gate_restore_context, 37 }; 38 39 static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = { 40 .init = &omap2_init_clk_clkdm, 41 .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore, 42 .disable = &omap2_dflt_clk_disable, 43 .is_enabled = &omap2_dflt_clk_is_enabled, 44 .restore_context = clk_gate_restore_context, 45 }; 46 47 /** 48 * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering 49 * from HSDivider PWRDN problem Implements Errata ID: i556. 50 * @hw: DPLL output struct clk_hw 51 * 52 * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck, 53 * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset 54 * valueafter their respective PWRDN bits are set. Any dummy write 55 * (Any other value different from the Read value) to the 56 * corresponding CM_CLKSEL register will refresh the dividers. 57 */ 58 static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw) 59 { 60 struct clk_omap_divider *parent; 61 struct clk_hw *parent_hw; 62 u32 dummy_v, orig_v; 63 int ret; 64 65 /* Clear PWRDN bit of HSDIVIDER */ 66 ret = omap2_dflt_clk_enable(hw); 67 68 /* Parent is the x2 node, get parent of parent for the m2 div */ 69 parent_hw = clk_hw_get_parent(clk_hw_get_parent(hw)); 70 parent = to_clk_omap_divider(parent_hw); 71 72 /* Restore the dividers */ 73 if (!ret) { 74 orig_v = ti_clk_ll_ops->clk_readl(&parent->reg); 75 dummy_v = orig_v; 76 77 /* Write any other value different from the Read value */ 78 dummy_v ^= (1 << parent->shift); 79 ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg); 80 81 /* Write the original divider */ 82 ti_clk_ll_ops->clk_writel(orig_v, &parent->reg); 83 } 84 85 return ret; 86 } 87 88 static struct clk *_register_gate(struct device_node *node, const char *name, 89 const char *parent_name, unsigned long flags, 90 struct clk_omap_reg *reg, u8 bit_idx, 91 u8 clk_gate_flags, const struct clk_ops *ops, 92 const struct clk_hw_omap_ops *hw_ops) 93 { 94 struct clk_init_data init = { NULL }; 95 struct clk_hw_omap *clk_hw; 96 struct clk *clk; 97 98 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 99 if (!clk_hw) 100 return ERR_PTR(-ENOMEM); 101 102 clk_hw->hw.init = &init; 103 104 init.name = name; 105 init.ops = ops; 106 107 memcpy(&clk_hw->enable_reg, reg, sizeof(*reg)); 108 clk_hw->enable_bit = bit_idx; 109 clk_hw->ops = hw_ops; 110 111 clk_hw->flags = clk_gate_flags; 112 113 init.parent_names = &parent_name; 114 init.num_parents = 1; 115 116 init.flags = flags; 117 118 clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); 119 120 if (IS_ERR(clk)) 121 kfree(clk_hw); 122 123 return clk; 124 } 125 126 static void __init _of_ti_gate_clk_setup(struct device_node *node, 127 const struct clk_ops *ops, 128 const struct clk_hw_omap_ops *hw_ops) 129 { 130 struct clk *clk; 131 const char *parent_name; 132 struct clk_omap_reg reg; 133 const char *name; 134 u8 enable_bit = 0; 135 u32 flags = 0; 136 u8 clk_gate_flags = 0; 137 138 if (ops != &omap_gate_clkdm_clk_ops) { 139 if (ti_clk_get_reg_addr(node, 0, ®)) 140 return; 141 142 enable_bit = reg.bit; 143 } 144 145 if (of_clk_get_parent_count(node) != 1) { 146 pr_err("%pOFn must have 1 parent\n", node); 147 return; 148 } 149 150 parent_name = of_clk_get_parent_name(node, 0); 151 152 if (of_property_read_bool(node, "ti,set-rate-parent")) 153 flags |= CLK_SET_RATE_PARENT; 154 155 if (of_property_read_bool(node, "ti,set-bit-to-disable")) 156 clk_gate_flags |= INVERT_ENABLE; 157 158 name = ti_dt_clk_name(node); 159 clk = _register_gate(node, name, parent_name, flags, ®, 160 enable_bit, clk_gate_flags, ops, hw_ops); 161 162 if (!IS_ERR(clk)) 163 of_clk_add_provider(node, of_clk_src_simple_get, clk); 164 } 165 166 static void __init 167 _of_ti_composite_gate_clk_setup(struct device_node *node, 168 const struct clk_hw_omap_ops *hw_ops) 169 { 170 struct clk_hw_omap *gate; 171 172 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 173 if (!gate) 174 return; 175 176 if (ti_clk_get_reg_addr(node, 0, &gate->enable_reg)) 177 goto cleanup; 178 179 gate->enable_bit = gate->enable_reg.bit; 180 gate->ops = hw_ops; 181 182 if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE)) 183 return; 184 185 cleanup: 186 kfree(gate); 187 } 188 189 static void __init 190 of_ti_composite_no_wait_gate_clk_setup(struct device_node *node) 191 { 192 _of_ti_composite_gate_clk_setup(node, NULL); 193 } 194 CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock", 195 of_ti_composite_no_wait_gate_clk_setup); 196 197 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 198 static void __init of_ti_composite_interface_clk_setup(struct device_node *node) 199 { 200 _of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait); 201 } 202 CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock", 203 of_ti_composite_interface_clk_setup); 204 #endif 205 206 static void __init of_ti_composite_gate_clk_setup(struct device_node *node) 207 { 208 _of_ti_composite_gate_clk_setup(node, &clkhwops_wait); 209 } 210 CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock", 211 of_ti_composite_gate_clk_setup); 212 213 214 static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node) 215 { 216 _of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL); 217 } 218 CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock", 219 of_ti_clkdm_gate_clk_setup); 220 221 static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node) 222 { 223 _of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops, 224 &clkhwops_wait); 225 } 226 CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock", 227 of_ti_hsdiv_gate_clk_setup); 228 229 static void __init of_ti_gate_clk_setup(struct device_node *node) 230 { 231 _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL); 232 } 233 CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup); 234 235 static void __init of_ti_wait_gate_clk_setup(struct device_node *node) 236 { 237 _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait); 238 } 239 CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock", 240 of_ti_wait_gate_clk_setup); 241 242 #ifdef CONFIG_ARCH_OMAP3 243 static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node) 244 { 245 _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, 246 &clkhwops_am35xx_ipss_module_wait); 247 } 248 CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock", 249 of_ti_am35xx_gate_clk_setup); 250 251 static void __init of_ti_dss_gate_clk_setup(struct device_node *node) 252 { 253 _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, 254 &clkhwops_omap3430es2_dss_usbhost_wait); 255 } 256 CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock", 257 of_ti_dss_gate_clk_setup); 258 #endif 259