1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/clk.h> 4 #include <linux/clk-provider.h> 5 #include <linux/delay.h> 6 #include <linux/err.h> 7 #include <linux/io.h> 8 #include <linux/math64.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/clk/ti.h> 12 13 #include "clock.h" 14 15 /* FAPLL Control Register PLL_CTRL */ 16 #define FAPLL_MAIN_MULT_N_SHIFT 16 17 #define FAPLL_MAIN_DIV_P_SHIFT 8 18 #define FAPLL_MAIN_LOCK BIT(7) 19 #define FAPLL_MAIN_PLLEN BIT(3) 20 #define FAPLL_MAIN_BP BIT(2) 21 #define FAPLL_MAIN_LOC_CTL BIT(0) 22 23 #define FAPLL_MAIN_MAX_MULT_N 0xffff 24 #define FAPLL_MAIN_MAX_DIV_P 0xff 25 #define FAPLL_MAIN_CLEAR_MASK \ 26 ((FAPLL_MAIN_MAX_MULT_N << FAPLL_MAIN_MULT_N_SHIFT) | \ 27 (FAPLL_MAIN_DIV_P_SHIFT << FAPLL_MAIN_DIV_P_SHIFT) | \ 28 FAPLL_MAIN_LOC_CTL) 29 30 /* FAPLL powerdown register PWD */ 31 #define FAPLL_PWD_OFFSET 4 32 33 #define MAX_FAPLL_OUTPUTS 7 34 #define FAPLL_MAX_RETRIES 1000 35 36 #define to_fapll(_hw) container_of(_hw, struct fapll_data, hw) 37 #define to_synth(_hw) container_of(_hw, struct fapll_synth, hw) 38 39 /* The bypass bit is inverted on the ddr_pll.. */ 40 #define fapll_is_ddr_pll(va) (((u32)(va) & 0xffff) == 0x0440) 41 42 /* 43 * The audio_pll_clk1 input is hard wired to the 27MHz bypass clock, 44 * and the audio_pll_clk1 synthesizer is hardwared to 32KiHz output. 45 */ 46 #define is_ddr_pll_clk1(va) (((u32)(va) & 0xffff) == 0x044c) 47 #define is_audio_pll_clk1(va) (((u32)(va) & 0xffff) == 0x04a8) 48 49 /* Synthesizer divider register */ 50 #define SYNTH_LDMDIV1 BIT(8) 51 52 /* Synthesizer frequency register */ 53 #define SYNTH_LDFREQ BIT(31) 54 55 #define SYNTH_PHASE_K 8 56 #define SYNTH_MAX_INT_DIV 0xf 57 #define SYNTH_MAX_DIV_M 0xff 58 59 struct fapll_data { 60 struct clk_hw hw; 61 void __iomem *base; 62 const char *name; 63 struct clk *clk_ref; 64 struct clk *clk_bypass; 65 struct clk_onecell_data outputs; 66 bool bypass_bit_inverted; 67 }; 68 69 struct fapll_synth { 70 struct clk_hw hw; 71 struct fapll_data *fd; 72 int index; 73 void __iomem *freq; 74 void __iomem *div; 75 const char *name; 76 struct clk *clk_pll; 77 }; 78 79 static bool ti_fapll_clock_is_bypass(struct fapll_data *fd) 80 { 81 u32 v = readl_relaxed(fd->base); 82 83 if (fd->bypass_bit_inverted) 84 return !(v & FAPLL_MAIN_BP); 85 else 86 return !!(v & FAPLL_MAIN_BP); 87 } 88 89 static void ti_fapll_set_bypass(struct fapll_data *fd) 90 { 91 u32 v = readl_relaxed(fd->base); 92 93 if (fd->bypass_bit_inverted) 94 v &= ~FAPLL_MAIN_BP; 95 else 96 v |= FAPLL_MAIN_BP; 97 writel_relaxed(v, fd->base); 98 } 99 100 static void ti_fapll_clear_bypass(struct fapll_data *fd) 101 { 102 u32 v = readl_relaxed(fd->base); 103 104 if (fd->bypass_bit_inverted) 105 v |= FAPLL_MAIN_BP; 106 else 107 v &= ~FAPLL_MAIN_BP; 108 writel_relaxed(v, fd->base); 109 } 110 111 static int ti_fapll_wait_lock(struct fapll_data *fd) 112 { 113 int retries = FAPLL_MAX_RETRIES; 114 u32 v; 115 116 while ((v = readl_relaxed(fd->base))) { 117 if (v & FAPLL_MAIN_LOCK) 118 return 0; 119 120 if (retries-- <= 0) 121 break; 122 123 udelay(1); 124 } 125 126 pr_err("%s failed to lock\n", fd->name); 127 128 return -ETIMEDOUT; 129 } 130 131 static int ti_fapll_enable(struct clk_hw *hw) 132 { 133 struct fapll_data *fd = to_fapll(hw); 134 u32 v = readl_relaxed(fd->base); 135 136 v |= FAPLL_MAIN_PLLEN; 137 writel_relaxed(v, fd->base); 138 ti_fapll_wait_lock(fd); 139 140 return 0; 141 } 142 143 static void ti_fapll_disable(struct clk_hw *hw) 144 { 145 struct fapll_data *fd = to_fapll(hw); 146 u32 v = readl_relaxed(fd->base); 147 148 v &= ~FAPLL_MAIN_PLLEN; 149 writel_relaxed(v, fd->base); 150 } 151 152 static int ti_fapll_is_enabled(struct clk_hw *hw) 153 { 154 struct fapll_data *fd = to_fapll(hw); 155 u32 v = readl_relaxed(fd->base); 156 157 return v & FAPLL_MAIN_PLLEN; 158 } 159 160 static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw, 161 unsigned long parent_rate) 162 { 163 struct fapll_data *fd = to_fapll(hw); 164 u32 fapll_n, fapll_p, v; 165 u64 rate; 166 167 if (ti_fapll_clock_is_bypass(fd)) 168 return parent_rate; 169 170 rate = parent_rate; 171 172 /* PLL pre-divider is P and multiplier is N */ 173 v = readl_relaxed(fd->base); 174 fapll_p = (v >> 8) & 0xff; 175 if (fapll_p) 176 do_div(rate, fapll_p); 177 fapll_n = v >> 16; 178 if (fapll_n) 179 rate *= fapll_n; 180 181 return rate; 182 } 183 184 static u8 ti_fapll_get_parent(struct clk_hw *hw) 185 { 186 struct fapll_data *fd = to_fapll(hw); 187 188 if (ti_fapll_clock_is_bypass(fd)) 189 return 1; 190 191 return 0; 192 } 193 194 static int ti_fapll_set_div_mult(unsigned long rate, 195 unsigned long parent_rate, 196 u32 *pre_div_p, u32 *mult_n) 197 { 198 /* 199 * So far no luck getting decent clock with PLL divider, 200 * PLL does not seem to lock and the signal does not look 201 * right. It seems the divider can only be used together 202 * with the multiplier? 203 */ 204 if (rate < parent_rate) { 205 pr_warn("FAPLL main divider rates unsupported\n"); 206 return -EINVAL; 207 } 208 209 *mult_n = rate / parent_rate; 210 if (*mult_n > FAPLL_MAIN_MAX_MULT_N) 211 return -EINVAL; 212 *pre_div_p = 1; 213 214 return 0; 215 } 216 217 static int ti_fapll_determine_rate(struct clk_hw *hw, 218 struct clk_rate_request *req) 219 { 220 u32 pre_div_p, mult_n; 221 int error; 222 223 if (!req->rate) 224 return -EINVAL; 225 226 error = ti_fapll_set_div_mult(req->rate, req->best_parent_rate, 227 &pre_div_p, &mult_n); 228 if (error) { 229 req->rate = error; 230 231 return 0; 232 } 233 234 req->rate = req->best_parent_rate / pre_div_p; 235 req->rate *= mult_n; 236 237 return 0; 238 } 239 240 static int ti_fapll_set_rate(struct clk_hw *hw, unsigned long rate, 241 unsigned long parent_rate) 242 { 243 struct fapll_data *fd = to_fapll(hw); 244 u32 pre_div_p, mult_n, v; 245 int error; 246 247 if (!rate) 248 return -EINVAL; 249 250 error = ti_fapll_set_div_mult(rate, parent_rate, 251 &pre_div_p, &mult_n); 252 if (error) 253 return error; 254 255 ti_fapll_set_bypass(fd); 256 v = readl_relaxed(fd->base); 257 v &= ~FAPLL_MAIN_CLEAR_MASK; 258 v |= pre_div_p << FAPLL_MAIN_DIV_P_SHIFT; 259 v |= mult_n << FAPLL_MAIN_MULT_N_SHIFT; 260 writel_relaxed(v, fd->base); 261 if (ti_fapll_is_enabled(hw)) 262 ti_fapll_wait_lock(fd); 263 ti_fapll_clear_bypass(fd); 264 265 return 0; 266 } 267 268 static const struct clk_ops ti_fapll_ops = { 269 .enable = ti_fapll_enable, 270 .disable = ti_fapll_disable, 271 .is_enabled = ti_fapll_is_enabled, 272 .recalc_rate = ti_fapll_recalc_rate, 273 .get_parent = ti_fapll_get_parent, 274 .determine_rate = ti_fapll_determine_rate, 275 .set_rate = ti_fapll_set_rate, 276 }; 277 278 static int ti_fapll_synth_enable(struct clk_hw *hw) 279 { 280 struct fapll_synth *synth = to_synth(hw); 281 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); 282 283 v &= ~(1 << synth->index); 284 writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET); 285 286 return 0; 287 } 288 289 static void ti_fapll_synth_disable(struct clk_hw *hw) 290 { 291 struct fapll_synth *synth = to_synth(hw); 292 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); 293 294 v |= 1 << synth->index; 295 writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET); 296 } 297 298 static int ti_fapll_synth_is_enabled(struct clk_hw *hw) 299 { 300 struct fapll_synth *synth = to_synth(hw); 301 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); 302 303 return !(v & (1 << synth->index)); 304 } 305 306 /* 307 * See dm816x TRM chapter 1.10.3 Flying Adder PLL fore more info 308 */ 309 static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw, 310 unsigned long parent_rate) 311 { 312 struct fapll_synth *synth = to_synth(hw); 313 u32 synth_div_m; 314 u64 rate; 315 316 /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */ 317 if (!synth->div) 318 return 32768; 319 320 /* 321 * PLL in bypass sets the synths in bypass mode too. The PLL rate 322 * can be also be set to 27MHz, so we can't use parent_rate to 323 * check for bypass mode. 324 */ 325 if (ti_fapll_clock_is_bypass(synth->fd)) 326 return parent_rate; 327 328 rate = parent_rate; 329 330 /* 331 * Synth frequency integer and fractional divider. 332 * Note that the phase output K is 8, so the result needs 333 * to be multiplied by SYNTH_PHASE_K. 334 */ 335 if (synth->freq) { 336 u32 v, synth_int_div, synth_frac_div, synth_div_freq; 337 338 v = readl_relaxed(synth->freq); 339 synth_int_div = (v >> 24) & 0xf; 340 synth_frac_div = v & 0xffffff; 341 synth_div_freq = (synth_int_div * 10000000) + synth_frac_div; 342 rate *= 10000000; 343 do_div(rate, synth_div_freq); 344 rate *= SYNTH_PHASE_K; 345 } 346 347 /* Synth post-divider M */ 348 synth_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M; 349 350 return DIV_ROUND_UP_ULL(rate, synth_div_m); 351 } 352 353 static unsigned long ti_fapll_synth_get_frac_rate(struct clk_hw *hw, 354 unsigned long parent_rate) 355 { 356 struct fapll_synth *synth = to_synth(hw); 357 unsigned long current_rate, frac_rate; 358 u32 post_div_m; 359 360 current_rate = ti_fapll_synth_recalc_rate(hw, parent_rate); 361 post_div_m = readl_relaxed(synth->div) & SYNTH_MAX_DIV_M; 362 frac_rate = current_rate * post_div_m; 363 364 return frac_rate; 365 } 366 367 static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth, 368 unsigned long rate, 369 unsigned long parent_rate) 370 { 371 u32 post_div_m, synth_int_div = 0, synth_frac_div = 0, v; 372 373 post_div_m = DIV_ROUND_UP_ULL((u64)parent_rate * SYNTH_PHASE_K, rate); 374 post_div_m = post_div_m / SYNTH_MAX_INT_DIV; 375 if (post_div_m > SYNTH_MAX_DIV_M) 376 return -EINVAL; 377 if (!post_div_m) 378 post_div_m = 1; 379 380 for (; post_div_m < SYNTH_MAX_DIV_M; post_div_m++) { 381 synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate * 382 SYNTH_PHASE_K * 383 10000000, 384 rate * post_div_m); 385 synth_frac_div = synth_int_div % 10000000; 386 synth_int_div /= 10000000; 387 388 if (synth_int_div <= SYNTH_MAX_INT_DIV) 389 break; 390 } 391 392 if (synth_int_div > SYNTH_MAX_INT_DIV) 393 return -EINVAL; 394 395 v = readl_relaxed(synth->freq); 396 v &= ~0x1fffffff; 397 v |= (synth_int_div & SYNTH_MAX_INT_DIV) << 24; 398 v |= (synth_frac_div & 0xffffff); 399 v |= SYNTH_LDFREQ; 400 writel_relaxed(v, synth->freq); 401 402 return post_div_m; 403 } 404 405 static int ti_fapll_synth_determine_rate(struct clk_hw *hw, 406 struct clk_rate_request *req) 407 { 408 struct fapll_synth *synth = to_synth(hw); 409 struct fapll_data *fd = synth->fd; 410 unsigned long r; 411 412 if (ti_fapll_clock_is_bypass(fd) || !synth->div || !req->rate) 413 return -EINVAL; 414 415 /* Only post divider m available with no fractional divider? */ 416 if (!synth->freq) { 417 unsigned long frac_rate; 418 u32 synth_post_div_m; 419 420 frac_rate = ti_fapll_synth_get_frac_rate(hw, 421 req->best_parent_rate); 422 synth_post_div_m = DIV_ROUND_UP(frac_rate, req->rate); 423 r = DIV_ROUND_UP(frac_rate, synth_post_div_m); 424 goto out; 425 } 426 427 r = req->best_parent_rate * SYNTH_PHASE_K; 428 if (req->rate > r) 429 goto out; 430 431 r = DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M); 432 if (req->rate < r) 433 goto out; 434 435 r = req->rate; 436 out: 437 req->rate = r; 438 439 return 0; 440 } 441 442 static int ti_fapll_synth_set_rate(struct clk_hw *hw, unsigned long rate, 443 unsigned long parent_rate) 444 { 445 struct fapll_synth *synth = to_synth(hw); 446 struct fapll_data *fd = synth->fd; 447 unsigned long frac_rate, post_rate = 0; 448 u32 post_div_m = 0, v; 449 450 if (ti_fapll_clock_is_bypass(fd) || !synth->div || !rate) 451 return -EINVAL; 452 453 /* Produce the rate with just post divider M? */ 454 frac_rate = ti_fapll_synth_get_frac_rate(hw, parent_rate); 455 if (frac_rate < rate) { 456 if (!synth->freq) 457 return -EINVAL; 458 } else { 459 post_div_m = DIV_ROUND_UP(frac_rate, rate); 460 if (post_div_m && (post_div_m <= SYNTH_MAX_DIV_M)) 461 post_rate = DIV_ROUND_UP(frac_rate, post_div_m); 462 if (!synth->freq && !post_rate) 463 return -EINVAL; 464 } 465 466 /* Need to recalculate the fractional divider? */ 467 if ((post_rate != rate) && synth->freq) 468 post_div_m = ti_fapll_synth_set_frac_rate(synth, 469 rate, 470 parent_rate); 471 472 v = readl_relaxed(synth->div); 473 v &= ~SYNTH_MAX_DIV_M; 474 v |= post_div_m; 475 v |= SYNTH_LDMDIV1; 476 writel_relaxed(v, synth->div); 477 478 return 0; 479 } 480 481 static const struct clk_ops ti_fapll_synt_ops = { 482 .enable = ti_fapll_synth_enable, 483 .disable = ti_fapll_synth_disable, 484 .is_enabled = ti_fapll_synth_is_enabled, 485 .recalc_rate = ti_fapll_synth_recalc_rate, 486 .determine_rate = ti_fapll_synth_determine_rate, 487 .set_rate = ti_fapll_synth_set_rate, 488 }; 489 490 static struct clk * __init ti_fapll_synth_setup(struct fapll_data *fd, 491 void __iomem *freq, 492 void __iomem *div, 493 int index, 494 const char *name, 495 const char *parent, 496 struct clk *pll_clk) 497 { 498 struct clk_init_data *init; 499 struct fapll_synth *synth; 500 struct clk *clk = ERR_PTR(-ENOMEM); 501 502 init = kzalloc(sizeof(*init), GFP_KERNEL); 503 if (!init) 504 return ERR_PTR(-ENOMEM); 505 506 init->ops = &ti_fapll_synt_ops; 507 init->name = name; 508 init->parent_names = &parent; 509 init->num_parents = 1; 510 511 synth = kzalloc(sizeof(*synth), GFP_KERNEL); 512 if (!synth) 513 goto free; 514 515 synth->fd = fd; 516 synth->index = index; 517 synth->freq = freq; 518 synth->div = div; 519 synth->name = name; 520 synth->hw.init = init; 521 synth->clk_pll = pll_clk; 522 523 clk = clk_register(NULL, &synth->hw); 524 if (IS_ERR(clk)) { 525 pr_err("failed to register clock\n"); 526 goto free; 527 } 528 529 return clk; 530 531 free: 532 kfree(synth); 533 kfree(init); 534 535 return clk; 536 } 537 538 static void __init ti_fapll_setup(struct device_node *node) 539 { 540 struct fapll_data *fd; 541 struct clk_init_data *init = NULL; 542 const char *parent_name[2]; 543 struct clk *pll_clk; 544 const char *name; 545 int i; 546 547 fd = kzalloc(sizeof(*fd), GFP_KERNEL); 548 if (!fd) 549 return; 550 551 fd->outputs.clks = kzalloc(sizeof(struct clk *) * 552 MAX_FAPLL_OUTPUTS + 1, 553 GFP_KERNEL); 554 if (!fd->outputs.clks) 555 goto free; 556 557 init = kzalloc(sizeof(*init), GFP_KERNEL); 558 if (!init) 559 goto free; 560 561 init->ops = &ti_fapll_ops; 562 name = ti_dt_clk_name(node); 563 init->name = name; 564 565 init->num_parents = of_clk_get_parent_count(node); 566 if (init->num_parents != 2) { 567 pr_err("%pOFn must have two parents\n", node); 568 goto free; 569 } 570 571 of_clk_parent_fill(node, parent_name, 2); 572 init->parent_names = parent_name; 573 574 fd->clk_ref = of_clk_get(node, 0); 575 if (IS_ERR(fd->clk_ref)) { 576 pr_err("%pOFn could not get clk_ref\n", node); 577 goto free; 578 } 579 580 fd->clk_bypass = of_clk_get(node, 1); 581 if (IS_ERR(fd->clk_bypass)) { 582 pr_err("%pOFn could not get clk_bypass\n", node); 583 goto free; 584 } 585 586 fd->base = of_iomap(node, 0); 587 if (!fd->base) { 588 pr_err("%pOFn could not get IO base\n", node); 589 goto free; 590 } 591 592 if (fapll_is_ddr_pll(fd->base)) 593 fd->bypass_bit_inverted = true; 594 595 fd->name = name; 596 fd->hw.init = init; 597 598 /* Register the parent PLL */ 599 pll_clk = clk_register(NULL, &fd->hw); 600 if (IS_ERR(pll_clk)) 601 goto unmap; 602 603 fd->outputs.clks[0] = pll_clk; 604 fd->outputs.clk_num++; 605 606 /* 607 * Set up the child synthesizers starting at index 1 as the 608 * PLL output is at index 0. We need to check the clock-indices 609 * for numbering in case there are holes in the synth mapping, 610 * and then probe the synth register to see if it has a FREQ 611 * register available. 612 */ 613 for (i = 0; i < MAX_FAPLL_OUTPUTS; i++) { 614 const char *output_name; 615 void __iomem *freq, *div; 616 struct clk *synth_clk; 617 int output_instance; 618 u32 v; 619 620 if (of_property_read_string_index(node, "clock-output-names", 621 i, &output_name)) 622 continue; 623 624 if (of_property_read_u32_index(node, "clock-indices", i, 625 &output_instance)) 626 output_instance = i; 627 628 freq = fd->base + (output_instance * 8); 629 div = freq + 4; 630 631 /* Check for hardwired audio_pll_clk1 */ 632 if (is_audio_pll_clk1(freq)) { 633 freq = NULL; 634 div = NULL; 635 } else { 636 /* Does the synthesizer have a FREQ register? */ 637 v = readl_relaxed(freq); 638 if (!v) 639 freq = NULL; 640 } 641 synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance, 642 output_name, name, pll_clk); 643 if (IS_ERR(synth_clk)) 644 continue; 645 646 fd->outputs.clks[output_instance] = synth_clk; 647 fd->outputs.clk_num++; 648 649 clk_register_clkdev(synth_clk, output_name, NULL); 650 } 651 652 /* Register the child synthesizers as the FAPLL outputs */ 653 of_clk_add_provider(node, of_clk_src_onecell_get, &fd->outputs); 654 /* Add clock alias for the outputs */ 655 656 kfree(init); 657 658 return; 659 660 unmap: 661 iounmap(fd->base); 662 free: 663 if (fd->clk_bypass) 664 clk_put(fd->clk_bypass); 665 if (fd->clk_ref) 666 clk_put(fd->clk_ref); 667 kfree(fd->outputs.clks); 668 kfree(fd); 669 kfree(init); 670 } 671 672 CLK_OF_DECLARE(ti_fapll_clock, "ti,dm816-fapll-clock", ti_fapll_setup); 673