1 /* 2 * TI Clock driver internal definitions 3 * 4 * Copyright (C) 2014 Texas Instruments, Inc 5 * Tero Kristo (t-kristo@ti.com) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 #ifndef __DRIVERS_CLK_TI_CLOCK__ 17 #define __DRIVERS_CLK_TI_CLOCK__ 18 19 struct clk_omap_divider { 20 struct clk_hw hw; 21 struct clk_omap_reg reg; 22 u8 shift; 23 u8 width; 24 u8 flags; 25 const struct clk_div_table *table; 26 }; 27 28 #define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw) 29 30 struct clk_omap_mux { 31 struct clk_hw hw; 32 struct clk_omap_reg reg; 33 u32 *table; 34 u32 mask; 35 u8 shift; 36 u8 flags; 37 }; 38 39 #define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw) 40 41 enum { 42 TI_CLK_FIXED, 43 TI_CLK_MUX, 44 TI_CLK_DIVIDER, 45 TI_CLK_COMPOSITE, 46 TI_CLK_FIXED_FACTOR, 47 TI_CLK_GATE, 48 TI_CLK_DPLL, 49 }; 50 51 /* Global flags */ 52 #define CLKF_INDEX_POWER_OF_TWO (1 << 0) 53 #define CLKF_INDEX_STARTS_AT_ONE (1 << 1) 54 #define CLKF_SET_RATE_PARENT (1 << 2) 55 #define CLKF_OMAP3 (1 << 3) 56 #define CLKF_AM35XX (1 << 4) 57 58 /* Gate flags */ 59 #define CLKF_SET_BIT_TO_DISABLE (1 << 5) 60 #define CLKF_INTERFACE (1 << 6) 61 #define CLKF_SSI (1 << 7) 62 #define CLKF_DSS (1 << 8) 63 #define CLKF_HSOTGUSB (1 << 9) 64 #define CLKF_WAIT (1 << 10) 65 #define CLKF_NO_WAIT (1 << 11) 66 #define CLKF_HSDIV (1 << 12) 67 #define CLKF_CLKDM (1 << 13) 68 69 /* DPLL flags */ 70 #define CLKF_LOW_POWER_STOP (1 << 5) 71 #define CLKF_LOCK (1 << 6) 72 #define CLKF_LOW_POWER_BYPASS (1 << 7) 73 #define CLKF_PER (1 << 8) 74 #define CLKF_CORE (1 << 9) 75 #define CLKF_J_TYPE (1 << 10) 76 77 #define CLK(dev, con, ck) \ 78 { \ 79 .lk = { \ 80 .dev_id = dev, \ 81 .con_id = con, \ 82 }, \ 83 .clk = ck, \ 84 } 85 86 struct ti_clk { 87 const char *name; 88 const char *clkdm_name; 89 int type; 90 void *data; 91 struct ti_clk *patch; 92 struct clk *clk; 93 }; 94 95 struct ti_clk_alias { 96 struct ti_clk *clk; 97 struct clk_lookup lk; 98 struct list_head link; 99 }; 100 101 struct ti_clk_fixed { 102 u32 frequency; 103 u16 flags; 104 }; 105 106 struct ti_clk_mux { 107 u8 bit_shift; 108 int num_parents; 109 u16 reg; 110 u8 module; 111 const char * const *parents; 112 u16 flags; 113 }; 114 115 struct ti_clk_divider { 116 const char *parent; 117 u8 bit_shift; 118 u16 max_div; 119 u16 reg; 120 u8 module; 121 int *dividers; 122 int num_dividers; 123 u16 flags; 124 }; 125 126 struct ti_clk_fixed_factor { 127 const char *parent; 128 u16 div; 129 u16 mult; 130 u16 flags; 131 }; 132 133 struct ti_clk_gate { 134 const char *parent; 135 u8 bit_shift; 136 u16 reg; 137 u8 module; 138 u16 flags; 139 }; 140 141 struct ti_clk_composite { 142 struct ti_clk_divider *divider; 143 struct ti_clk_mux *mux; 144 struct ti_clk_gate *gate; 145 u16 flags; 146 }; 147 148 struct ti_clk_clkdm_gate { 149 const char *parent; 150 u16 flags; 151 }; 152 153 struct ti_clk_dpll { 154 int num_parents; 155 u16 control_reg; 156 u16 idlest_reg; 157 u16 autoidle_reg; 158 u16 mult_div1_reg; 159 u8 module; 160 const char **parents; 161 u16 flags; 162 u8 modes; 163 u32 mult_mask; 164 u32 div1_mask; 165 u32 enable_mask; 166 u32 autoidle_mask; 167 u32 freqsel_mask; 168 u32 idlest_mask; 169 u32 dco_mask; 170 u32 sddiv_mask; 171 u16 max_multiplier; 172 u16 max_divider; 173 u8 min_divider; 174 u8 auto_recal_bit; 175 u8 recal_en_bit; 176 u8 recal_st_bit; 177 }; 178 179 /* Composite clock component types */ 180 enum { 181 CLK_COMPONENT_TYPE_GATE = 0, 182 CLK_COMPONENT_TYPE_DIVIDER, 183 CLK_COMPONENT_TYPE_MUX, 184 CLK_COMPONENT_TYPE_MAX, 185 }; 186 187 /** 188 * struct ti_dt_clk - OMAP DT clock alias declarations 189 * @lk: clock lookup definition 190 * @node_name: clock DT node to map to 191 */ 192 struct ti_dt_clk { 193 struct clk_lookup lk; 194 char *node_name; 195 }; 196 197 #define DT_CLK(dev, con, name) \ 198 { \ 199 .lk = { \ 200 .dev_id = dev, \ 201 .con_id = con, \ 202 }, \ 203 .node_name = name, \ 204 } 205 206 typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *); 207 208 struct clk *ti_clk_register_gate(struct ti_clk *setup); 209 struct clk *ti_clk_register_interface(struct ti_clk *setup); 210 struct clk *ti_clk_register_mux(struct ti_clk *setup); 211 struct clk *ti_clk_register_divider(struct ti_clk *setup); 212 struct clk *ti_clk_register_composite(struct ti_clk *setup); 213 struct clk *ti_clk_register_dpll(struct ti_clk *setup); 214 struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, 215 const char *con); 216 int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con); 217 void ti_clk_add_aliases(void); 218 219 struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup); 220 struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup); 221 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup); 222 223 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, 224 u8 flags, u8 *width, 225 const struct clk_div_table **table); 226 227 void ti_clk_patch_legacy_clks(struct ti_clk **patch); 228 struct clk *ti_clk_register_clk(struct ti_clk *setup); 229 int ti_clk_register_legacy_clks(struct ti_clk_alias *clks); 230 231 int ti_clk_get_reg_addr(struct device_node *node, int index, 232 struct clk_omap_reg *reg); 233 void ti_dt_clocks_register(struct ti_dt_clk *oclks); 234 int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, 235 ti_of_clk_init_cb_t func); 236 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); 237 238 void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw); 239 int of_ti_clk_autoidle_setup(struct device_node *node); 240 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); 241 242 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; 243 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; 244 extern const struct clk_hw_omap_ops clkhwops_wait; 245 extern const struct clk_hw_omap_ops clkhwops_iclk; 246 extern const struct clk_hw_omap_ops clkhwops_iclk_wait; 247 extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; 248 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; 249 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; 250 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; 251 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; 252 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; 253 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; 254 255 extern const struct clk_ops ti_clk_divider_ops; 256 extern const struct clk_ops ti_clk_mux_ops; 257 extern const struct clk_ops omap_gate_clk_ops; 258 259 void omap2_init_clk_clkdm(struct clk_hw *hw); 260 int omap2_clkops_enable_clkdm(struct clk_hw *hw); 261 void omap2_clkops_disable_clkdm(struct clk_hw *hw); 262 263 int omap2_dflt_clk_enable(struct clk_hw *hw); 264 void omap2_dflt_clk_disable(struct clk_hw *hw); 265 int omap2_dflt_clk_is_enabled(struct clk_hw *hw); 266 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 267 struct clk_omap_reg *other_reg, 268 u8 *other_bit); 269 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 270 struct clk_omap_reg *idlest_reg, 271 u8 *idlest_bit, u8 *idlest_val); 272 273 void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); 274 void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); 275 276 u8 omap2_init_dpll_parent(struct clk_hw *hw); 277 int omap3_noncore_dpll_enable(struct clk_hw *hw); 278 void omap3_noncore_dpll_disable(struct clk_hw *hw); 279 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index); 280 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, 281 unsigned long parent_rate); 282 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, 283 unsigned long rate, 284 unsigned long parent_rate, 285 u8 index); 286 int omap3_noncore_dpll_determine_rate(struct clk_hw *hw, 287 struct clk_rate_request *req); 288 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, 289 unsigned long *parent_rate); 290 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, 291 unsigned long parent_rate); 292 293 /* 294 * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks 295 * that are sourced by DPLL5, and both of these require this clock 296 * to be at 120 MHz for proper operation. 297 */ 298 #define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000 299 300 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); 301 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, 302 unsigned long parent_rate); 303 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, 304 unsigned long parent_rate, u8 index); 305 int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate, 306 unsigned long parent_rate); 307 void omap3_clk_lock_dpll5(void); 308 309 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 310 unsigned long parent_rate); 311 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, 312 unsigned long target_rate, 313 unsigned long *parent_rate); 314 int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, 315 struct clk_rate_request *req); 316 317 extern struct ti_clk_ll_ops *ti_clk_ll_ops; 318 319 #endif 320