1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Default clock type 4 * 5 * Copyright (C) 2005-2008, 2015 Texas Instruments, Inc. 6 * Copyright (C) 2004-2010 Nokia Corporation 7 * 8 * Contacts: 9 * Richard Woodruff <r-woodruff2@ti.com> 10 * Paul Walmsley 11 * Tero Kristo <t-kristo@ti.com> 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/errno.h> 16 #include <linux/clk-provider.h> 17 #include <linux/io.h> 18 #include <linux/clk/ti.h> 19 #include <linux/delay.h> 20 21 #include "clock.h" 22 23 /* 24 * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait 25 * for a module to indicate that it is no longer in idle 26 */ 27 #define MAX_MODULE_ENABLE_WAIT 100000 28 29 /* 30 * CM module register offsets, used for calculating the companion 31 * register addresses. 32 */ 33 #define CM_FCLKEN 0x0000 34 #define CM_ICLKEN 0x0010 35 36 /** 37 * _wait_idlest_generic - wait for a module to leave the idle state 38 * @clk: module clock to wait for (needed for register offsets) 39 * @reg: virtual address of module IDLEST register 40 * @mask: value to mask against to determine if the module is active 41 * @idlest: idle state indicator (0 or 1) for the clock 42 * @name: name of the clock (for printk) 43 * 44 * Wait for a module to leave idle, where its idle-status register is 45 * not inside the CM module. Returns 1 if the module left idle 46 * promptly, or 0 if the module did not leave idle before the timeout 47 * elapsed. XXX Deprecated - should be moved into drivers for the 48 * individual IP block that the IDLEST register exists in. 49 */ 50 static int _wait_idlest_generic(struct clk_hw_omap *clk, 51 struct clk_omap_reg *reg, 52 u32 mask, u8 idlest, const char *name) 53 { 54 int i = 0, ena = 0; 55 56 ena = (idlest) ? 0 : mask; 57 58 /* Wait until module enters enabled state */ 59 for (i = 0; i < MAX_MODULE_ENABLE_WAIT; i++) { 60 if ((ti_clk_ll_ops->clk_readl(reg) & mask) == ena) 61 break; 62 udelay(1); 63 } 64 65 if (i < MAX_MODULE_ENABLE_WAIT) 66 pr_debug("omap clock: module associated with clock %s ready after %d loops\n", 67 name, i); 68 else 69 pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n", 70 name, MAX_MODULE_ENABLE_WAIT); 71 72 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; 73 } 74 75 /** 76 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE 77 * @clk: struct clk * belonging to the module 78 * 79 * If the necessary clocks for the OMAP hardware IP block that 80 * corresponds to clock @clk are enabled, then wait for the module to 81 * indicate readiness (i.e., to leave IDLE). This code does not 82 * belong in the clock code and will be moved in the medium term to 83 * module-dependent code. No return value. 84 */ 85 static void _omap2_module_wait_ready(struct clk_hw_omap *clk) 86 { 87 struct clk_omap_reg companion_reg, idlest_reg; 88 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; 89 s16 prcm_mod; 90 int r; 91 92 /* Not all modules have multiple clocks that their IDLEST depends on */ 93 if (clk->ops->find_companion) { 94 clk->ops->find_companion(clk, &companion_reg, &other_bit); 95 if (!(ti_clk_ll_ops->clk_readl(&companion_reg) & 96 (1 << other_bit))) 97 return; 98 } 99 100 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); 101 r = ti_clk_ll_ops->cm_split_idlest_reg(&idlest_reg, &prcm_mod, 102 &idlest_reg_id); 103 if (r) { 104 /* IDLEST register not in the CM module */ 105 _wait_idlest_generic(clk, &idlest_reg, (1 << idlest_bit), 106 idlest_val, clk_hw_get_name(&clk->hw)); 107 } else { 108 ti_clk_ll_ops->cm_wait_module_ready(0, prcm_mod, idlest_reg_id, 109 idlest_bit); 110 } 111 } 112 113 /** 114 * omap2_clk_dflt_find_companion - find companion clock to @clk 115 * @clk: struct clk * to find the companion clock of 116 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in 117 * @other_bit: u8 ** to return the companion clock bit shift in 118 * 119 * Note: We don't need special code here for INVERT_ENABLE for the 120 * time being since INVERT_ENABLE only applies to clocks enabled by 121 * CM_CLKEN_PLL 122 * 123 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's 124 * just a matter of XORing the bits. 125 * 126 * Some clocks don't have companion clocks. For example, modules with 127 * only an interface clock (such as MAILBOXES) don't have a companion 128 * clock. Right now, this code relies on the hardware exporting a bit 129 * in the correct companion register that indicates that the 130 * nonexistent 'companion clock' is active. Future patches will 131 * associate this type of code with per-module data structures to 132 * avoid this issue, and remove the casts. No return value. 133 */ 134 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 135 struct clk_omap_reg *other_reg, 136 u8 *other_bit) 137 { 138 memcpy(other_reg, &clk->enable_reg, sizeof(*other_reg)); 139 140 /* 141 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes 142 * it's just a matter of XORing the bits. 143 */ 144 other_reg->offset ^= (CM_FCLKEN ^ CM_ICLKEN); 145 146 *other_bit = clk->enable_bit; 147 } 148 149 /** 150 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk 151 * @clk: struct clk * to find IDLEST info for 152 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in 153 * @idlest_bit: u8 * to return the CM_IDLEST bit shift in 154 * @idlest_val: u8 * to return the idle status indicator 155 * 156 * Return the CM_IDLEST register address and bit shift corresponding 157 * to the module that "owns" this clock. This default code assumes 158 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that 159 * the IDLEST register address ID corresponds to the CM_*CLKEN 160 * register address ID (e.g., that CM_FCLKEN2 corresponds to 161 * CM_IDLEST2). This is not true for all modules. No return value. 162 */ 163 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 164 struct clk_omap_reg *idlest_reg, u8 *idlest_bit, 165 u8 *idlest_val) 166 { 167 memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg)); 168 169 idlest_reg->offset &= ~0xf0; 170 idlest_reg->offset |= 0x20; 171 172 *idlest_bit = clk->enable_bit; 173 174 /* 175 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 176 * 34xx reverses this, just to keep us on our toes 177 * AM35xx uses both, depending on the module. 178 */ 179 *idlest_val = ti_clk_get_features()->cm_idlest_val; 180 } 181 182 /** 183 * omap2_dflt_clk_enable - enable a clock in the hardware 184 * @hw: struct clk_hw * of the clock to enable 185 * 186 * Enable the clock @hw in the hardware. We first call into the OMAP 187 * clockdomain code to "enable" the corresponding clockdomain if this 188 * is the first enabled user of the clockdomain. Then program the 189 * hardware to enable the clock. Then wait for the IP block that uses 190 * this clock to leave idle (if applicable). Returns the error value 191 * from clkdm_clk_enable() if it terminated with an error, or -EINVAL 192 * if @hw has a null clock enable_reg, or zero upon success. 193 */ 194 int omap2_dflt_clk_enable(struct clk_hw *hw) 195 { 196 struct clk_hw_omap *clk; 197 u32 v; 198 int ret = 0; 199 bool clkdm_control; 200 201 if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) 202 clkdm_control = false; 203 else 204 clkdm_control = true; 205 206 clk = to_clk_hw_omap(hw); 207 208 if (clkdm_control && clk->clkdm) { 209 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); 210 if (ret) { 211 WARN(1, 212 "%s: could not enable %s's clockdomain %s: %d\n", 213 __func__, clk_hw_get_name(hw), 214 clk->clkdm_name, ret); 215 return ret; 216 } 217 } 218 219 /* FIXME should not have INVERT_ENABLE bit here */ 220 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); 221 if (clk->flags & INVERT_ENABLE) 222 v &= ~(1 << clk->enable_bit); 223 else 224 v |= (1 << clk->enable_bit); 225 ti_clk_ll_ops->clk_writel(v, &clk->enable_reg); 226 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); /* OCP barrier */ 227 228 if (clk->ops && clk->ops->find_idlest) 229 _omap2_module_wait_ready(clk); 230 231 return 0; 232 } 233 234 /** 235 * omap2_dflt_clk_disable - disable a clock in the hardware 236 * @hw: struct clk_hw * of the clock to disable 237 * 238 * Disable the clock @hw in the hardware, and call into the OMAP 239 * clockdomain code to "disable" the corresponding clockdomain if all 240 * clocks/hwmods in that clockdomain are now disabled. No return 241 * value. 242 */ 243 void omap2_dflt_clk_disable(struct clk_hw *hw) 244 { 245 struct clk_hw_omap *clk; 246 u32 v; 247 248 clk = to_clk_hw_omap(hw); 249 250 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); 251 if (clk->flags & INVERT_ENABLE) 252 v |= (1 << clk->enable_bit); 253 else 254 v &= ~(1 << clk->enable_bit); 255 ti_clk_ll_ops->clk_writel(v, &clk->enable_reg); 256 /* No OCP barrier needed here since it is a disable operation */ 257 258 if (!(ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) && 259 clk->clkdm) 260 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); 261 } 262 263 /** 264 * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? 265 * @hw: struct clk_hw * to check 266 * 267 * Return 1 if the clock represented by @hw is enabled in the 268 * hardware, or 0 otherwise. Intended for use in the struct 269 * clk_ops.is_enabled function pointer. 270 */ 271 int omap2_dflt_clk_is_enabled(struct clk_hw *hw) 272 { 273 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 274 u32 v; 275 276 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); 277 278 if (clk->flags & INVERT_ENABLE) 279 v ^= BIT(clk->enable_bit); 280 281 v &= BIT(clk->enable_bit); 282 283 return v ? 1 : 0; 284 } 285 286 const struct clk_hw_omap_ops clkhwops_wait = { 287 .find_idlest = omap2_clk_dflt_find_idlest, 288 .find_companion = omap2_clk_dflt_find_companion, 289 }; 290