1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * DRA7 Clock init 4 * 5 * Copyright (C) 2013 Texas Instruments, Inc. 6 * 7 * Tero Kristo (t-kristo@ti.com) 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/list.h> 12 #include <linux/clk.h> 13 #include <linux/clkdev.h> 14 #include <linux/clk/ti.h> 15 #include <dt-bindings/clock/dra7.h> 16 17 #include "clock.h" 18 19 #define DRA7_DPLL_GMAC_DEFFREQ 1000000000 20 #define DRA7_DPLL_USB_DEFFREQ 960000000 21 22 static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = { 23 { DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" }, 24 { 0 }, 25 }; 26 27 static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = { 28 { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" }, 29 { 0 }, 30 }; 31 32 static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = { 33 "dpll_abe_m2x2_ck", 34 "dpll_core_h22x2_ck", 35 NULL, 36 }; 37 38 static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = { 39 { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL }, 40 { 0 }, 41 }; 42 43 static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = { 44 { DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP | CLKF_NO_IDLEST, "ipu1-clkctrl:0000:24" }, 45 { 0 }, 46 }; 47 48 static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = { 49 "per_abe_x1_gfclk2_div", 50 "video1_clk2_div", 51 "video2_clk2_div", 52 "hdmi_clk2_div", 53 NULL, 54 }; 55 56 static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = { 57 "abe_24m_fclk", 58 "abe_sys_clk_div", 59 "func_24m_clk", 60 "atl_clkin3_ck", 61 "atl_clkin2_ck", 62 "atl_clkin1_ck", 63 "atl_clkin0_ck", 64 "sys_clkin2", 65 "ref_clkin0_ck", 66 "ref_clkin1_ck", 67 "ref_clkin2_ck", 68 "ref_clkin3_ck", 69 "mlb_clk", 70 "mlbp_clk", 71 NULL, 72 }; 73 74 static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = { 75 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 76 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 77 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 78 { 0 }, 79 }; 80 81 static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = { 82 "timer_sys_clk_div", 83 "sys_32k_ck", 84 "sys_clkin2", 85 "ref_clkin0_ck", 86 "ref_clkin1_ck", 87 "ref_clkin2_ck", 88 "ref_clkin3_ck", 89 "abe_giclk_div", 90 "video1_div_clk", 91 "video2_div_clk", 92 "hdmi_div_clk", 93 "clkoutmux0_clk_mux", 94 NULL, 95 }; 96 97 static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = { 98 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, 99 { 0 }, 100 }; 101 102 static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = { 103 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, 104 { 0 }, 105 }; 106 107 static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = { 108 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, 109 { 0 }, 110 }; 111 112 static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = { 113 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, 114 { 0 }, 115 }; 116 117 static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = { 118 "func_48m_fclk", 119 "dpll_per_m2x2_ck", 120 NULL, 121 }; 122 123 static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = { 124 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 125 { 0 }, 126 }; 127 128 static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = { 129 { DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" }, 130 { DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" }, 131 { DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" }, 132 { DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" }, 133 { DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" }, 134 { DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 135 { DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" }, 136 { 0 }, 137 }; 138 139 static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = { 140 { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" }, 141 { 0 }, 142 }; 143 144 static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = { 145 { DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 146 { 0 }, 147 }; 148 149 static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = { 150 { DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, 151 { DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, 152 { 0 }, 153 }; 154 155 static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = { 156 { DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 157 { DRA7_L3MAIN1_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 158 { DRA7_L3MAIN1_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" }, 159 { DRA7_L3MAIN1_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 160 { DRA7_L3MAIN1_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 161 { DRA7_L3MAIN1_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 162 { DRA7_L3MAIN1_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 163 { 0 }, 164 }; 165 166 static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = { 167 { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" }, 168 { 0 }, 169 }; 170 171 static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = { 172 { DRA7_DMA_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 173 { 0 }, 174 }; 175 176 static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = { 177 { DRA7_EMIF_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 178 { 0 }, 179 }; 180 181 static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = { 182 "sys_32k_ck", 183 "video1_clkin_ck", 184 "video2_clkin_ck", 185 "hdmi_clkin_ck", 186 NULL, 187 }; 188 189 static const char * const dra7_atl_gfclk_mux_parents[] __initconst = { 190 "l3_iclk_div", 191 "dpll_abe_m2_ck", 192 "atl-clkctrl:0000:24", 193 NULL, 194 }; 195 196 static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = { 197 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL }, 198 { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL }, 199 { 0 }, 200 }; 201 202 static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = { 203 { DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" }, 204 { 0 }, 205 }; 206 207 static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = { 208 { DRA7_L4CFG_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" }, 209 { DRA7_L4CFG_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" }, 210 { DRA7_L4CFG_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 211 { DRA7_L4CFG_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 212 { DRA7_L4CFG_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" }, 213 { DRA7_L4CFG_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" }, 214 { DRA7_L4CFG_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" }, 215 { DRA7_L4CFG_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" }, 216 { DRA7_L4CFG_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" }, 217 { DRA7_L4CFG_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" }, 218 { DRA7_L4CFG_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" }, 219 { DRA7_L4CFG_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" }, 220 { DRA7_L4CFG_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" }, 221 { DRA7_L4CFG_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" }, 222 { DRA7_L4CFG_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" }, 223 { 0 }, 224 }; 225 226 static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = { 227 { DRA7_L3INSTR_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 228 { DRA7_L3INSTR_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 229 { 0 }, 230 }; 231 232 static const char * const dra7_dss_dss_clk_parents[] __initconst = { 233 "dpll_per_h12x2_ck", 234 NULL, 235 }; 236 237 static const char * const dra7_dss_48mhz_clk_parents[] __initconst = { 238 "func_48m_fclk", 239 NULL, 240 }; 241 242 static const char * const dra7_dss_hdmi_clk_parents[] __initconst = { 243 "hdmi_dpll_clk_mux", 244 NULL, 245 }; 246 247 static const char * const dra7_dss_32khz_clk_parents[] __initconst = { 248 "sys_32k_ck", 249 NULL, 250 }; 251 252 static const char * const dra7_dss_video1_clk_parents[] __initconst = { 253 "video1_dpll_clk_mux", 254 NULL, 255 }; 256 257 static const char * const dra7_dss_video2_clk_parents[] __initconst = { 258 "video2_dpll_clk_mux", 259 NULL, 260 }; 261 262 static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = { 263 { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL }, 264 { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL }, 265 { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL }, 266 { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 267 { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL }, 268 { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL }, 269 { 0 }, 270 }; 271 272 static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = { 273 { DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" }, 274 { DRA7_DSS_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" }, 275 { 0 }, 276 }; 277 278 static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = { 279 "func_128m_clk", 280 "dpll_per_m2x2_ck", 281 NULL, 282 }; 283 284 static const char * const dra7_mmc1_fclk_div_parents[] __initconst = { 285 "l3init-clkctrl:0008:24", 286 NULL, 287 }; 288 289 static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = { 290 .max_div = 4, 291 .flags = CLK_DIVIDER_POWER_OF_TWO, 292 }; 293 294 static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = { 295 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 296 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL }, 297 { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data }, 298 { 0 }, 299 }; 300 301 static const char * const dra7_mmc2_fclk_div_parents[] __initconst = { 302 "l3init-clkctrl:0010:24", 303 NULL, 304 }; 305 306 static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = { 307 .max_div = 4, 308 .flags = CLK_DIVIDER_POWER_OF_TWO, 309 }; 310 311 static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = { 312 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 313 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL }, 314 { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data }, 315 { 0 }, 316 }; 317 318 static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = { 319 "l3init_960m_gfclk", 320 NULL, 321 }; 322 323 static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = { 324 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL }, 325 { 0 }, 326 }; 327 328 static const char * const dra7_sata_ref_clk_parents[] __initconst = { 329 "sys_clkin1", 330 NULL, 331 }; 332 333 static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = { 334 { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL }, 335 { 0 }, 336 }; 337 338 static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = { 339 { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL }, 340 { 0 }, 341 }; 342 343 static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = { 344 { DRA7_L3INIT_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" }, 345 { DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" }, 346 { DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 347 { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 348 { DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" }, 349 { DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, 350 { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 351 { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 352 { DRA7_L3INIT_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 353 { 0 }, 354 }; 355 356 static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = { 357 "apll_pcie_ck", 358 NULL, 359 }; 360 361 static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = { 362 "optfclk_pciephy_div", 363 NULL, 364 }; 365 366 static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = { 367 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 368 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL }, 369 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL }, 370 { 0 }, 371 }; 372 373 static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = { 374 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 375 { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL }, 376 { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL }, 377 { 0 }, 378 }; 379 380 static const struct omap_clkctrl_reg_data dra7_pcie_clkctrl_regs[] __initconst = { 381 { DRA7_PCIE_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div" }, 382 { DRA7_PCIE_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div" }, 383 { 0 }, 384 }; 385 386 static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = { 387 "dpll_gmac_h11x2_ck", 388 "rmii_clk_ck", 389 NULL, 390 }; 391 392 static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = { 393 "video1_clkin_ck", 394 "video2_clkin_ck", 395 "dpll_abe_m2_ck", 396 "hdmi_clkin_ck", 397 "l3_iclk_div", 398 NULL, 399 }; 400 401 static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = { 402 { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL }, 403 { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL }, 404 { 0 }, 405 }; 406 407 static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = { 408 { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck" }, 409 { 0 }, 410 }; 411 412 static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = { 413 "timer_sys_clk_div", 414 "sys_32k_ck", 415 "sys_clkin2", 416 "ref_clkin0_ck", 417 "ref_clkin1_ck", 418 "ref_clkin2_ck", 419 "ref_clkin3_ck", 420 "abe_giclk_div", 421 "video1_div_clk", 422 "video2_div_clk", 423 "hdmi_div_clk", 424 NULL, 425 }; 426 427 static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = { 428 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 429 { 0 }, 430 }; 431 432 static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = { 433 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 434 { 0 }, 435 }; 436 437 static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = { 438 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 439 { 0 }, 440 }; 441 442 static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = { 443 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 444 { 0 }, 445 }; 446 447 static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = { 448 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 449 { 0 }, 450 }; 451 452 static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = { 453 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 454 { 0 }, 455 }; 456 457 static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = { 458 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 459 { 0 }, 460 }; 461 462 static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = { 463 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 464 { 0 }, 465 }; 466 467 static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = { 468 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 469 { 0 }, 470 }; 471 472 static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = { 473 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 474 { 0 }, 475 }; 476 477 static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = { 478 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 479 { 0 }, 480 }; 481 482 static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = { 483 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 484 { 0 }, 485 }; 486 487 static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = { 488 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 489 { 0 }, 490 }; 491 492 static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = { 493 "l4per-clkctrl:00f8:24", 494 NULL, 495 }; 496 497 static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = { 498 .max_div = 4, 499 .flags = CLK_DIVIDER_POWER_OF_TWO, 500 }; 501 502 static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = { 503 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 504 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 505 { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data }, 506 { 0 }, 507 }; 508 509 static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = { 510 "l4per-clkctrl:0100:24", 511 NULL, 512 }; 513 514 static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = { 515 .max_div = 4, 516 .flags = CLK_DIVIDER_POWER_OF_TWO, 517 }; 518 519 static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = { 520 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 521 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 522 { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data }, 523 { 0 }, 524 }; 525 526 static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = { 527 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 528 { 0 }, 529 }; 530 531 static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = { 532 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 533 { 0 }, 534 }; 535 536 static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = { 537 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 538 { 0 }, 539 }; 540 541 static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = { 542 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 543 { 0 }, 544 }; 545 546 static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = { 547 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 548 { 0 }, 549 }; 550 551 static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = { 552 { DRA7_L4PER_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0000:24" }, 553 { DRA7_L4PER_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" }, 554 { DRA7_L4PER_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" }, 555 { DRA7_L4PER_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" }, 556 { DRA7_L4PER_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" }, 557 { DRA7_L4PER_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" }, 558 { DRA7_L4PER_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 559 { DRA7_L4PER_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 560 { DRA7_L4PER_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 561 { DRA7_L4PER_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 562 { DRA7_L4PER_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 563 { DRA7_L4PER_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 564 { DRA7_L4PER_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" }, 565 { DRA7_L4PER_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 566 { DRA7_L4PER_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 567 { DRA7_L4PER_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 568 { DRA7_L4PER_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 569 { DRA7_L4PER_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 570 { DRA7_L4PER_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 571 { DRA7_L4PER_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 572 { DRA7_L4PER_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 573 { DRA7_L4PER_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 574 { DRA7_L4PER_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 575 { DRA7_L4PER_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, 576 { DRA7_L4PER_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:00f8:25" }, 577 { DRA7_L4PER_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0100:25" }, 578 { DRA7_L4PER_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0118:24" }, 579 { DRA7_L4PER_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0120:24" }, 580 { DRA7_L4PER_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0128:24" }, 581 { DRA7_L4PER_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0130:24" }, 582 { DRA7_L4PER_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0148:24" }, 583 { 0 }, 584 }; 585 586 static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst = { 587 { DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 588 { DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 589 { DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 590 { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" }, 591 { DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 592 { 0 }, 593 }; 594 595 static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = { 596 "func_128m_clk", 597 "dpll_per_h13x2_ck", 598 NULL, 599 }; 600 601 static const char * const dra7_qspi_gfclk_div_parents[] __initconst = { 602 "l4per2-clkctrl:012c:24", 603 NULL, 604 }; 605 606 static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = { 607 .max_div = 4, 608 .flags = CLK_DIVIDER_POWER_OF_TWO, 609 }; 610 611 static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = { 612 { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL }, 613 { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data }, 614 { 0 }, 615 }; 616 617 static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = { 618 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 619 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 620 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 621 { 0 }, 622 }; 623 624 static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = { 625 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 626 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 627 { 0 }, 628 }; 629 630 static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = { 631 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 632 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 633 { 0 }, 634 }; 635 636 static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = { 637 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 638 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 639 { 0 }, 640 }; 641 642 static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = { 643 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 644 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 645 { 0 }, 646 }; 647 648 static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = { 649 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 650 { 0 }, 651 }; 652 653 static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = { 654 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 655 { 0 }, 656 }; 657 658 static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = { 659 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 660 { 0 }, 661 }; 662 663 static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = { 664 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 665 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 666 { 0 }, 667 }; 668 669 static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = { 670 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, 671 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, 672 { 0 }, 673 }; 674 675 static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst = { 676 { DRA7_L4PER2_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 677 { DRA7_L4PER2_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "" }, 678 { DRA7_L4PER2_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "" }, 679 { DRA7_L4PER2_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" }, 680 { DRA7_L4PER2_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" }, 681 { DRA7_L4PER2_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" }, 682 { DRA7_L4PER2_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:012c:25" }, 683 { DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" }, 684 { DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" }, 685 { DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" }, 686 { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:22" }, 687 { DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" }, 688 { DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" }, 689 { DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" }, 690 { DRA7_L4PER2_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01dc:24" }, 691 { DRA7_L4PER2_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1" }, 692 { DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01f8:22" }, 693 { DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01fc:22" }, 694 { 0 }, 695 }; 696 697 static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = { 698 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 699 { 0 }, 700 }; 701 702 static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = { 703 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 704 { 0 }, 705 }; 706 707 static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = { 708 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 709 { 0 }, 710 }; 711 712 static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = { 713 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 714 { 0 }, 715 }; 716 717 static const struct omap_clkctrl_reg_data dra7_l4per3_clkctrl_regs[] __initconst = { 718 { DRA7_L4PER3_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div" }, 719 { DRA7_L4PER3_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00b4:24" }, 720 { DRA7_L4PER3_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00bc:24" }, 721 { DRA7_L4PER3_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00c4:24" }, 722 { DRA7_L4PER3_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:011c:24" }, 723 { 0 }, 724 }; 725 726 static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = { 727 { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, 728 { 0 }, 729 }; 730 731 static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = { 732 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, 733 { 0 }, 734 }; 735 736 static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = { 737 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, 738 { 0 }, 739 }; 740 741 static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = { 742 "sys_clkin1", 743 "sys_clkin2", 744 NULL, 745 }; 746 747 static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = { 748 { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL }, 749 { 0 }, 750 }; 751 752 static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = { 753 { DRA7_WKUPAON_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 754 { DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 755 { DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, 756 { DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" }, 757 { DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" }, 758 { DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 759 { DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" }, 760 { DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" }, 761 { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk" }, 762 { 0 }, 763 }; 764 765 const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = { 766 { 0x4a005320, dra7_mpu_clkctrl_regs }, 767 { 0x4a005420, dra7_dsp1_clkctrl_regs }, 768 { 0x4a005520, dra7_ipu1_clkctrl_regs }, 769 { 0x4a005550, dra7_ipu_clkctrl_regs }, 770 { 0x4a005620, dra7_dsp2_clkctrl_regs }, 771 { 0x4a005720, dra7_rtc_clkctrl_regs }, 772 { 0x4a008620, dra7_coreaon_clkctrl_regs }, 773 { 0x4a008720, dra7_l3main1_clkctrl_regs }, 774 { 0x4a008920, dra7_ipu2_clkctrl_regs }, 775 { 0x4a008a20, dra7_dma_clkctrl_regs }, 776 { 0x4a008b20, dra7_emif_clkctrl_regs }, 777 { 0x4a008c00, dra7_atl_clkctrl_regs }, 778 { 0x4a008d20, dra7_l4cfg_clkctrl_regs }, 779 { 0x4a008e20, dra7_l3instr_clkctrl_regs }, 780 { 0x4a009120, dra7_dss_clkctrl_regs }, 781 { 0x4a009320, dra7_l3init_clkctrl_regs }, 782 { 0x4a0093b0, dra7_pcie_clkctrl_regs }, 783 { 0x4a0093d0, dra7_gmac_clkctrl_regs }, 784 { 0x4a009728, dra7_l4per_clkctrl_regs }, 785 { 0x4a0098a0, dra7_l4sec_clkctrl_regs }, 786 { 0x4a00970c, dra7_l4per2_clkctrl_regs }, 787 { 0x4a009714, dra7_l4per3_clkctrl_regs }, 788 { 0x4ae07820, dra7_wkupaon_clkctrl_regs }, 789 { 0 }, 790 }; 791 792 static struct ti_dt_clk dra7xx_clks[] = { 793 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 794 DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"), 795 DT_CLK(NULL, "sys_clkin", "sys_clkin1"), 796 DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"), 797 DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"), 798 DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"), 799 DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"), 800 DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"), 801 DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"), 802 DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"), 803 DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"), 804 DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"), 805 DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"), 806 DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"), 807 DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"), 808 DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"), 809 DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"), 810 DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"), 811 DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"), 812 DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"), 813 DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"), 814 DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"), 815 DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"), 816 DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"), 817 DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"), 818 DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"), 819 DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"), 820 DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"), 821 DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"), 822 DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"), 823 DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"), 824 DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"), 825 DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"), 826 DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"), 827 DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"), 828 DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"), 829 DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"), 830 DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"), 831 DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"), 832 DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"), 833 DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"), 834 DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"), 835 DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"), 836 DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"), 837 DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"), 838 DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"), 839 DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"), 840 DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"), 841 DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"), 842 DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"), 843 DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"), 844 DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"), 845 DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"), 846 DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"), 847 DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"), 848 DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"), 849 DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"), 850 DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"), 851 DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"), 852 DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"), 853 DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"), 854 DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"), 855 DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"), 856 DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"), 857 DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"), 858 DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"), 859 DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"), 860 DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"), 861 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"), 862 DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"), 863 DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"), 864 DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"), 865 DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"), 866 DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"), 867 DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"), 868 DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"), 869 DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"), 870 DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"), 871 DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"), 872 DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"), 873 DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"), 874 DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"), 875 DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"), 876 DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"), 877 DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"), 878 DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"), 879 DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"), 880 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"), 881 DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"), 882 { .node_name = NULL }, 883 }; 884 885 int __init dra7xx_dt_clk_init(void) 886 { 887 int rc; 888 struct clk *dpll_ck, *hdcp_ck; 889 890 if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) 891 ti_dt_clocks_register(dra7xx_compat_clks); 892 else 893 ti_dt_clocks_register(dra7xx_clks); 894 895 omap2_clk_disable_autoidle_all(); 896 897 ti_clk_add_aliases(); 898 899 dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); 900 rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); 901 if (rc) 902 pr_err("%s: failed to configure GMAC DPLL!\n", __func__); 903 904 dpll_ck = clk_get_sys(NULL, "dpll_usb_ck"); 905 rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ); 906 if (rc) 907 pr_err("%s: failed to configure USB DPLL!\n", __func__); 908 909 dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck"); 910 rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2); 911 if (rc) 912 pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); 913 914 hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk"); 915 rc = clk_prepare_enable(hdcp_ck); 916 if (rc) 917 pr_err("%s: failed to set dss_deshdcp_clk\n", __func__); 918 919 return rc; 920 } 921