1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 252b14728STero Kristo /* 352b14728STero Kristo * OMAP5 Clock init 452b14728STero Kristo * 552b14728STero Kristo * Copyright (C) 2013 Texas Instruments, Inc. 652b14728STero Kristo * 752b14728STero Kristo * Tero Kristo (t-kristo@ti.com) 852b14728STero Kristo */ 952b14728STero Kristo 1052b14728STero Kristo #include <linux/kernel.h> 1152b14728STero Kristo #include <linux/list.h> 12e387088aSStephen Boyd #include <linux/clk.h> 1352b14728STero Kristo #include <linux/clkdev.h> 1452b14728STero Kristo #include <linux/io.h> 1552b14728STero Kristo #include <linux/clk/ti.h> 160ad902f6STero Kristo #include <dt-bindings/clock/omap5.h> 1752b14728STero Kristo 18a3314e9cSTero Kristo #include "clock.h" 19a3314e9cSTero Kristo 2052b14728STero Kristo #define OMAP5_DPLL_ABE_DEFFREQ 98304000 2152b14728STero Kristo 2262125a46SRoger Quadros /* 2362125a46SRoger Quadros * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings" 2462125a46SRoger Quadros * states it must be at 960MHz 2562125a46SRoger Quadros */ 2662125a46SRoger Quadros #define OMAP5_DPLL_USB_DEFFREQ 960000000 2762125a46SRoger Quadros 280ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = { 290ad902f6STero Kristo { OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" }, 300ad902f6STero Kristo { 0 }, 310ad902f6STero Kristo }; 320ad902f6STero Kristo 330ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = { 340ad902f6STero Kristo { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h11x2_ck" }, 350ad902f6STero Kristo { 0 }, 360ad902f6STero Kristo }; 370ad902f6STero Kristo 380ad902f6STero Kristo static const char * const omap5_dmic_gfclk_parents[] __initconst = { 390ad902f6STero Kristo "abe_cm:clk:0018:26", 400ad902f6STero Kristo "pad_clks_ck", 410ad902f6STero Kristo "slimbus_clk", 420ad902f6STero Kristo NULL, 430ad902f6STero Kristo }; 440ad902f6STero Kristo 450ad902f6STero Kristo static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = { 460ad902f6STero Kristo "abe_24m_fclk", 470ad902f6STero Kristo "dss_syc_gfclk_div", 480ad902f6STero Kristo "func_24m_clk", 490ad902f6STero Kristo NULL, 500ad902f6STero Kristo }; 510ad902f6STero Kristo 520ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = { 530ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL }, 540ad902f6STero Kristo { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, 550ad902f6STero Kristo { 0 }, 560ad902f6STero Kristo }; 570ad902f6STero Kristo 580ad902f6STero Kristo static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = { 590ad902f6STero Kristo "abe_cm:clk:0028:26", 600ad902f6STero Kristo "pad_clks_ck", 610ad902f6STero Kristo "slimbus_clk", 620ad902f6STero Kristo NULL, 630ad902f6STero Kristo }; 640ad902f6STero Kristo 650ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = { 660ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL }, 670ad902f6STero Kristo { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, 680ad902f6STero Kristo { 0 }, 690ad902f6STero Kristo }; 700ad902f6STero Kristo 710ad902f6STero Kristo static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = { 720ad902f6STero Kristo "abe_cm:clk:0030:26", 730ad902f6STero Kristo "pad_clks_ck", 740ad902f6STero Kristo "slimbus_clk", 750ad902f6STero Kristo NULL, 760ad902f6STero Kristo }; 770ad902f6STero Kristo 780ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = { 790ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL }, 800ad902f6STero Kristo { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, 810ad902f6STero Kristo { 0 }, 820ad902f6STero Kristo }; 830ad902f6STero Kristo 840ad902f6STero Kristo static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = { 850ad902f6STero Kristo "abe_cm:clk:0038:26", 860ad902f6STero Kristo "pad_clks_ck", 870ad902f6STero Kristo "slimbus_clk", 880ad902f6STero Kristo NULL, 890ad902f6STero Kristo }; 900ad902f6STero Kristo 910ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = { 920ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL }, 930ad902f6STero Kristo { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, 940ad902f6STero Kristo { 0 }, 950ad902f6STero Kristo }; 960ad902f6STero Kristo 970ad902f6STero Kristo static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = { 980ad902f6STero Kristo "dss_syc_gfclk_div", 990ad902f6STero Kristo "sys_32k_ck", 1000ad902f6STero Kristo NULL, 1010ad902f6STero Kristo }; 1020ad902f6STero Kristo 1030ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = { 1040ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, 1050ad902f6STero Kristo { 0 }, 1060ad902f6STero Kristo }; 1070ad902f6STero Kristo 1080ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = { 1090ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, 1100ad902f6STero Kristo { 0 }, 1110ad902f6STero Kristo }; 1120ad902f6STero Kristo 1130ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = { 1140ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, 1150ad902f6STero Kristo { 0 }, 1160ad902f6STero Kristo }; 1170ad902f6STero Kristo 1180ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = { 1190ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, 1200ad902f6STero Kristo { 0 }, 1210ad902f6STero Kristo }; 1220ad902f6STero Kristo 1230ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = { 1240ad902f6STero Kristo { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" }, 1250ad902f6STero Kristo { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" }, 1260ad902f6STero Kristo { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" }, 1270ad902f6STero Kristo { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" }, 1280ad902f6STero Kristo { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" }, 1290ad902f6STero Kristo { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" }, 1300ad902f6STero Kristo { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" }, 1310ad902f6STero Kristo { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" }, 1320ad902f6STero Kristo { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" }, 1330ad902f6STero Kristo { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" }, 1340ad902f6STero Kristo { 0 }, 1350ad902f6STero Kristo }; 1360ad902f6STero Kristo 1370ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = { 1380ad902f6STero Kristo { OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 1390ad902f6STero Kristo { 0 }, 1400ad902f6STero Kristo }; 1410ad902f6STero Kristo 1420ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = { 1430ad902f6STero Kristo { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 1440ad902f6STero Kristo { 0 }, 1450ad902f6STero Kristo }; 1460ad902f6STero Kristo 1470ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = { 1480ad902f6STero Kristo { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" }, 1490ad902f6STero Kristo { 0 }, 1500ad902f6STero Kristo }; 1510ad902f6STero Kristo 1520ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = { 1530ad902f6STero Kristo { OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 1540ad902f6STero Kristo { 0 }, 1550ad902f6STero Kristo }; 1560ad902f6STero Kristo 1570ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = { 1580ad902f6STero Kristo { OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 1590ad902f6STero Kristo { OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" }, 1600ad902f6STero Kristo { OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" }, 1610ad902f6STero Kristo { 0 }, 1620ad902f6STero Kristo }; 1630ad902f6STero Kristo 1640ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = { 1650ad902f6STero Kristo { OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" }, 1660ad902f6STero Kristo { OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" }, 1670ad902f6STero Kristo { OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" }, 1680ad902f6STero Kristo { 0 }, 1690ad902f6STero Kristo }; 1700ad902f6STero Kristo 1710ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = { 1720ad902f6STero Kristo { OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 1730ad902f6STero Kristo { OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 1740ad902f6STero Kristo { 0 }, 1750ad902f6STero Kristo }; 1760ad902f6STero Kristo 1770ad902f6STero Kristo static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = { 1780ad902f6STero Kristo "sys_clkin", 1790ad902f6STero Kristo "sys_32k_ck", 1800ad902f6STero Kristo NULL, 1810ad902f6STero Kristo }; 1820ad902f6STero Kristo 1830ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = { 1840ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 1850ad902f6STero Kristo { 0 }, 1860ad902f6STero Kristo }; 1870ad902f6STero Kristo 1880ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = { 1890ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 1900ad902f6STero Kristo { 0 }, 1910ad902f6STero Kristo }; 1920ad902f6STero Kristo 1930ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = { 1940ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 1950ad902f6STero Kristo { 0 }, 1960ad902f6STero Kristo }; 1970ad902f6STero Kristo 1980ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = { 1990ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 2000ad902f6STero Kristo { 0 }, 2010ad902f6STero Kristo }; 2020ad902f6STero Kristo 2030ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = { 2040ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 2050ad902f6STero Kristo { 0 }, 2060ad902f6STero Kristo }; 2070ad902f6STero Kristo 2080ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = { 2090ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 2100ad902f6STero Kristo { 0 }, 2110ad902f6STero Kristo }; 2120ad902f6STero Kristo 2130ad902f6STero Kristo static const char * const omap5_gpio2_dbclk_parents[] __initconst = { 2140ad902f6STero Kristo "sys_32k_ck", 2150ad902f6STero Kristo NULL, 2160ad902f6STero Kristo }; 2170ad902f6STero Kristo 2180ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = { 2190ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 2200ad902f6STero Kristo { 0 }, 2210ad902f6STero Kristo }; 2220ad902f6STero Kristo 2230ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = { 2240ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 2250ad902f6STero Kristo { 0 }, 2260ad902f6STero Kristo }; 2270ad902f6STero Kristo 2280ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = { 2290ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 2300ad902f6STero Kristo { 0 }, 2310ad902f6STero Kristo }; 2320ad902f6STero Kristo 2330ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = { 2340ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 2350ad902f6STero Kristo { 0 }, 2360ad902f6STero Kristo }; 2370ad902f6STero Kristo 2380ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = { 2390ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 2400ad902f6STero Kristo { 0 }, 2410ad902f6STero Kristo }; 2420ad902f6STero Kristo 2430ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = { 2440ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 2450ad902f6STero Kristo { 0 }, 2460ad902f6STero Kristo }; 2470ad902f6STero Kristo 2480ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = { 2490ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 2500ad902f6STero Kristo { 0 }, 2510ad902f6STero Kristo }; 2520ad902f6STero Kristo 2530ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = { 2540ad902f6STero Kristo { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" }, 2550ad902f6STero Kristo { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" }, 2560ad902f6STero Kristo { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" }, 2570ad902f6STero Kristo { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" }, 2580ad902f6STero Kristo { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" }, 2590ad902f6STero Kristo { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" }, 2600ad902f6STero Kristo { OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 2610ad902f6STero Kristo { OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 2620ad902f6STero Kristo { OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 2630ad902f6STero Kristo { OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 2640ad902f6STero Kristo { OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 2650ad902f6STero Kristo { OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 2660ad902f6STero Kristo { OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 2670ad902f6STero Kristo { OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 2680ad902f6STero Kristo { OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 2690ad902f6STero Kristo { OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" }, 2700ad902f6STero Kristo { OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2710ad902f6STero Kristo { OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2720ad902f6STero Kristo { OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2730ad902f6STero Kristo { OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2740ad902f6STero Kristo { OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 2750ad902f6STero Kristo { OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 2760ad902f6STero Kristo { OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2770ad902f6STero Kristo { OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2780ad902f6STero Kristo { OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2790ad902f6STero Kristo { OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2800ad902f6STero Kristo { OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2810ad902f6STero Kristo { OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2820ad902f6STero Kristo { OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 2830ad902f6STero Kristo { OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 2840ad902f6STero Kristo { OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2850ad902f6STero Kristo { OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 2860ad902f6STero Kristo { 0 }, 2870ad902f6STero Kristo }; 2880ad902f6STero Kristo 2890ad902f6STero Kristo static const char * const omap5_dss_dss_clk_parents[] __initconst = { 2900ad902f6STero Kristo "dpll_per_h12x2_ck", 2910ad902f6STero Kristo NULL, 2920ad902f6STero Kristo }; 2930ad902f6STero Kristo 2940ad902f6STero Kristo static const char * const omap5_dss_48mhz_clk_parents[] __initconst = { 2950ad902f6STero Kristo "func_48m_fclk", 2960ad902f6STero Kristo NULL, 2970ad902f6STero Kristo }; 2980ad902f6STero Kristo 2990ad902f6STero Kristo static const char * const omap5_dss_sys_clk_parents[] __initconst = { 3000ad902f6STero Kristo "dss_syc_gfclk_div", 3010ad902f6STero Kristo NULL, 3020ad902f6STero Kristo }; 3030ad902f6STero Kristo 3040ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = { 3050ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL }, 3060ad902f6STero Kristo { 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL }, 3070ad902f6STero Kristo { 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL }, 3080ad902f6STero Kristo { 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 3090ad902f6STero Kristo { 0 }, 3100ad902f6STero Kristo }; 3110ad902f6STero Kristo 3120ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = { 3130ad902f6STero Kristo { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" }, 3140ad902f6STero Kristo { 0 }, 3150ad902f6STero Kristo }; 3160ad902f6STero Kristo 317*fd568374STony Lindgren static const char * const omap5_gpu_core_mux_parents[] __initconst = { 318*fd568374STony Lindgren "dpll_core_h14x2_ck", 319*fd568374STony Lindgren "dpll_per_h14x2_ck", 320*fd568374STony Lindgren NULL, 321*fd568374STony Lindgren }; 322*fd568374STony Lindgren 323*fd568374STony Lindgren static const char * const omap5_gpu_hyd_mux_parents[] __initconst = { 324*fd568374STony Lindgren "dpll_core_h14x2_ck", 325*fd568374STony Lindgren "dpll_per_h14x2_ck", 326*fd568374STony Lindgren NULL, 327*fd568374STony Lindgren }; 328*fd568374STony Lindgren 329*fd568374STony Lindgren static const char * const omap5_gpu_sys_clk_parents[] __initconst = { 330*fd568374STony Lindgren "sys_clkin", 331*fd568374STony Lindgren NULL, 332*fd568374STony Lindgren }; 333*fd568374STony Lindgren 334*fd568374STony Lindgren static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = { 335*fd568374STony Lindgren .max_div = 2, 336*fd568374STony Lindgren }; 337*fd568374STony Lindgren 338*fd568374STony Lindgren static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = { 339*fd568374STony Lindgren { 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL }, 340*fd568374STony Lindgren { 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL }, 341*fd568374STony Lindgren { 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data }, 342*fd568374STony Lindgren { 0 }, 343*fd568374STony Lindgren }; 344*fd568374STony Lindgren 345*fd568374STony Lindgren static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = { 346*fd568374STony Lindgren { OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" }, 347*fd568374STony Lindgren { 0 }, 348*fd568374STony Lindgren }; 349*fd568374STony Lindgren 3500ad902f6STero Kristo static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = { 3510ad902f6STero Kristo "func_128m_clk", 3520ad902f6STero Kristo "dpll_per_m2x2_ck", 3530ad902f6STero Kristo NULL, 3540ad902f6STero Kristo }; 3550ad902f6STero Kristo 3560ad902f6STero Kristo static const char * const omap5_mmc1_fclk_parents[] __initconst = { 3570ad902f6STero Kristo "l3init_cm:clk:0008:24", 3580ad902f6STero Kristo NULL, 3590ad902f6STero Kristo }; 3600ad902f6STero Kristo 3610ad902f6STero Kristo static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = { 3620ad902f6STero Kristo .max_div = 2, 3630ad902f6STero Kristo }; 3640ad902f6STero Kristo 3650ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = { 3660ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 3670ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL }, 3680ad902f6STero Kristo { 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data }, 3690ad902f6STero Kristo { 0 }, 3700ad902f6STero Kristo }; 3710ad902f6STero Kristo 3720ad902f6STero Kristo static const char * const omap5_mmc2_fclk_parents[] __initconst = { 3730ad902f6STero Kristo "l3init_cm:clk:0010:24", 3740ad902f6STero Kristo NULL, 3750ad902f6STero Kristo }; 3760ad902f6STero Kristo 3770ad902f6STero Kristo static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = { 3780ad902f6STero Kristo .max_div = 2, 3790ad902f6STero Kristo }; 3800ad902f6STero Kristo 3810ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = { 3820ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL }, 3830ad902f6STero Kristo { 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data }, 3840ad902f6STero Kristo { 0 }, 3850ad902f6STero Kristo }; 3860ad902f6STero Kristo 3870ad902f6STero Kristo static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = { 3880ad902f6STero Kristo "l3init_60m_fclk", 3890ad902f6STero Kristo NULL, 3900ad902f6STero Kristo }; 3910ad902f6STero Kristo 3920ad902f6STero Kristo static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = { 3930ad902f6STero Kristo "dpll_usb_m2_ck", 3940ad902f6STero Kristo NULL, 3950ad902f6STero Kristo }; 3960ad902f6STero Kristo 3970ad902f6STero Kristo static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = { 3980ad902f6STero Kristo "l3init_cm:clk:0038:24", 3990ad902f6STero Kristo NULL, 4000ad902f6STero Kristo }; 4010ad902f6STero Kristo 4020ad902f6STero Kristo static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = { 4030ad902f6STero Kristo "l3init_cm:clk:0038:25", 4040ad902f6STero Kristo NULL, 4050ad902f6STero Kristo }; 4060ad902f6STero Kristo 4070ad902f6STero Kristo static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = { 4080ad902f6STero Kristo "l3init_60m_fclk", 4090ad902f6STero Kristo "xclk60mhsp1_ck", 4100ad902f6STero Kristo NULL, 4110ad902f6STero Kristo }; 4120ad902f6STero Kristo 4130ad902f6STero Kristo static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = { 4140ad902f6STero Kristo "l3init_60m_fclk", 4150ad902f6STero Kristo "xclk60mhsp2_ck", 4160ad902f6STero Kristo NULL, 4170ad902f6STero Kristo }; 4180ad902f6STero Kristo 4190ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = { 4200ad902f6STero Kristo { 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 4210ad902f6STero Kristo { 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL }, 4220ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL }, 4230ad902f6STero Kristo { 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL }, 4240ad902f6STero Kristo { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 4250ad902f6STero Kristo { 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 4260ad902f6STero Kristo { 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 4270ad902f6STero Kristo { 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL }, 4280ad902f6STero Kristo { 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL }, 4290ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL }, 4300ad902f6STero Kristo { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL }, 4310ad902f6STero Kristo { 0 }, 4320ad902f6STero Kristo }; 4330ad902f6STero Kristo 4340ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = { 4350ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 4360ad902f6STero Kristo { 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 4370ad902f6STero Kristo { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 4380ad902f6STero Kristo { 0 }, 4390ad902f6STero Kristo }; 4400ad902f6STero Kristo 4410ad902f6STero Kristo static const char * const omap5_sata_ref_clk_parents[] __initconst = { 4420ad902f6STero Kristo "sys_clkin", 4430ad902f6STero Kristo NULL, 4440ad902f6STero Kristo }; 4450ad902f6STero Kristo 4460ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = { 4470ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL }, 4480ad902f6STero Kristo { 0 }, 4490ad902f6STero Kristo }; 4500ad902f6STero Kristo 4510ad902f6STero Kristo static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = { 4520ad902f6STero Kristo "dpll_usb_clkdcoldo", 4530ad902f6STero Kristo NULL, 4540ad902f6STero Kristo }; 4550ad902f6STero Kristo 4560ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = { 4570ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL }, 4580ad902f6STero Kristo { 0 }, 4590ad902f6STero Kristo }; 4600ad902f6STero Kristo 4610ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = { 4620ad902f6STero Kristo { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" }, 4630ad902f6STero Kristo { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" }, 4640ad902f6STero Kristo { OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" }, 4650ad902f6STero Kristo { OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 4660ad902f6STero Kristo { OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, 4670ad902f6STero Kristo { OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 4680ad902f6STero Kristo { OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 4690ad902f6STero Kristo { OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 4700ad902f6STero Kristo { 0 }, 4710ad902f6STero Kristo }; 4720ad902f6STero Kristo 4730ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = { 4740ad902f6STero Kristo { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 4750ad902f6STero Kristo { 0 }, 4760ad902f6STero Kristo }; 4770ad902f6STero Kristo 4780ad902f6STero Kristo static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = { 4790ad902f6STero Kristo { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 4800ad902f6STero Kristo { 0 }, 4810ad902f6STero Kristo }; 4820ad902f6STero Kristo 4830ad902f6STero Kristo static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = { 4840ad902f6STero Kristo { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 4850ad902f6STero Kristo { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 4860ad902f6STero Kristo { OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, 4870ad902f6STero Kristo { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" }, 4880ad902f6STero Kristo { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 4890ad902f6STero Kristo { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 4900ad902f6STero Kristo { 0 }, 4910ad902f6STero Kristo }; 4920ad902f6STero Kristo 4930ad902f6STero Kristo const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = { 4940ad902f6STero Kristo { 0x4a004320, omap5_mpu_clkctrl_regs }, 4950ad902f6STero Kristo { 0x4a004420, omap5_dsp_clkctrl_regs }, 4960ad902f6STero Kristo { 0x4a004520, omap5_abe_clkctrl_regs }, 4970ad902f6STero Kristo { 0x4a008720, omap5_l3main1_clkctrl_regs }, 4980ad902f6STero Kristo { 0x4a008820, omap5_l3main2_clkctrl_regs }, 4990ad902f6STero Kristo { 0x4a008920, omap5_ipu_clkctrl_regs }, 5000ad902f6STero Kristo { 0x4a008a20, omap5_dma_clkctrl_regs }, 5010ad902f6STero Kristo { 0x4a008b20, omap5_emif_clkctrl_regs }, 5020ad902f6STero Kristo { 0x4a008d20, omap5_l4cfg_clkctrl_regs }, 5030ad902f6STero Kristo { 0x4a008e20, omap5_l3instr_clkctrl_regs }, 5040ad902f6STero Kristo { 0x4a009020, omap5_l4per_clkctrl_regs }, 5050ad902f6STero Kristo { 0x4a009420, omap5_dss_clkctrl_regs }, 506*fd568374STony Lindgren { 0x4a009520, omap5_gpu_clkctrl_regs }, 5070ad902f6STero Kristo { 0x4a009620, omap5_l3init_clkctrl_regs }, 5080ad902f6STero Kristo { 0x4ae07920, omap5_wkupaon_clkctrl_regs }, 5090ad902f6STero Kristo { 0 }, 5100ad902f6STero Kristo }; 5110ad902f6STero Kristo 51252b14728STero Kristo static struct ti_dt_clk omap54xx_clks[] = { 51352b14728STero Kristo DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 514d5630b7aSGrygorii Strashko DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"), 5150ad902f6STero Kristo DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"), 5160ad902f6STero Kristo DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"), 5170ad902f6STero Kristo DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"), 5180ad902f6STero Kristo DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"), 5190ad902f6STero Kristo DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"), 5200ad902f6STero Kristo DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"), 5210ad902f6STero Kristo DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"), 5220ad902f6STero Kristo DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"), 5230ad902f6STero Kristo DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"), 5240ad902f6STero Kristo DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"), 5250ad902f6STero Kristo DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"), 5260ad902f6STero Kristo DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"), 5270ad902f6STero Kristo DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"), 5280ad902f6STero Kristo DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"), 5290ad902f6STero Kristo DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"), 5300ad902f6STero Kristo DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"), 5310ad902f6STero Kristo DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"), 5320ad902f6STero Kristo DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"), 5330ad902f6STero Kristo DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"), 5340ad902f6STero Kristo DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"), 5350ad902f6STero Kristo DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"), 5360ad902f6STero Kristo DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"), 5370ad902f6STero Kristo DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"), 5380ad902f6STero Kristo DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"), 5390ad902f6STero Kristo DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"), 5400ad902f6STero Kristo DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"), 5410ad902f6STero Kristo DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"), 5420ad902f6STero Kristo DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"), 5430ad902f6STero Kristo DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"), 5440ad902f6STero Kristo DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"), 5450ad902f6STero Kristo DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"), 5460ad902f6STero Kristo DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"), 5470ad902f6STero Kristo DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"), 5480ad902f6STero Kristo DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"), 5490ad902f6STero Kristo DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"), 5500ad902f6STero Kristo DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"), 5510ad902f6STero Kristo DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"), 5520ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"), 5530ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"), 5540ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"), 5550ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"), 5560ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"), 5570ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"), 5580ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"), 5590ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"), 5600ad902f6STero Kristo DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"), 5610ad902f6STero Kristo DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"), 5620ad902f6STero Kristo DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"), 5630ad902f6STero Kristo DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"), 5640ad902f6STero Kristo DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"), 5650ad902f6STero Kristo DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"), 5660ad902f6STero Kristo DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"), 56752b14728STero Kristo { .node_name = NULL }, 56852b14728STero Kristo }; 56952b14728STero Kristo 57052b14728STero Kristo int __init omap5xxx_dt_clk_init(void) 57152b14728STero Kristo { 57252b14728STero Kristo int rc; 57362125a46SRoger Quadros struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; 57452b14728STero Kristo 57552b14728STero Kristo ti_dt_clocks_register(omap54xx_clks); 57652b14728STero Kristo 57752b14728STero Kristo omap2_clk_disable_autoidle_all(); 57852b14728STero Kristo 579d41e5304STero Kristo ti_clk_add_aliases(); 580d41e5304STero Kristo 58152b14728STero Kristo abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux"); 58252b14728STero Kristo sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); 58352b14728STero Kristo rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); 58452b14728STero Kristo abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); 58552b14728STero Kristo if (!rc) 58652b14728STero Kristo rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ); 58752b14728STero Kristo if (rc) 58852b14728STero Kristo pr_err("%s: failed to configure ABE DPLL!\n", __func__); 58952b14728STero Kristo 59081c7e03aSPeter Ujfalusi abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck"); 59181c7e03aSPeter Ujfalusi if (!rc) 59281c7e03aSPeter Ujfalusi rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2); 59381c7e03aSPeter Ujfalusi if (rc) 59481c7e03aSPeter Ujfalusi pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__); 59581c7e03aSPeter Ujfalusi 59662125a46SRoger Quadros usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); 59762125a46SRoger Quadros rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ); 59862125a46SRoger Quadros if (rc) 59962125a46SRoger Quadros pr_err("%s: failed to configure USB DPLL!\n", __func__); 60062125a46SRoger Quadros 60162125a46SRoger Quadros usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck"); 60262125a46SRoger Quadros rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2); 60362125a46SRoger Quadros if (rc) 60462125a46SRoger Quadros pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); 60562125a46SRoger Quadros 60652b14728STero Kristo return 0; 60752b14728STero Kristo } 608