1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * OMAP4 Clock init 4 * 5 * Copyright (C) 2013 Texas Instruments, Inc. 6 * 7 * Tero Kristo (t-kristo@ti.com) 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/list.h> 12 #include <linux/clk.h> 13 #include <linux/clkdev.h> 14 #include <linux/clk/ti.h> 15 #include <dt-bindings/clock/omap4.h> 16 17 #include "clock.h" 18 19 /* 20 * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section 21 * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK 22 * must be set to 196.608 MHz" and hence, the DPLL locked frequency is 23 * half of this value. 24 */ 25 #define OMAP4_DPLL_ABE_DEFFREQ 98304000 26 27 /* 28 * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section 29 * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred 30 * locked frequency for the USB DPLL is 960MHz. 31 */ 32 #define OMAP4_DPLL_USB_DEFFREQ 960000000 33 34 static const struct omap_clkctrl_reg_data omap4_mpuss_clkctrl_regs[] __initconst = { 35 { OMAP4_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" }, 36 { 0 }, 37 }; 38 39 static const struct omap_clkctrl_reg_data omap4_tesla_clkctrl_regs[] __initconst = { 40 { OMAP4_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_m4x2_ck" }, 41 { 0 }, 42 }; 43 44 static const char * const omap4_aess_fclk_parents[] __initconst = { 45 "abe_clk", 46 NULL, 47 }; 48 49 static const struct omap_clkctrl_div_data omap4_aess_fclk_data __initconst = { 50 .max_div = 2, 51 }; 52 53 static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = { 54 { 24, TI_CLK_DIVIDER, omap4_aess_fclk_parents, &omap4_aess_fclk_data }, 55 { 0 }, 56 }; 57 58 static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = { 59 "abe_cm:clk:0018:26", 60 "pad_clks_ck", 61 "slimbus_clk", 62 NULL, 63 }; 64 65 static const char * const omap4_dmic_sync_mux_ck_parents[] __initconst = { 66 "abe_24m_fclk", 67 "syc_clk_div_ck", 68 "func_24m_clk", 69 NULL, 70 }; 71 72 static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = { 73 { 24, TI_CLK_MUX, omap4_func_dmic_abe_gfclk_parents, NULL }, 74 { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL }, 75 { 0 }, 76 }; 77 78 static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = { 79 "abe_cm:clk:0020:26", 80 "pad_clks_ck", 81 "slimbus_clk", 82 NULL, 83 }; 84 85 static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = { 86 { 24, TI_CLK_MUX, omap4_func_mcasp_abe_gfclk_parents, NULL }, 87 { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL }, 88 { 0 }, 89 }; 90 91 static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = { 92 "abe_cm:clk:0028:26", 93 "pad_clks_ck", 94 "slimbus_clk", 95 NULL, 96 }; 97 98 static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst = { 99 { 24, TI_CLK_MUX, omap4_func_mcbsp1_gfclk_parents, NULL }, 100 { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL }, 101 { 0 }, 102 }; 103 104 static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = { 105 "abe_cm:clk:0030:26", 106 "pad_clks_ck", 107 "slimbus_clk", 108 NULL, 109 }; 110 111 static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst = { 112 { 24, TI_CLK_MUX, omap4_func_mcbsp2_gfclk_parents, NULL }, 113 { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL }, 114 { 0 }, 115 }; 116 117 static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = { 118 "abe_cm:clk:0038:26", 119 "pad_clks_ck", 120 "slimbus_clk", 121 NULL, 122 }; 123 124 static const struct omap_clkctrl_bit_data omap4_mcbsp3_bit_data[] __initconst = { 125 { 24, TI_CLK_MUX, omap4_func_mcbsp3_gfclk_parents, NULL }, 126 { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL }, 127 { 0 }, 128 }; 129 130 static const char * const omap4_slimbus1_fclk_0_parents[] __initconst = { 131 "abe_24m_fclk", 132 NULL, 133 }; 134 135 static const char * const omap4_slimbus1_fclk_1_parents[] __initconst = { 136 "func_24m_clk", 137 NULL, 138 }; 139 140 static const char * const omap4_slimbus1_fclk_2_parents[] __initconst = { 141 "pad_clks_ck", 142 NULL, 143 }; 144 145 static const char * const omap4_slimbus1_slimbus_clk_parents[] __initconst = { 146 "slimbus_clk", 147 NULL, 148 }; 149 150 static const struct omap_clkctrl_bit_data omap4_slimbus1_bit_data[] __initconst = { 151 { 8, TI_CLK_GATE, omap4_slimbus1_fclk_0_parents, NULL }, 152 { 9, TI_CLK_GATE, omap4_slimbus1_fclk_1_parents, NULL }, 153 { 10, TI_CLK_GATE, omap4_slimbus1_fclk_2_parents, NULL }, 154 { 11, TI_CLK_GATE, omap4_slimbus1_slimbus_clk_parents, NULL }, 155 { 0 }, 156 }; 157 158 static const char * const omap4_timer5_sync_mux_parents[] __initconst = { 159 "syc_clk_div_ck", 160 "sys_32k_ck", 161 NULL, 162 }; 163 164 static const struct omap_clkctrl_bit_data omap4_timer5_bit_data[] __initconst = { 165 { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL }, 166 { 0 }, 167 }; 168 169 static const struct omap_clkctrl_bit_data omap4_timer6_bit_data[] __initconst = { 170 { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL }, 171 { 0 }, 172 }; 173 174 static const struct omap_clkctrl_bit_data omap4_timer7_bit_data[] __initconst = { 175 { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL }, 176 { 0 }, 177 }; 178 179 static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst = { 180 { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL }, 181 { 0 }, 182 }; 183 184 static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = { 185 { OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" }, 186 { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" }, 187 { OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" }, 188 { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" }, 189 { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe_cm:clk:0020:24" }, 190 { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" }, 191 { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" }, 192 { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" }, 193 { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0040:8" }, 194 { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" }, 195 { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" }, 196 { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" }, 197 { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" }, 198 { OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 199 { 0 }, 200 }; 201 202 static const struct omap_clkctrl_reg_data omap4_l4_ao_clkctrl_regs[] __initconst = { 203 { OMAP4_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" }, 204 { OMAP4_SMARTREFLEX_IVA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" }, 205 { OMAP4_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" }, 206 { 0 }, 207 }; 208 209 static const struct omap_clkctrl_reg_data omap4_l3_1_clkctrl_regs[] __initconst = { 210 { OMAP4_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_div_ck" }, 211 { 0 }, 212 }; 213 214 static const struct omap_clkctrl_reg_data omap4_l3_2_clkctrl_regs[] __initconst = { 215 { OMAP4_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_div_ck" }, 216 { OMAP4_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" }, 217 { OMAP4_OCMC_RAM_CLKCTRL, NULL, 0, "l3_div_ck" }, 218 { 0 }, 219 }; 220 221 static const struct omap_clkctrl_reg_data omap4_ducati_clkctrl_regs[] __initconst = { 222 { OMAP4_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "ducati_clk_mux_ck" }, 223 { 0 }, 224 }; 225 226 static const struct omap_clkctrl_reg_data omap4_l3_dma_clkctrl_regs[] __initconst = { 227 { OMAP4_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_div_ck" }, 228 { 0 }, 229 }; 230 231 static const struct omap_clkctrl_reg_data omap4_l3_emif_clkctrl_regs[] __initconst = { 232 { OMAP4_DMM_CLKCTRL, NULL, 0, "l3_div_ck" }, 233 { OMAP4_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" }, 234 { OMAP4_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" }, 235 { 0 }, 236 }; 237 238 static const struct omap_clkctrl_reg_data omap4_d2d_clkctrl_regs[] __initconst = { 239 { OMAP4_C2C_CLKCTRL, NULL, 0, "div_core_ck" }, 240 { 0 }, 241 }; 242 243 static const struct omap_clkctrl_reg_data omap4_l4_cfg_clkctrl_regs[] __initconst = { 244 { OMAP4_L4_CFG_CLKCTRL, NULL, 0, "l4_div_ck" }, 245 { OMAP4_SPINLOCK_CLKCTRL, NULL, 0, "l4_div_ck" }, 246 { OMAP4_MAILBOX_CLKCTRL, NULL, 0, "l4_div_ck" }, 247 { 0 }, 248 }; 249 250 static const struct omap_clkctrl_reg_data omap4_l3_instr_clkctrl_regs[] __initconst = { 251 { OMAP4_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" }, 252 { OMAP4_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" }, 253 { OMAP4_OCP_WP_NOC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" }, 254 { 0 }, 255 }; 256 257 static const struct omap_clkctrl_reg_data omap4_ivahd_clkctrl_regs[] __initconst = { 258 { OMAP4_IVA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_m5x2_ck" }, 259 { OMAP4_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" }, 260 { 0 }, 261 }; 262 263 static const char * const omap4_iss_ctrlclk_parents[] __initconst = { 264 "func_96m_fclk", 265 NULL, 266 }; 267 268 static const struct omap_clkctrl_bit_data omap4_iss_bit_data[] __initconst = { 269 { 8, TI_CLK_GATE, omap4_iss_ctrlclk_parents, NULL }, 270 { 0 }, 271 }; 272 273 static const char * const omap4_fdif_fck_parents[] __initconst = { 274 "dpll_per_m4x2_ck", 275 NULL, 276 }; 277 278 static const struct omap_clkctrl_div_data omap4_fdif_fck_data __initconst = { 279 .max_div = 4, 280 .flags = CLK_DIVIDER_POWER_OF_TWO, 281 }; 282 283 static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = { 284 { 24, TI_CLK_DIVIDER, omap4_fdif_fck_parents, &omap4_fdif_fck_data }, 285 { 0 }, 286 }; 287 288 static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = { 289 { OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" }, 290 { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss_cm:clk:0008:24" }, 291 { 0 }, 292 }; 293 294 static const char * const omap4_dss_dss_clk_parents[] __initconst = { 295 "dpll_per_m5x2_ck", 296 NULL, 297 }; 298 299 static const char * const omap4_dss_48mhz_clk_parents[] __initconst = { 300 "func_48mc_fclk", 301 NULL, 302 }; 303 304 static const char * const omap4_dss_sys_clk_parents[] __initconst = { 305 "syc_clk_div_ck", 306 NULL, 307 }; 308 309 static const char * const omap4_dss_tv_clk_parents[] __initconst = { 310 "extalt_clkin_ck", 311 NULL, 312 }; 313 314 static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst = { 315 { 8, TI_CLK_GATE, omap4_dss_dss_clk_parents, NULL }, 316 { 9, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL }, 317 { 10, TI_CLK_GATE, omap4_dss_sys_clk_parents, NULL }, 318 { 11, TI_CLK_GATE, omap4_dss_tv_clk_parents, NULL }, 319 { 0 }, 320 }; 321 322 static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = { 323 { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3_dss_cm:clk:0000:8" }, 324 { 0 }, 325 }; 326 327 static const char * const omap4_sgx_clk_mux_parents[] __initconst = { 328 "dpll_core_m7x2_ck", 329 "dpll_per_m7x2_ck", 330 NULL, 331 }; 332 333 static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = { 334 { 24, TI_CLK_MUX, omap4_sgx_clk_mux_parents, NULL }, 335 { 0 }, 336 }; 337 338 static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = { 339 { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3_gfx_cm:clk:0000:24" }, 340 { 0 }, 341 }; 342 343 static const char * const omap4_hsmmc1_fclk_parents[] __initconst = { 344 "func_64m_fclk", 345 "func_96m_fclk", 346 NULL, 347 }; 348 349 static const struct omap_clkctrl_bit_data omap4_mmc1_bit_data[] __initconst = { 350 { 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL }, 351 { 0 }, 352 }; 353 354 static const struct omap_clkctrl_bit_data omap4_mmc2_bit_data[] __initconst = { 355 { 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL }, 356 { 0 }, 357 }; 358 359 static const char * const omap4_hsi_fck_parents[] __initconst = { 360 "dpll_per_m2x2_ck", 361 NULL, 362 }; 363 364 static const struct omap_clkctrl_div_data omap4_hsi_fck_data __initconst = { 365 .max_div = 4, 366 .flags = CLK_DIVIDER_POWER_OF_TWO, 367 }; 368 369 static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = { 370 { 24, TI_CLK_DIVIDER, omap4_hsi_fck_parents, &omap4_hsi_fck_data }, 371 { 0 }, 372 }; 373 374 static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = { 375 "l3_init_cm:clk:0038:24", 376 NULL, 377 }; 378 379 static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = { 380 "l3_init_cm:clk:0038:25", 381 NULL, 382 }; 383 384 static const char * const omap4_usb_host_hs_utmi_p3_clk_parents[] __initconst = { 385 "init_60m_fclk", 386 NULL, 387 }; 388 389 static const char * const omap4_usb_host_hs_hsic480m_p1_clk_parents[] __initconst = { 390 "dpll_usb_m2_ck", 391 NULL, 392 }; 393 394 static const char * const omap4_utmi_p1_gfclk_parents[] __initconst = { 395 "init_60m_fclk", 396 "xclk60mhsp1_ck", 397 NULL, 398 }; 399 400 static const char * const omap4_utmi_p2_gfclk_parents[] __initconst = { 401 "init_60m_fclk", 402 "xclk60mhsp2_ck", 403 NULL, 404 }; 405 406 static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initconst = { 407 { 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p1_clk_parents, NULL }, 408 { 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p2_clk_parents, NULL }, 409 { 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL }, 410 { 11, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL }, 411 { 12, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL }, 412 { 13, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL }, 413 { 14, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL }, 414 { 15, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL }, 415 { 24, TI_CLK_MUX, omap4_utmi_p1_gfclk_parents, NULL }, 416 { 25, TI_CLK_MUX, omap4_utmi_p2_gfclk_parents, NULL }, 417 { 0 }, 418 }; 419 420 static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = { 421 "l3_init_cm:clk:0040:24", 422 NULL, 423 }; 424 425 static const char * const omap4_otg_60m_gfclk_parents[] __initconst = { 426 "utmi_phy_clkout_ck", 427 "xclk60motg_ck", 428 NULL, 429 }; 430 431 static const struct omap_clkctrl_bit_data omap4_usb_otg_hs_bit_data[] __initconst = { 432 { 8, TI_CLK_GATE, omap4_usb_otg_hs_xclk_parents, NULL }, 433 { 24, TI_CLK_MUX, omap4_otg_60m_gfclk_parents, NULL }, 434 { 0 }, 435 }; 436 437 static const struct omap_clkctrl_bit_data omap4_usb_tll_hs_bit_data[] __initconst = { 438 { 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL }, 439 { 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL }, 440 { 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL }, 441 { 0 }, 442 }; 443 444 static const char * const omap4_ocp2scp_usb_phy_phy_48m_parents[] __initconst = { 445 "func_48m_fclk", 446 NULL, 447 }; 448 449 static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __initconst = { 450 { 8, TI_CLK_GATE, omap4_ocp2scp_usb_phy_phy_48m_parents, NULL }, 451 { 0 }, 452 }; 453 454 static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = { 455 { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0008:24" }, 456 { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0010:24" }, 457 { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:0018:24" }, 458 { OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" }, 459 { OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" }, 460 { OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" }, 461 { OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" }, 462 { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:00c0:8" }, 463 { 0 }, 464 }; 465 466 static const char * const omap4_cm2_dm10_mux_parents[] __initconst = { 467 "sys_clkin_ck", 468 "sys_32k_ck", 469 NULL, 470 }; 471 472 static const struct omap_clkctrl_bit_data omap4_timer10_bit_data[] __initconst = { 473 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL }, 474 { 0 }, 475 }; 476 477 static const struct omap_clkctrl_bit_data omap4_timer11_bit_data[] __initconst = { 478 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL }, 479 { 0 }, 480 }; 481 482 static const struct omap_clkctrl_bit_data omap4_timer2_bit_data[] __initconst = { 483 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL }, 484 { 0 }, 485 }; 486 487 static const struct omap_clkctrl_bit_data omap4_timer3_bit_data[] __initconst = { 488 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL }, 489 { 0 }, 490 }; 491 492 static const struct omap_clkctrl_bit_data omap4_timer4_bit_data[] __initconst = { 493 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL }, 494 { 0 }, 495 }; 496 497 static const struct omap_clkctrl_bit_data omap4_timer9_bit_data[] __initconst = { 498 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL }, 499 { 0 }, 500 }; 501 502 static const char * const omap4_gpio2_dbclk_parents[] __initconst = { 503 "sys_32k_ck", 504 NULL, 505 }; 506 507 static const struct omap_clkctrl_bit_data omap4_gpio2_bit_data[] __initconst = { 508 { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL }, 509 { 0 }, 510 }; 511 512 static const struct omap_clkctrl_bit_data omap4_gpio3_bit_data[] __initconst = { 513 { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL }, 514 { 0 }, 515 }; 516 517 static const struct omap_clkctrl_bit_data omap4_gpio4_bit_data[] __initconst = { 518 { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL }, 519 { 0 }, 520 }; 521 522 static const struct omap_clkctrl_bit_data omap4_gpio5_bit_data[] __initconst = { 523 { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL }, 524 { 0 }, 525 }; 526 527 static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = { 528 { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL }, 529 { 0 }, 530 }; 531 532 static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = { 533 "l4_per_cm:clk:00c0:26", 534 "pad_clks_ck", 535 NULL, 536 }; 537 538 static const char * const omap4_mcbsp4_sync_mux_ck_parents[] __initconst = { 539 "func_96m_fclk", 540 "per_abe_nc_fclk", 541 NULL, 542 }; 543 544 static const struct omap_clkctrl_bit_data omap4_mcbsp4_bit_data[] __initconst = { 545 { 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL }, 546 { 26, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL }, 547 { 0 }, 548 }; 549 550 static const char * const omap4_slimbus2_fclk_0_parents[] __initconst = { 551 "func_24mc_fclk", 552 NULL, 553 }; 554 555 static const char * const omap4_slimbus2_fclk_1_parents[] __initconst = { 556 "per_abe_24m_fclk", 557 NULL, 558 }; 559 560 static const char * const omap4_slimbus2_slimbus_clk_parents[] __initconst = { 561 "pad_slimbus_core_clks_ck", 562 NULL, 563 }; 564 565 static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst = { 566 { 8, TI_CLK_GATE, omap4_slimbus2_fclk_0_parents, NULL }, 567 { 9, TI_CLK_GATE, omap4_slimbus2_fclk_1_parents, NULL }, 568 { 10, TI_CLK_GATE, omap4_slimbus2_slimbus_clk_parents, NULL }, 569 { 0 }, 570 }; 571 572 static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = { 573 { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0008:24" }, 574 { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0010:24" }, 575 { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0018:24" }, 576 { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0020:24" }, 577 { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0028:24" }, 578 { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0030:24" }, 579 { OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" }, 580 { OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" }, 581 { OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" }, 582 { OMAP4_GPIO4_CLKCTRL, omap4_gpio4_bit_data, CLKF_HW_SUP, "l4_div_ck" }, 583 { OMAP4_GPIO5_CLKCTRL, omap4_gpio5_bit_data, CLKF_HW_SUP, "l4_div_ck" }, 584 { OMAP4_GPIO6_CLKCTRL, omap4_gpio6_bit_data, CLKF_HW_SUP, "l4_div_ck" }, 585 { OMAP4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" }, 586 { OMAP4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 587 { OMAP4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 588 { OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 589 { OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 590 { OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" }, 591 { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:00c0:24" }, 592 { OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 593 { OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 594 { OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 595 { OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 596 { OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 597 { OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 598 { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0118:8" }, 599 { OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 600 { OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 601 { OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 602 { OMAP4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 603 { OMAP4_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 604 { 0 }, 605 }; 606 607 static const struct 608 omap_clkctrl_reg_data omap4_l4_secure_clkctrl_regs[] __initconst = { 609 { OMAP4_AES1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" }, 610 { OMAP4_AES2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" }, 611 { OMAP4_DES3DES_CLKCTRL, NULL, CLKF_SW_SUP, "l4_div_ck" }, 612 { OMAP4_PKA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_div_ck" }, 613 { OMAP4_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_div_ck" }, 614 { OMAP4_SHA2MD5_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" }, 615 { OMAP4_CRYPTODMA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_div_ck" }, 616 { 0 }, 617 }; 618 619 static const struct omap_clkctrl_bit_data omap4_gpio1_bit_data[] __initconst = { 620 { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL }, 621 { 0 }, 622 }; 623 624 static const struct omap_clkctrl_bit_data omap4_timer1_bit_data[] __initconst = { 625 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL }, 626 { 0 }, 627 }; 628 629 static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initconst = { 630 { OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" }, 631 { OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 632 { OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" }, 633 { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0020:24" }, 634 { OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" }, 635 { OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 636 { 0 }, 637 }; 638 639 static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = { 640 "sys_clkin_ck", 641 "dpll_core_m6x2_ck", 642 "tie_low_clock_ck", 643 NULL, 644 }; 645 646 static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = { 647 "emu_sys_cm:clk:0000:22", 648 NULL, 649 }; 650 651 static const int omap4_trace_clk_div_div_ck_divs[] __initconst = { 652 0, 653 1, 654 2, 655 0, 656 4, 657 -1, 658 }; 659 660 static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __initconst = { 661 .dividers = omap4_trace_clk_div_div_ck_divs, 662 }; 663 664 static const char * const omap4_stm_clk_div_ck_parents[] __initconst = { 665 "emu_sys_cm:clk:0000:20", 666 NULL, 667 }; 668 669 static const struct omap_clkctrl_div_data omap4_stm_clk_div_ck_data __initconst = { 670 .max_div = 64, 671 .flags = CLK_DIVIDER_POWER_OF_TWO, 672 }; 673 674 static const struct omap_clkctrl_bit_data omap4_debugss_bit_data[] __initconst = { 675 { 20, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL }, 676 { 22, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL }, 677 { 24, TI_CLK_DIVIDER, omap4_trace_clk_div_div_ck_parents, &omap4_trace_clk_div_div_ck_data }, 678 { 27, TI_CLK_DIVIDER, omap4_stm_clk_div_ck_parents, &omap4_stm_clk_div_ck_data }, 679 { 0 }, 680 }; 681 682 static const struct omap_clkctrl_reg_data omap4_emu_sys_clkctrl_regs[] __initconst = { 683 { OMAP4_DEBUGSS_CLKCTRL, omap4_debugss_bit_data, 0, "trace_clk_div_ck" }, 684 { 0 }, 685 }; 686 687 const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = { 688 { 0x4a004320, omap4_mpuss_clkctrl_regs }, 689 { 0x4a004420, omap4_tesla_clkctrl_regs }, 690 { 0x4a004520, omap4_abe_clkctrl_regs }, 691 { 0x4a008620, omap4_l4_ao_clkctrl_regs }, 692 { 0x4a008720, omap4_l3_1_clkctrl_regs }, 693 { 0x4a008820, omap4_l3_2_clkctrl_regs }, 694 { 0x4a008920, omap4_ducati_clkctrl_regs }, 695 { 0x4a008a20, omap4_l3_dma_clkctrl_regs }, 696 { 0x4a008b20, omap4_l3_emif_clkctrl_regs }, 697 { 0x4a008c20, omap4_d2d_clkctrl_regs }, 698 { 0x4a008d20, omap4_l4_cfg_clkctrl_regs }, 699 { 0x4a008e20, omap4_l3_instr_clkctrl_regs }, 700 { 0x4a008f20, omap4_ivahd_clkctrl_regs }, 701 { 0x4a009020, omap4_iss_clkctrl_regs }, 702 { 0x4a009120, omap4_l3_dss_clkctrl_regs }, 703 { 0x4a009220, omap4_l3_gfx_clkctrl_regs }, 704 { 0x4a009320, omap4_l3_init_clkctrl_regs }, 705 { 0x4a009420, omap4_l4_per_clkctrl_regs }, 706 { 0x4a0095a0, omap4_l4_secure_clkctrl_regs }, 707 { 0x4a307820, omap4_l4_wkup_clkctrl_regs }, 708 { 0x4a307a20, omap4_emu_sys_clkctrl_regs }, 709 { 0 }, 710 }; 711 712 static struct ti_dt_clk omap44xx_clks[] = { 713 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 714 /* 715 * XXX: All the clock aliases below are only needed for legacy 716 * hwmod support. Once hwmod is removed, these can be removed 717 * also. 718 */ 719 DT_CLK(NULL, "aess_fclk", "abe_cm:0008:24"), 720 DT_CLK(NULL, "cm2_dm10_mux", "l4_per_cm:0008:24"), 721 DT_CLK(NULL, "cm2_dm11_mux", "l4_per_cm:0010:24"), 722 DT_CLK(NULL, "cm2_dm2_mux", "l4_per_cm:0018:24"), 723 DT_CLK(NULL, "cm2_dm3_mux", "l4_per_cm:0020:24"), 724 DT_CLK(NULL, "cm2_dm4_mux", "l4_per_cm:0028:24"), 725 DT_CLK(NULL, "cm2_dm9_mux", "l4_per_cm:0030:24"), 726 DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"), 727 DT_CLK(NULL, "dmt1_clk_mux", "l4_wkup_cm:0020:24"), 728 DT_CLK(NULL, "dss_48mhz_clk", "l3_dss_cm:0000:9"), 729 DT_CLK(NULL, "dss_dss_clk", "l3_dss_cm:0000:8"), 730 DT_CLK(NULL, "dss_sys_clk", "l3_dss_cm:0000:10"), 731 DT_CLK(NULL, "dss_tv_clk", "l3_dss_cm:0000:11"), 732 DT_CLK(NULL, "fdif_fck", "iss_cm:0008:24"), 733 DT_CLK(NULL, "func_dmic_abe_gfclk", "abe_cm:0018:24"), 734 DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe_cm:0020:24"), 735 DT_CLK(NULL, "func_mcbsp1_gfclk", "abe_cm:0028:24"), 736 DT_CLK(NULL, "func_mcbsp2_gfclk", "abe_cm:0030:24"), 737 DT_CLK(NULL, "func_mcbsp3_gfclk", "abe_cm:0038:24"), 738 DT_CLK(NULL, "gpio1_dbclk", "l4_wkup_cm:0018:8"), 739 DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0040:8"), 740 DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0048:8"), 741 DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0050:8"), 742 DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0058:8"), 743 DT_CLK(NULL, "gpio6_dbclk", "l4_per_cm:0060:8"), 744 DT_CLK(NULL, "hsi_fck", "l3_init_cm:0018:24"), 745 DT_CLK(NULL, "hsmmc1_fclk", "l3_init_cm:0008:24"), 746 DT_CLK(NULL, "hsmmc2_fclk", "l3_init_cm:0010:24"), 747 DT_CLK(NULL, "iss_ctrlclk", "iss_cm:0000:8"), 748 DT_CLK(NULL, "mcasp_sync_mux_ck", "abe_cm:0020:26"), 749 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"), 750 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"), 751 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"), 752 DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4_per_cm:00c0:26"), 753 DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3_init_cm:00c0:8"), 754 DT_CLK(NULL, "otg_60m_gfclk", "l3_init_cm:0040:24"), 755 DT_CLK(NULL, "per_mcbsp4_gfclk", "l4_per_cm:00c0:24"), 756 DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu_sys_cm:0000:20"), 757 DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu_sys_cm:0000:22"), 758 DT_CLK(NULL, "sgx_clk_mux", "l3_gfx_cm:0000:24"), 759 DT_CLK(NULL, "slimbus1_fclk_0", "abe_cm:0040:8"), 760 DT_CLK(NULL, "slimbus1_fclk_1", "abe_cm:0040:9"), 761 DT_CLK(NULL, "slimbus1_fclk_2", "abe_cm:0040:10"), 762 DT_CLK(NULL, "slimbus1_slimbus_clk", "abe_cm:0040:11"), 763 DT_CLK(NULL, "slimbus2_fclk_0", "l4_per_cm:0118:8"), 764 DT_CLK(NULL, "slimbus2_fclk_1", "l4_per_cm:0118:9"), 765 DT_CLK(NULL, "slimbus2_slimbus_clk", "l4_per_cm:0118:10"), 766 DT_CLK(NULL, "stm_clk_div_ck", "emu_sys_cm:0000:27"), 767 DT_CLK(NULL, "timer5_sync_mux", "abe_cm:0048:24"), 768 DT_CLK(NULL, "timer6_sync_mux", "abe_cm:0050:24"), 769 DT_CLK(NULL, "timer7_sync_mux", "abe_cm:0058:24"), 770 DT_CLK(NULL, "timer8_sync_mux", "abe_cm:0060:24"), 771 DT_CLK(NULL, "trace_clk_div_div_ck", "emu_sys_cm:0000:24"), 772 DT_CLK(NULL, "usb_host_hs_func48mclk", "l3_init_cm:0038:15"), 773 DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3_init_cm:0038:13"), 774 DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3_init_cm:0038:14"), 775 DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3_init_cm:0038:11"), 776 DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3_init_cm:0038:12"), 777 DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3_init_cm:0038:8"), 778 DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3_init_cm:0038:9"), 779 DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init_cm:0038:10"), 780 DT_CLK(NULL, "usb_otg_hs_xclk", "l3_init_cm:0040:8"), 781 DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3_init_cm:0048:8"), 782 DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3_init_cm:0048:9"), 783 DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3_init_cm:0048:10"), 784 DT_CLK(NULL, "utmi_p1_gfclk", "l3_init_cm:0038:24"), 785 DT_CLK(NULL, "utmi_p2_gfclk", "l3_init_cm:0038:25"), 786 { .node_name = NULL }, 787 }; 788 789 int __init omap4xxx_dt_clk_init(void) 790 { 791 int rc; 792 struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; 793 794 ti_dt_clocks_register(omap44xx_clks); 795 796 omap2_clk_disable_autoidle_all(); 797 798 ti_clk_add_aliases(); 799 800 /* 801 * Lock USB DPLL on OMAP4 devices so that the L3INIT power 802 * domain can transition to retention state when not in use. 803 */ 804 usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); 805 rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ); 806 if (rc) 807 pr_err("%s: failed to configure USB DPLL!\n", __func__); 808 809 /* 810 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power 811 * state when turning the ABE clock domain. Workaround this by 812 * locking the ABE DPLL on boot. 813 * Lock the ABE DPLL in any case to avoid issues with audio. 814 */ 815 abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck"); 816 sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); 817 rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); 818 abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); 819 if (!rc) 820 rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ); 821 if (rc) 822 pr_err("%s: failed to configure ABE DPLL!\n", __func__); 823 824 return 0; 825 } 826