1 /* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __TEGRA_CLK_H 18 #define __TEGRA_CLK_H 19 20 #include <linux/clk-provider.h> 21 #include <linux/clkdev.h> 22 23 /** 24 * struct tegra_clk_sync_source - external clock source from codec 25 * 26 * @hw: handle between common and hardware-specific interfaces 27 * @rate: input frequency from source 28 * @max_rate: max rate allowed 29 */ 30 struct tegra_clk_sync_source { 31 struct clk_hw hw; 32 unsigned long rate; 33 unsigned long max_rate; 34 }; 35 36 #define to_clk_sync_source(_hw) \ 37 container_of(_hw, struct tegra_clk_sync_source, hw) 38 39 extern const struct clk_ops tegra_clk_sync_source_ops; 40 extern int *periph_clk_enb_refcnt; 41 42 struct clk *tegra_clk_register_sync_source(const char *name, 43 unsigned long fixed_rate, unsigned long max_rate); 44 45 /** 46 * struct tegra_clk_frac_div - fractional divider clock 47 * 48 * @hw: handle between common and hardware-specific interfaces 49 * @reg: register containing divider 50 * @flags: hardware-specific flags 51 * @shift: shift to the divider bit field 52 * @width: width of the divider bit field 53 * @frac_width: width of the fractional bit field 54 * @lock: register lock 55 * 56 * Flags: 57 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. 58 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this 59 * flag indicates that this divider is for fixed rate PLL. 60 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when 61 * fraction bit is set. This flags indicates to calculate divider for which 62 * fracton bit will be zero. 63 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is 64 * set when divider value is not 0. This flags indicates that the divider 65 * is for UART module. 66 */ 67 struct tegra_clk_frac_div { 68 struct clk_hw hw; 69 void __iomem *reg; 70 u8 flags; 71 u8 shift; 72 u8 width; 73 u8 frac_width; 74 spinlock_t *lock; 75 }; 76 77 #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw) 78 79 #define TEGRA_DIVIDER_ROUND_UP BIT(0) 80 #define TEGRA_DIVIDER_FIXED BIT(1) 81 #define TEGRA_DIVIDER_INT BIT(2) 82 #define TEGRA_DIVIDER_UART BIT(3) 83 84 extern const struct clk_ops tegra_clk_frac_div_ops; 85 struct clk *tegra_clk_register_divider(const char *name, 86 const char *parent_name, void __iomem *reg, 87 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, 88 u8 frac_width, spinlock_t *lock); 89 struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, 90 void __iomem *reg, spinlock_t *lock); 91 92 /* 93 * Tegra PLL: 94 * 95 * In general, there are 3 requirements for each PLL 96 * that SW needs to be comply with. 97 * (1) Input frequency range (REF). 98 * (2) Comparison frequency range (CF). CF = REF/DIVM. 99 * (3) VCO frequency range (VCO). VCO = CF * DIVN. 100 * 101 * The final PLL output frequency (FO) = VCO >> DIVP. 102 */ 103 104 /** 105 * struct tegra_clk_pll_freq_table - PLL frequecy table 106 * 107 * @input_rate: input rate from source 108 * @output_rate: output rate from PLL for the input rate 109 * @n: feedback divider 110 * @m: input divider 111 * @p: post divider 112 * @cpcon: charge pump current 113 */ 114 struct tegra_clk_pll_freq_table { 115 unsigned long input_rate; 116 unsigned long output_rate; 117 u16 n; 118 u16 m; 119 u8 p; 120 u8 cpcon; 121 }; 122 123 /** 124 * struct pdiv_map - map post divider to hw value 125 * 126 * @pdiv: post divider 127 * @hw_val: value to be written to the PLL hw 128 */ 129 struct pdiv_map { 130 u8 pdiv; 131 u8 hw_val; 132 }; 133 134 /** 135 * struct div_nmp - offset and width of m,n and p fields 136 * 137 * @divn_shift: shift to the feedback divider bit field 138 * @divn_width: width of the feedback divider bit field 139 * @divm_shift: shift to the input divider bit field 140 * @divm_width: width of the input divider bit field 141 * @divp_shift: shift to the post divider bit field 142 * @divp_width: width of the post divider bit field 143 * @override_divn_shift: shift to the feedback divider bitfield in override reg 144 * @override_divm_shift: shift to the input divider bitfield in override reg 145 * @override_divp_shift: shift to the post divider bitfield in override reg 146 */ 147 struct div_nmp { 148 u8 divn_shift; 149 u8 divn_width; 150 u8 divm_shift; 151 u8 divm_width; 152 u8 divp_shift; 153 u8 divp_width; 154 u8 override_divn_shift; 155 u8 override_divm_shift; 156 u8 override_divp_shift; 157 }; 158 159 /** 160 * struct clk_pll_params - PLL parameters 161 * 162 * @input_min: Minimum input frequency 163 * @input_max: Maximum input frequency 164 * @cf_min: Minimum comparison frequency 165 * @cf_max: Maximum comparison frequency 166 * @vco_min: Minimum VCO frequency 167 * @vco_max: Maximum VCO frequency 168 * @base_reg: PLL base reg offset 169 * @misc_reg: PLL misc reg offset 170 * @lock_reg: PLL lock reg offset 171 * @lock_bit_idx: Bit index for PLL lock status 172 * @lock_enable_bit_idx: Bit index to enable PLL lock 173 * @lock_delay: Delay in us if PLL lock is not used 174 */ 175 struct tegra_clk_pll_params { 176 unsigned long input_min; 177 unsigned long input_max; 178 unsigned long cf_min; 179 unsigned long cf_max; 180 unsigned long vco_min; 181 unsigned long vco_max; 182 183 u32 base_reg; 184 u32 misc_reg; 185 u32 lock_reg; 186 u32 lock_mask; 187 u32 lock_enable_bit_idx; 188 u32 iddq_reg; 189 u32 iddq_bit_idx; 190 u32 aux_reg; 191 u32 dyn_ramp_reg; 192 u32 ext_misc_reg[3]; 193 u32 pmc_divnm_reg; 194 u32 pmc_divp_reg; 195 u32 flags; 196 int stepa_shift; 197 int stepb_shift; 198 int lock_delay; 199 int max_p; 200 struct pdiv_map *pdiv_tohw; 201 struct div_nmp *div_nmp; 202 struct tegra_clk_pll_freq_table *freq_table; 203 unsigned long fixed_rate; 204 }; 205 206 /** 207 * struct tegra_clk_pll - Tegra PLL clock 208 * 209 * @hw: handle between common and hardware-specifix interfaces 210 * @clk_base: address of CAR controller 211 * @pmc: address of PMC, required to read override bits 212 * @freq_table: array of frequencies supported by PLL 213 * @params: PLL parameters 214 * @flags: PLL flags 215 * @fixed_rate: PLL rate if it is fixed 216 * @lock: register lock 217 * 218 * Flags: 219 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for 220 * PLL locking. If not set it will use lock_delay value to wait. 221 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs 222 * to be programmed to change output frequency of the PLL. 223 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs 224 * to be programmed to change output frequency of the PLL. 225 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs 226 * to be programmed to change output frequency of the PLL. 227 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated 228 * that it is PLLU and invert post divider value. 229 * TEGRA_PLLM - PLLM has additional override settings in PMC. This 230 * flag indicates that it is PLLM and use override settings. 231 * TEGRA_PLL_FIXED - We are not supposed to change output frequency 232 * of some plls. 233 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling. 234 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the 235 * base register. 236 * TEGRA_PLL_BYPASS - PLL has bypass bit 237 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring 238 */ 239 struct tegra_clk_pll { 240 struct clk_hw hw; 241 void __iomem *clk_base; 242 void __iomem *pmc; 243 spinlock_t *lock; 244 struct tegra_clk_pll_params *params; 245 }; 246 247 #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) 248 249 #define TEGRA_PLL_USE_LOCK BIT(0) 250 #define TEGRA_PLL_HAS_CPCON BIT(1) 251 #define TEGRA_PLL_SET_LFCON BIT(2) 252 #define TEGRA_PLL_SET_DCCON BIT(3) 253 #define TEGRA_PLLU BIT(4) 254 #define TEGRA_PLLM BIT(5) 255 #define TEGRA_PLL_FIXED BIT(6) 256 #define TEGRA_PLLE_CONFIGURE BIT(7) 257 #define TEGRA_PLL_LOCK_MISC BIT(8) 258 #define TEGRA_PLL_BYPASS BIT(9) 259 #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) 260 261 extern const struct clk_ops tegra_clk_pll_ops; 262 extern const struct clk_ops tegra_clk_plle_ops; 263 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 264 void __iomem *clk_base, void __iomem *pmc, 265 unsigned long flags, struct tegra_clk_pll_params *pll_params, 266 spinlock_t *lock); 267 268 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 269 void __iomem *clk_base, void __iomem *pmc, 270 unsigned long flags, struct tegra_clk_pll_params *pll_params, 271 spinlock_t *lock); 272 273 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 274 void __iomem *clk_base, void __iomem *pmc, 275 unsigned long flags, 276 struct tegra_clk_pll_params *pll_params, 277 spinlock_t *lock); 278 279 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 280 void __iomem *clk_base, void __iomem *pmc, 281 unsigned long flags, 282 struct tegra_clk_pll_params *pll_params, 283 spinlock_t *lock); 284 285 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 286 void __iomem *clk_base, void __iomem *pmc, 287 unsigned long flags, 288 struct tegra_clk_pll_params *pll_params, 289 spinlock_t *lock); 290 291 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 292 void __iomem *clk_base, void __iomem *pmc, 293 unsigned long flags, 294 struct tegra_clk_pll_params *pll_params, 295 spinlock_t *lock, unsigned long parent_rate); 296 297 struct clk *tegra_clk_register_plle_tegra114(const char *name, 298 const char *parent_name, 299 void __iomem *clk_base, unsigned long flags, 300 struct tegra_clk_pll_params *pll_params, 301 spinlock_t *lock); 302 303 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, 304 void __iomem *clk_base, unsigned long flags, 305 struct tegra_clk_pll_params *pll_params, 306 spinlock_t *lock); 307 308 /** 309 * struct tegra_clk_pll_out - PLL divider down clock 310 * 311 * @hw: handle between common and hardware-specific interfaces 312 * @reg: register containing the PLL divider 313 * @enb_bit_idx: bit to enable/disable PLL divider 314 * @rst_bit_idx: bit to reset PLL divider 315 * @lock: register lock 316 * @flags: hardware-specific flags 317 */ 318 struct tegra_clk_pll_out { 319 struct clk_hw hw; 320 void __iomem *reg; 321 u8 enb_bit_idx; 322 u8 rst_bit_idx; 323 spinlock_t *lock; 324 u8 flags; 325 }; 326 327 #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) 328 329 extern const struct clk_ops tegra_clk_pll_out_ops; 330 struct clk *tegra_clk_register_pll_out(const char *name, 331 const char *parent_name, void __iomem *reg, u8 enb_bit_idx, 332 u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags, 333 spinlock_t *lock); 334 335 /** 336 * struct tegra_clk_periph_regs - Registers controlling peripheral clock 337 * 338 * @enb_reg: read the enable status 339 * @enb_set_reg: write 1 to enable clock 340 * @enb_clr_reg: write 1 to disable clock 341 * @rst_reg: read the reset status 342 * @rst_set_reg: write 1 to assert the reset of peripheral 343 * @rst_clr_reg: write 1 to deassert the reset of peripheral 344 */ 345 struct tegra_clk_periph_regs { 346 u32 enb_reg; 347 u32 enb_set_reg; 348 u32 enb_clr_reg; 349 u32 rst_reg; 350 u32 rst_set_reg; 351 u32 rst_clr_reg; 352 }; 353 354 /** 355 * struct tegra_clk_periph_gate - peripheral gate clock 356 * 357 * @magic: magic number to validate type 358 * @hw: handle between common and hardware-specific interfaces 359 * @clk_base: address of CAR controller 360 * @regs: Registers to control the peripheral 361 * @flags: hardware-specific flags 362 * @clk_num: Clock number 363 * @enable_refcnt: array to maintain reference count of the clock 364 * 365 * Flags: 366 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed 367 * for this module. 368 * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module 369 * after clock enable and driver for the module is responsible for 370 * doing reset. 371 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the 372 * bus to flush the write operation in apb bus. This flag indicates 373 * that this peripheral is in apb bus. 374 * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug 375 */ 376 struct tegra_clk_periph_gate { 377 u32 magic; 378 struct clk_hw hw; 379 void __iomem *clk_base; 380 u8 flags; 381 int clk_num; 382 int *enable_refcnt; 383 struct tegra_clk_periph_regs *regs; 384 }; 385 386 #define to_clk_periph_gate(_hw) \ 387 container_of(_hw, struct tegra_clk_periph_gate, hw) 388 389 #define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309 390 391 #define TEGRA_PERIPH_NO_RESET BIT(0) 392 #define TEGRA_PERIPH_MANUAL_RESET BIT(1) 393 #define TEGRA_PERIPH_ON_APB BIT(2) 394 #define TEGRA_PERIPH_WAR_1005168 BIT(3) 395 #define TEGRA_PERIPH_NO_DIV BIT(4) 396 #define TEGRA_PERIPH_NO_GATE BIT(5) 397 398 extern const struct clk_ops tegra_clk_periph_gate_ops; 399 struct clk *tegra_clk_register_periph_gate(const char *name, 400 const char *parent_name, u8 gate_flags, void __iomem *clk_base, 401 unsigned long flags, int clk_num, int *enable_refcnt); 402 403 /** 404 * struct clk-periph - peripheral clock 405 * 406 * @magic: magic number to validate type 407 * @hw: handle between common and hardware-specific interfaces 408 * @mux: mux clock 409 * @divider: divider clock 410 * @gate: gate clock 411 * @mux_ops: mux clock ops 412 * @div_ops: divider clock ops 413 * @gate_ops: gate clock ops 414 */ 415 struct tegra_clk_periph { 416 u32 magic; 417 struct clk_hw hw; 418 struct clk_mux mux; 419 struct tegra_clk_frac_div divider; 420 struct tegra_clk_periph_gate gate; 421 422 const struct clk_ops *mux_ops; 423 const struct clk_ops *div_ops; 424 const struct clk_ops *gate_ops; 425 }; 426 427 #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw) 428 429 #define TEGRA_CLK_PERIPH_MAGIC 0x18221223 430 431 extern const struct clk_ops tegra_clk_periph_ops; 432 struct clk *tegra_clk_register_periph(const char *name, 433 const char **parent_names, int num_parents, 434 struct tegra_clk_periph *periph, void __iomem *clk_base, 435 u32 offset, unsigned long flags); 436 struct clk *tegra_clk_register_periph_nodiv(const char *name, 437 const char **parent_names, int num_parents, 438 struct tegra_clk_periph *periph, void __iomem *clk_base, 439 u32 offset); 440 441 #define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \ 442 _div_shift, _div_width, _div_frac_width, \ 443 _div_flags, _clk_num,\ 444 _gate_flags, _table, _lock) \ 445 { \ 446 .mux = { \ 447 .flags = _mux_flags, \ 448 .shift = _mux_shift, \ 449 .mask = _mux_mask, \ 450 .table = _table, \ 451 .lock = _lock, \ 452 }, \ 453 .divider = { \ 454 .flags = _div_flags, \ 455 .shift = _div_shift, \ 456 .width = _div_width, \ 457 .frac_width = _div_frac_width, \ 458 .lock = _lock, \ 459 }, \ 460 .gate = { \ 461 .flags = _gate_flags, \ 462 .clk_num = _clk_num, \ 463 }, \ 464 .mux_ops = &clk_mux_ops, \ 465 .div_ops = &tegra_clk_frac_div_ops, \ 466 .gate_ops = &tegra_clk_periph_gate_ops, \ 467 } 468 469 struct tegra_periph_init_data { 470 const char *name; 471 int clk_id; 472 union { 473 const char **parent_names; 474 const char *parent_name; 475 } p; 476 int num_parents; 477 struct tegra_clk_periph periph; 478 u32 offset; 479 const char *con_id; 480 const char *dev_id; 481 unsigned long flags; 482 }; 483 484 #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 485 _mux_shift, _mux_mask, _mux_flags, _div_shift, \ 486 _div_width, _div_frac_width, _div_flags, \ 487 _clk_num, _gate_flags, _clk_id, _table, \ 488 _flags, _lock) \ 489 { \ 490 .name = _name, \ 491 .clk_id = _clk_id, \ 492 .p.parent_names = _parent_names, \ 493 .num_parents = ARRAY_SIZE(_parent_names), \ 494 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \ 495 _mux_flags, _div_shift, \ 496 _div_width, _div_frac_width, \ 497 _div_flags, _clk_num, \ 498 _gate_flags, _table, _lock), \ 499 .offset = _offset, \ 500 .con_id = _con_id, \ 501 .dev_id = _dev_id, \ 502 .flags = _flags \ 503 } 504 505 #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ 506 _mux_shift, _mux_width, _mux_flags, _div_shift, \ 507 _div_width, _div_frac_width, _div_flags, \ 508 _clk_num, _gate_flags, _clk_id) \ 509 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 510 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ 511 _div_shift, _div_width, _div_frac_width, _div_flags, \ 512 _clk_num, _gate_flags, _clk_id,\ 513 NULL, 0, NULL) 514 515 /** 516 * struct clk_super_mux - super clock 517 * 518 * @hw: handle between common and hardware-specific interfaces 519 * @reg: register controlling multiplexer 520 * @width: width of the multiplexer bit field 521 * @flags: hardware-specific flags 522 * @div2_index: bit controlling divide-by-2 523 * @pllx_index: PLLX index in the parent list 524 * @lock: register lock 525 * 526 * Flags: 527 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates 528 * that this is LP cluster clock. 529 */ 530 struct tegra_clk_super_mux { 531 struct clk_hw hw; 532 void __iomem *reg; 533 u8 width; 534 u8 flags; 535 u8 div2_index; 536 u8 pllx_index; 537 spinlock_t *lock; 538 }; 539 540 #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw) 541 542 #define TEGRA_DIVIDER_2 BIT(0) 543 544 extern const struct clk_ops tegra_clk_super_ops; 545 struct clk *tegra_clk_register_super_mux(const char *name, 546 const char **parent_names, u8 num_parents, 547 unsigned long flags, void __iomem *reg, u8 clk_super_flags, 548 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); 549 550 /** 551 * struct clk_init_table - clock initialization table 552 * @clk_id: clock id as mentioned in device tree bindings 553 * @parent_id: parent clock id as mentioned in device tree bindings 554 * @rate: rate to set 555 * @state: enable/disable 556 */ 557 struct tegra_clk_init_table { 558 unsigned int clk_id; 559 unsigned int parent_id; 560 unsigned long rate; 561 int state; 562 }; 563 564 /** 565 * struct clk_duplicate - duplicate clocks 566 * @clk_id: clock id as mentioned in device tree bindings 567 * @lookup: duplicate lookup entry for the clock 568 */ 569 struct tegra_clk_duplicate { 570 int clk_id; 571 struct clk_lookup lookup; 572 }; 573 574 #define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \ 575 { \ 576 .clk_id = _clk_id, \ 577 .lookup = { \ 578 .dev_id = _dev, \ 579 .con_id = _con, \ 580 }, \ 581 } 582 583 struct tegra_clk { 584 int dt_id; 585 bool present; 586 }; 587 588 struct tegra_devclk { 589 int dt_id; 590 char *dev_id; 591 char *con_id; 592 }; 593 594 void tegra_init_special_resets(unsigned int num, int (*assert)(unsigned long), 595 int (*deassert)(unsigned long)); 596 597 void tegra_init_from_table(struct tegra_clk_init_table *tbl, 598 struct clk *clks[], int clk_max); 599 600 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 601 struct clk *clks[], int clk_max); 602 603 struct tegra_clk_periph_regs *get_reg_bank(int clkid); 604 struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks); 605 606 struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk); 607 608 void tegra_add_of_provider(struct device_node *np); 609 void tegra_register_devclks(struct tegra_devclk *dev_clks, int num); 610 611 void tegra_audio_clk_init(void __iomem *clk_base, 612 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 613 struct tegra_clk_pll_params *pll_params); 614 615 void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base, 616 struct tegra_clk *tegra_clks, 617 struct tegra_clk_pll_params *pll_params); 618 619 void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks); 620 void tegra_fixed_clk_init(struct tegra_clk *tegra_clks); 621 int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, 622 unsigned long *input_freqs, unsigned int num, 623 unsigned int clk_m_div, unsigned long *osc_freq, 624 unsigned long *pll_ref_freq); 625 void tegra_super_clk_gen4_init(void __iomem *clk_base, 626 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 627 struct tegra_clk_pll_params *pll_params); 628 629 #ifdef CONFIG_TEGRA_CLK_EMC 630 struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np, 631 spinlock_t *lock); 632 #else 633 static inline struct clk *tegra_clk_register_emc(void __iomem *base, 634 struct device_node *np, 635 spinlock_t *lock) 636 { 637 return NULL; 638 } 639 #endif 640 641 void tegra114_clock_tune_cpu_trimmers_high(void); 642 void tegra114_clock_tune_cpu_trimmers_low(void); 643 void tegra114_clock_tune_cpu_trimmers_init(void); 644 void tegra114_clock_assert_dfll_dvco_reset(void); 645 void tegra114_clock_deassert_dfll_dvco_reset(void); 646 647 typedef void (*tegra_clk_apply_init_table_func)(void); 648 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 649 650 #endif /* TEGRA_CLK_H */ 651