1 /* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/clkdev.h> 18 #include <linux/clk.h> 19 #include <linux/clk-provider.h> 20 #include <linux/of.h> 21 #include <linux/clk/tegra.h> 22 #include <linux/reset-controller.h> 23 24 #include <soc/tegra/fuse.h> 25 26 #include "clk.h" 27 28 #define CLK_OUT_ENB_L 0x010 29 #define CLK_OUT_ENB_H 0x014 30 #define CLK_OUT_ENB_U 0x018 31 #define CLK_OUT_ENB_V 0x360 32 #define CLK_OUT_ENB_W 0x364 33 #define CLK_OUT_ENB_X 0x280 34 #define CLK_OUT_ENB_Y 0x298 35 #define CLK_OUT_ENB_SET_L 0x320 36 #define CLK_OUT_ENB_CLR_L 0x324 37 #define CLK_OUT_ENB_SET_H 0x328 38 #define CLK_OUT_ENB_CLR_H 0x32c 39 #define CLK_OUT_ENB_SET_U 0x330 40 #define CLK_OUT_ENB_CLR_U 0x334 41 #define CLK_OUT_ENB_SET_V 0x440 42 #define CLK_OUT_ENB_CLR_V 0x444 43 #define CLK_OUT_ENB_SET_W 0x448 44 #define CLK_OUT_ENB_CLR_W 0x44c 45 #define CLK_OUT_ENB_SET_X 0x284 46 #define CLK_OUT_ENB_CLR_X 0x288 47 #define CLK_OUT_ENB_SET_Y 0x29c 48 #define CLK_OUT_ENB_CLR_Y 0x2a0 49 50 #define RST_DEVICES_L 0x004 51 #define RST_DEVICES_H 0x008 52 #define RST_DEVICES_U 0x00C 53 #define RST_DFLL_DVCO 0x2F4 54 #define RST_DEVICES_V 0x358 55 #define RST_DEVICES_W 0x35C 56 #define RST_DEVICES_X 0x28C 57 #define RST_DEVICES_Y 0x2a4 58 #define RST_DEVICES_SET_L 0x300 59 #define RST_DEVICES_CLR_L 0x304 60 #define RST_DEVICES_SET_H 0x308 61 #define RST_DEVICES_CLR_H 0x30c 62 #define RST_DEVICES_SET_U 0x310 63 #define RST_DEVICES_CLR_U 0x314 64 #define RST_DEVICES_SET_V 0x430 65 #define RST_DEVICES_CLR_V 0x434 66 #define RST_DEVICES_SET_W 0x438 67 #define RST_DEVICES_CLR_W 0x43c 68 #define RST_DEVICES_SET_X 0x290 69 #define RST_DEVICES_CLR_X 0x294 70 #define RST_DEVICES_SET_Y 0x2a8 71 #define RST_DEVICES_CLR_Y 0x2ac 72 73 /* Global data of Tegra CPU CAR ops */ 74 static struct tegra_cpu_car_ops dummy_car_ops; 75 struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops; 76 77 int *periph_clk_enb_refcnt; 78 static int periph_banks; 79 static struct clk **clks; 80 static int clk_num; 81 static struct clk_onecell_data clk_data; 82 83 static struct tegra_clk_periph_regs periph_regs[] = { 84 [0] = { 85 .enb_reg = CLK_OUT_ENB_L, 86 .enb_set_reg = CLK_OUT_ENB_SET_L, 87 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 88 .rst_reg = RST_DEVICES_L, 89 .rst_set_reg = RST_DEVICES_SET_L, 90 .rst_clr_reg = RST_DEVICES_CLR_L, 91 }, 92 [1] = { 93 .enb_reg = CLK_OUT_ENB_H, 94 .enb_set_reg = CLK_OUT_ENB_SET_H, 95 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 96 .rst_reg = RST_DEVICES_H, 97 .rst_set_reg = RST_DEVICES_SET_H, 98 .rst_clr_reg = RST_DEVICES_CLR_H, 99 }, 100 [2] = { 101 .enb_reg = CLK_OUT_ENB_U, 102 .enb_set_reg = CLK_OUT_ENB_SET_U, 103 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 104 .rst_reg = RST_DEVICES_U, 105 .rst_set_reg = RST_DEVICES_SET_U, 106 .rst_clr_reg = RST_DEVICES_CLR_U, 107 }, 108 [3] = { 109 .enb_reg = CLK_OUT_ENB_V, 110 .enb_set_reg = CLK_OUT_ENB_SET_V, 111 .enb_clr_reg = CLK_OUT_ENB_CLR_V, 112 .rst_reg = RST_DEVICES_V, 113 .rst_set_reg = RST_DEVICES_SET_V, 114 .rst_clr_reg = RST_DEVICES_CLR_V, 115 }, 116 [4] = { 117 .enb_reg = CLK_OUT_ENB_W, 118 .enb_set_reg = CLK_OUT_ENB_SET_W, 119 .enb_clr_reg = CLK_OUT_ENB_CLR_W, 120 .rst_reg = RST_DEVICES_W, 121 .rst_set_reg = RST_DEVICES_SET_W, 122 .rst_clr_reg = RST_DEVICES_CLR_W, 123 }, 124 [5] = { 125 .enb_reg = CLK_OUT_ENB_X, 126 .enb_set_reg = CLK_OUT_ENB_SET_X, 127 .enb_clr_reg = CLK_OUT_ENB_CLR_X, 128 .rst_reg = RST_DEVICES_X, 129 .rst_set_reg = RST_DEVICES_SET_X, 130 .rst_clr_reg = RST_DEVICES_CLR_X, 131 }, 132 [6] = { 133 .enb_reg = CLK_OUT_ENB_Y, 134 .enb_set_reg = CLK_OUT_ENB_SET_Y, 135 .enb_clr_reg = CLK_OUT_ENB_CLR_Y, 136 .rst_reg = RST_DEVICES_Y, 137 .rst_set_reg = RST_DEVICES_SET_Y, 138 .rst_clr_reg = RST_DEVICES_CLR_Y, 139 }, 140 }; 141 142 static void __iomem *clk_base; 143 144 static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev, 145 unsigned long id) 146 { 147 /* 148 * If peripheral is on the APB bus then we must read the APB bus to 149 * flush the write operation in apb bus. This will avoid peripheral 150 * access after disabling clock. Since the reset driver has no 151 * knowledge of which reset IDs represent which devices, simply do 152 * this all the time. 153 */ 154 tegra_read_chipid(); 155 156 writel_relaxed(BIT(id % 32), 157 clk_base + periph_regs[id / 32].rst_set_reg); 158 159 return 0; 160 } 161 162 static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev, 163 unsigned long id) 164 { 165 writel_relaxed(BIT(id % 32), 166 clk_base + periph_regs[id / 32].rst_clr_reg); 167 168 return 0; 169 } 170 171 struct tegra_clk_periph_regs *get_reg_bank(int clkid) 172 { 173 int reg_bank = clkid / 32; 174 175 if (reg_bank < periph_banks) 176 return &periph_regs[reg_bank]; 177 else { 178 WARN_ON(1); 179 return NULL; 180 } 181 } 182 183 struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks) 184 { 185 clk_base = regs; 186 187 if (WARN_ON(banks > ARRAY_SIZE(periph_regs))) 188 return NULL; 189 190 periph_clk_enb_refcnt = kzalloc(32 * banks * 191 sizeof(*periph_clk_enb_refcnt), GFP_KERNEL); 192 if (!periph_clk_enb_refcnt) 193 return NULL; 194 195 periph_banks = banks; 196 197 clks = kzalloc(num * sizeof(struct clk *), GFP_KERNEL); 198 if (!clks) 199 kfree(periph_clk_enb_refcnt); 200 201 clk_num = num; 202 203 return clks; 204 } 205 206 void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 207 struct clk *clks[], int clk_max) 208 { 209 struct clk *clk; 210 211 for (; dup_list->clk_id < clk_max; dup_list++) { 212 clk = clks[dup_list->clk_id]; 213 dup_list->lookup.clk = clk; 214 clkdev_add(&dup_list->lookup); 215 } 216 } 217 218 void __init tegra_init_from_table(struct tegra_clk_init_table *tbl, 219 struct clk *clks[], int clk_max) 220 { 221 struct clk *clk; 222 223 for (; tbl->clk_id < clk_max; tbl++) { 224 clk = clks[tbl->clk_id]; 225 if (IS_ERR_OR_NULL(clk)) { 226 pr_err("%s: invalid entry %ld in clks array for id %d\n", 227 __func__, PTR_ERR(clk), tbl->clk_id); 228 WARN_ON(1); 229 230 continue; 231 } 232 233 if (tbl->parent_id < clk_max) { 234 struct clk *parent = clks[tbl->parent_id]; 235 if (clk_set_parent(clk, parent)) { 236 pr_err("%s: Failed to set parent %s of %s\n", 237 __func__, __clk_get_name(parent), 238 __clk_get_name(clk)); 239 WARN_ON(1); 240 } 241 } 242 243 if (tbl->rate) 244 if (clk_set_rate(clk, tbl->rate)) { 245 pr_err("%s: Failed to set rate %lu of %s\n", 246 __func__, tbl->rate, 247 __clk_get_name(clk)); 248 WARN_ON(1); 249 } 250 251 if (tbl->state) 252 if (clk_prepare_enable(clk)) { 253 pr_err("%s: Failed to enable %s\n", __func__, 254 __clk_get_name(clk)); 255 WARN_ON(1); 256 } 257 } 258 } 259 260 static struct reset_control_ops rst_ops = { 261 .assert = tegra_clk_rst_assert, 262 .deassert = tegra_clk_rst_deassert, 263 }; 264 265 static struct reset_controller_dev rst_ctlr = { 266 .ops = &rst_ops, 267 .owner = THIS_MODULE, 268 .of_reset_n_cells = 1, 269 }; 270 271 void __init tegra_add_of_provider(struct device_node *np) 272 { 273 int i; 274 275 for (i = 0; i < clk_num; i++) { 276 if (IS_ERR(clks[i])) { 277 pr_err 278 ("Tegra clk %d: register failed with %ld\n", 279 i, PTR_ERR(clks[i])); 280 } 281 if (!clks[i]) 282 clks[i] = ERR_PTR(-EINVAL); 283 } 284 285 clk_data.clks = clks; 286 clk_data.clk_num = clk_num; 287 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 288 289 rst_ctlr.of_node = np; 290 rst_ctlr.nr_resets = periph_banks * 32; 291 reset_controller_register(&rst_ctlr); 292 } 293 294 void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num) 295 { 296 int i; 297 298 for (i = 0; i < num; i++, dev_clks++) 299 clk_register_clkdev(clks[dev_clks->dt_id], dev_clks->con_id, 300 dev_clks->dev_id); 301 302 for (i = 0; i < clk_num; i++) { 303 if (!IS_ERR_OR_NULL(clks[i])) 304 clk_register_clkdev(clks[i], __clk_get_name(clks[i]), 305 "tegra-clk-debug"); 306 } 307 } 308 309 struct clk ** __init tegra_lookup_dt_id(int clk_id, 310 struct tegra_clk *tegra_clk) 311 { 312 if (tegra_clk[clk_id].present) 313 return &clks[tegra_clk[clk_id].dt_id]; 314 else 315 return NULL; 316 } 317 318 tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 319 320 static int __init tegra_clocks_apply_init_table(void) 321 { 322 if (!tegra_clk_apply_init_table) 323 return 0; 324 325 tegra_clk_apply_init_table(); 326 327 return 0; 328 } 329 arch_initcall(tegra_clocks_apply_init_table); 330