1 /* 2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/clk.h> 19 #include <linux/clk-provider.h> 20 #include <linux/clkdev.h> 21 #include <linux/of.h> 22 #include <linux/of_address.h> 23 #include <linux/delay.h> 24 #include <linux/export.h> 25 #include <linux/mutex.h> 26 #include <linux/clk/tegra.h> 27 #include <dt-bindings/clock/tegra210-car.h> 28 #include <dt-bindings/reset/tegra210-car.h> 29 #include <linux/iopoll.h> 30 #include <soc/tegra/pmc.h> 31 32 #include "clk.h" 33 #include "clk-id.h" 34 35 /* 36 * TEGRA210_CAR_BANK_COUNT: the number of peripheral clock register 37 * banks present in the Tegra210 CAR IP block. The banks are 38 * identified by single letters, e.g.: L, H, U, V, W, X, Y. See 39 * periph_regs[] in drivers/clk/tegra/clk.c 40 */ 41 #define TEGRA210_CAR_BANK_COUNT 7 42 43 #define CLK_SOURCE_CSITE 0x1d4 44 #define CLK_SOURCE_EMC 0x19c 45 #define CLK_SOURCE_SOR1 0x410 46 #define CLK_SOURCE_LA 0x1f8 47 48 #define PLLC_BASE 0x80 49 #define PLLC_OUT 0x84 50 #define PLLC_MISC0 0x88 51 #define PLLC_MISC1 0x8c 52 #define PLLC_MISC2 0x5d0 53 #define PLLC_MISC3 0x5d4 54 55 #define PLLC2_BASE 0x4e8 56 #define PLLC2_MISC0 0x4ec 57 #define PLLC2_MISC1 0x4f0 58 #define PLLC2_MISC2 0x4f4 59 #define PLLC2_MISC3 0x4f8 60 61 #define PLLC3_BASE 0x4fc 62 #define PLLC3_MISC0 0x500 63 #define PLLC3_MISC1 0x504 64 #define PLLC3_MISC2 0x508 65 #define PLLC3_MISC3 0x50c 66 67 #define PLLM_BASE 0x90 68 #define PLLM_MISC1 0x98 69 #define PLLM_MISC2 0x9c 70 #define PLLP_BASE 0xa0 71 #define PLLP_MISC0 0xac 72 #define PLLP_MISC1 0x680 73 #define PLLA_BASE 0xb0 74 #define PLLA_MISC0 0xbc 75 #define PLLA_MISC1 0xb8 76 #define PLLA_MISC2 0x5d8 77 #define PLLD_BASE 0xd0 78 #define PLLD_MISC0 0xdc 79 #define PLLD_MISC1 0xd8 80 #define PLLU_BASE 0xc0 81 #define PLLU_OUTA 0xc4 82 #define PLLU_MISC0 0xcc 83 #define PLLU_MISC1 0xc8 84 #define PLLX_BASE 0xe0 85 #define PLLX_MISC0 0xe4 86 #define PLLX_MISC1 0x510 87 #define PLLX_MISC2 0x514 88 #define PLLX_MISC3 0x518 89 #define PLLX_MISC4 0x5f0 90 #define PLLX_MISC5 0x5f4 91 #define PLLE_BASE 0xe8 92 #define PLLE_MISC0 0xec 93 #define PLLD2_BASE 0x4b8 94 #define PLLD2_MISC0 0x4bc 95 #define PLLD2_MISC1 0x570 96 #define PLLD2_MISC2 0x574 97 #define PLLD2_MISC3 0x578 98 #define PLLE_AUX 0x48c 99 #define PLLRE_BASE 0x4c4 100 #define PLLRE_MISC0 0x4c8 101 #define PLLRE_OUT1 0x4cc 102 #define PLLDP_BASE 0x590 103 #define PLLDP_MISC 0x594 104 105 #define PLLC4_BASE 0x5a4 106 #define PLLC4_MISC0 0x5a8 107 #define PLLC4_OUT 0x5e4 108 #define PLLMB_BASE 0x5e8 109 #define PLLMB_MISC1 0x5ec 110 #define PLLA1_BASE 0x6a4 111 #define PLLA1_MISC0 0x6a8 112 #define PLLA1_MISC1 0x6ac 113 #define PLLA1_MISC2 0x6b0 114 #define PLLA1_MISC3 0x6b4 115 116 #define PLLU_IDDQ_BIT 31 117 #define PLLCX_IDDQ_BIT 27 118 #define PLLRE_IDDQ_BIT 24 119 #define PLLA_IDDQ_BIT 25 120 #define PLLD_IDDQ_BIT 20 121 #define PLLSS_IDDQ_BIT 18 122 #define PLLM_IDDQ_BIT 5 123 #define PLLMB_IDDQ_BIT 17 124 #define PLLXP_IDDQ_BIT 3 125 126 #define PLLCX_RESET_BIT 30 127 128 #define PLL_BASE_LOCK BIT(27) 129 #define PLLCX_BASE_LOCK BIT(26) 130 #define PLLE_MISC_LOCK BIT(11) 131 #define PLLRE_MISC_LOCK BIT(27) 132 133 #define PLL_MISC_LOCK_ENABLE 18 134 #define PLLC_MISC_LOCK_ENABLE 24 135 #define PLLDU_MISC_LOCK_ENABLE 22 136 #define PLLU_MISC_LOCK_ENABLE 29 137 #define PLLE_MISC_LOCK_ENABLE 9 138 #define PLLRE_MISC_LOCK_ENABLE 30 139 #define PLLSS_MISC_LOCK_ENABLE 30 140 #define PLLP_MISC_LOCK_ENABLE 18 141 #define PLLM_MISC_LOCK_ENABLE 4 142 #define PLLMB_MISC_LOCK_ENABLE 16 143 #define PLLA_MISC_LOCK_ENABLE 28 144 #define PLLU_MISC_LOCK_ENABLE 29 145 #define PLLD_MISC_LOCK_ENABLE 18 146 147 #define PLLA_SDM_DIN_MASK 0xffff 148 #define PLLA_SDM_EN_MASK BIT(26) 149 150 #define PLLD_SDM_EN_MASK BIT(16) 151 152 #define PLLD2_SDM_EN_MASK BIT(31) 153 #define PLLD2_SSC_EN_MASK 0 154 155 #define PLLDP_SS_CFG 0x598 156 #define PLLDP_SDM_EN_MASK BIT(31) 157 #define PLLDP_SSC_EN_MASK BIT(30) 158 #define PLLDP_SS_CTRL1 0x59c 159 #define PLLDP_SS_CTRL2 0x5a0 160 161 #define PMC_PLLM_WB0_OVERRIDE 0x1dc 162 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 163 164 #define UTMIP_PLL_CFG2 0x488 165 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6) 166 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 167 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 168 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1) 169 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 170 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3) 171 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 172 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5) 173 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24) 174 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25) 175 176 #define UTMIP_PLL_CFG1 0x484 177 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) 178 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 179 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) 180 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 181 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) 182 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 183 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 184 185 #define SATA_PLL_CFG0 0x490 186 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 187 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) 188 #define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL BIT(4) 189 #define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE BIT(5) 190 #define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE BIT(6) 191 #define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE BIT(7) 192 193 #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) 194 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) 195 196 #define XUSBIO_PLL_CFG0 0x51c 197 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 198 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) 199 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) 200 #define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) 201 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) 202 203 #define UTMIPLL_HW_PWRDN_CFG0 0x52c 204 #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31) 205 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) 206 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 207 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(7) 208 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 209 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) 210 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) 211 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 212 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) 213 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) 214 215 #define PLLU_HW_PWRDN_CFG0 0x530 216 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28) 217 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 218 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7) 219 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 220 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 221 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0) 222 223 #define XUSB_PLL_CFG0 0x534 224 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff 225 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14) 226 227 #define SPARE_REG0 0x55c 228 #define CLK_M_DIVISOR_SHIFT 2 229 #define CLK_M_DIVISOR_MASK 0x3 230 231 #define RST_DFLL_DVCO 0x2f4 232 #define DVFS_DFLL_RESET_SHIFT 0 233 234 #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8 235 #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac 236 237 #define LVL2_CLK_GATE_OVRA 0xf8 238 #define LVL2_CLK_GATE_OVRC 0x3a0 239 #define LVL2_CLK_GATE_OVRD 0x3a4 240 #define LVL2_CLK_GATE_OVRE 0x554 241 242 /* I2S registers to handle during APE MBIST WAR */ 243 #define TEGRA210_I2S_BASE 0x1000 244 #define TEGRA210_I2S_SIZE 0x100 245 #define TEGRA210_I2S_CTRLS 5 246 #define TEGRA210_I2S_CG 0x88 247 #define TEGRA210_I2S_CTRL 0xa0 248 249 /* DISPA registers to handle during MBIST WAR */ 250 #define DC_CMD_DISPLAY_COMMAND 0xc8 251 #define DC_COM_DSC_TOP_CTL 0xcf8 252 253 /* VIC register to handle during MBIST WAR */ 254 #define NV_PVIC_THI_SLCG_OVERRIDE_LOW 0x8c 255 256 /* APE, DISPA and VIC base addesses needed for MBIST WAR */ 257 #define TEGRA210_AHUB_BASE 0x702d0000 258 #define TEGRA210_DISPA_BASE 0x54200000 259 #define TEGRA210_VIC_BASE 0x54340000 260 261 /* 262 * SDM fractional divisor is 16-bit 2's complement signed number within 263 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned 264 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to 265 * indicate that SDM is disabled. 266 * 267 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13 268 */ 269 #define PLL_SDM_COEFF BIT(13) 270 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU)) 271 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat) 272 /* This macro returns ndiv effective scaled to SDM range */ 273 #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \ 274 (PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0)) 275 276 /* Tegra CPU clock and reset control regs */ 277 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 278 279 #ifdef CONFIG_PM_SLEEP 280 static struct cpu_clk_suspend_context { 281 u32 clk_csite_src; 282 } tegra210_cpu_clk_sctx; 283 #endif 284 285 struct tegra210_domain_mbist_war { 286 void (*handle_lvl2_ovr)(struct tegra210_domain_mbist_war *mbist); 287 const u32 lvl2_offset; 288 const u32 lvl2_mask; 289 const unsigned int num_clks; 290 const unsigned int *clk_init_data; 291 struct clk_bulk_data *clks; 292 }; 293 294 static struct clk **clks; 295 296 static void __iomem *clk_base; 297 static void __iomem *pmc_base; 298 static void __iomem *ahub_base; 299 static void __iomem *dispa_base; 300 static void __iomem *vic_base; 301 302 static unsigned long osc_freq; 303 static unsigned long pll_ref_freq; 304 305 static DEFINE_SPINLOCK(pll_d_lock); 306 static DEFINE_SPINLOCK(pll_e_lock); 307 static DEFINE_SPINLOCK(pll_re_lock); 308 static DEFINE_SPINLOCK(pll_u_lock); 309 static DEFINE_SPINLOCK(sor1_lock); 310 static DEFINE_SPINLOCK(emc_lock); 311 static DEFINE_MUTEX(lvl2_ovr_lock); 312 313 /* possible OSC frequencies in Hz */ 314 static unsigned long tegra210_input_freq[] = { 315 [5] = 38400000, 316 [8] = 12000000, 317 }; 318 319 static const char *mux_pllmcp_clkm[] = { 320 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb", 321 "pll_p", 322 }; 323 #define mux_pllmcp_clkm_idx NULL 324 325 #define PLL_ENABLE (1 << 30) 326 327 #define PLLCX_MISC1_IDDQ (1 << 27) 328 #define PLLCX_MISC0_RESET (1 << 30) 329 330 #define PLLCX_MISC0_DEFAULT_VALUE 0x40080000 331 #define PLLCX_MISC0_WRITE_MASK 0x400ffffb 332 #define PLLCX_MISC1_DEFAULT_VALUE 0x08000000 333 #define PLLCX_MISC1_WRITE_MASK 0x08003cff 334 #define PLLCX_MISC2_DEFAULT_VALUE 0x1f720f05 335 #define PLLCX_MISC2_WRITE_MASK 0xffffff17 336 #define PLLCX_MISC3_DEFAULT_VALUE 0x000000c4 337 #define PLLCX_MISC3_WRITE_MASK 0x00ffffff 338 339 /* PLLA */ 340 #define PLLA_BASE_IDDQ (1 << 25) 341 #define PLLA_BASE_LOCK (1 << 27) 342 343 #define PLLA_MISC0_LOCK_ENABLE (1 << 28) 344 #define PLLA_MISC0_LOCK_OVERRIDE (1 << 27) 345 346 #define PLLA_MISC2_EN_SDM (1 << 26) 347 #define PLLA_MISC2_EN_DYNRAMP (1 << 25) 348 349 #define PLLA_MISC0_DEFAULT_VALUE 0x12000020 350 #define PLLA_MISC0_WRITE_MASK 0x7fffffff 351 #define PLLA_MISC2_DEFAULT_VALUE 0x0 352 #define PLLA_MISC2_WRITE_MASK 0x06ffffff 353 354 /* PLLD */ 355 #define PLLD_BASE_CSI_CLKSOURCE (1 << 23) 356 357 #define PLLD_MISC0_EN_SDM (1 << 16) 358 #define PLLD_MISC0_LOCK_OVERRIDE (1 << 17) 359 #define PLLD_MISC0_LOCK_ENABLE (1 << 18) 360 #define PLLD_MISC0_IDDQ (1 << 20) 361 #define PLLD_MISC0_DSI_CLKENABLE (1 << 21) 362 363 #define PLLD_MISC0_DEFAULT_VALUE 0x00140000 364 #define PLLD_MISC0_WRITE_MASK 0x3ff7ffff 365 #define PLLD_MISC1_DEFAULT_VALUE 0x20 366 #define PLLD_MISC1_WRITE_MASK 0x00ffffff 367 368 /* PLLD2 and PLLDP and PLLC4 */ 369 #define PLLDSS_BASE_LOCK (1 << 27) 370 #define PLLDSS_BASE_LOCK_OVERRIDE (1 << 24) 371 #define PLLDSS_BASE_IDDQ (1 << 18) 372 #define PLLDSS_BASE_REF_SEL_SHIFT 25 373 #define PLLDSS_BASE_REF_SEL_MASK (0x3 << PLLDSS_BASE_REF_SEL_SHIFT) 374 375 #define PLLDSS_MISC0_LOCK_ENABLE (1 << 30) 376 377 #define PLLDSS_MISC1_CFG_EN_SDM (1 << 31) 378 #define PLLDSS_MISC1_CFG_EN_SSC (1 << 30) 379 380 #define PLLD2_MISC0_DEFAULT_VALUE 0x40000020 381 #define PLLD2_MISC1_CFG_DEFAULT_VALUE 0x10000000 382 #define PLLD2_MISC2_CTRL1_DEFAULT_VALUE 0x0 383 #define PLLD2_MISC3_CTRL2_DEFAULT_VALUE 0x0 384 385 #define PLLDP_MISC0_DEFAULT_VALUE 0x40000020 386 #define PLLDP_MISC1_CFG_DEFAULT_VALUE 0xc0000000 387 #define PLLDP_MISC2_CTRL1_DEFAULT_VALUE 0xf400f0da 388 #define PLLDP_MISC3_CTRL2_DEFAULT_VALUE 0x2004f400 389 390 #define PLLDSS_MISC0_WRITE_MASK 0x47ffffff 391 #define PLLDSS_MISC1_CFG_WRITE_MASK 0xf8000000 392 #define PLLDSS_MISC2_CTRL1_WRITE_MASK 0xffffffff 393 #define PLLDSS_MISC3_CTRL2_WRITE_MASK 0xffffffff 394 395 #define PLLC4_MISC0_DEFAULT_VALUE 0x40000000 396 397 /* PLLRE */ 398 #define PLLRE_MISC0_LOCK_ENABLE (1 << 30) 399 #define PLLRE_MISC0_LOCK_OVERRIDE (1 << 29) 400 #define PLLRE_MISC0_LOCK (1 << 27) 401 #define PLLRE_MISC0_IDDQ (1 << 24) 402 403 #define PLLRE_BASE_DEFAULT_VALUE 0x0 404 #define PLLRE_MISC0_DEFAULT_VALUE 0x41000000 405 406 #define PLLRE_BASE_DEFAULT_MASK 0x1c000000 407 #define PLLRE_MISC0_WRITE_MASK 0x67ffffff 408 409 /* PLLX */ 410 #define PLLX_USE_DYN_RAMP 1 411 #define PLLX_BASE_LOCK (1 << 27) 412 413 #define PLLX_MISC0_FO_G_DISABLE (0x1 << 28) 414 #define PLLX_MISC0_LOCK_ENABLE (0x1 << 18) 415 416 #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24 417 #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT) 418 #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16 419 #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT) 420 #define PLLX_MISC2_NDIV_NEW_SHIFT 8 421 #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT) 422 #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4) 423 #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2) 424 #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0) 425 426 #define PLLX_MISC3_IDDQ (0x1 << 3) 427 428 #define PLLX_MISC0_DEFAULT_VALUE PLLX_MISC0_LOCK_ENABLE 429 #define PLLX_MISC0_WRITE_MASK 0x10c40000 430 #define PLLX_MISC1_DEFAULT_VALUE 0x20 431 #define PLLX_MISC1_WRITE_MASK 0x00ffffff 432 #define PLLX_MISC2_DEFAULT_VALUE 0x0 433 #define PLLX_MISC2_WRITE_MASK 0xffffff11 434 #define PLLX_MISC3_DEFAULT_VALUE PLLX_MISC3_IDDQ 435 #define PLLX_MISC3_WRITE_MASK 0x01ff0f0f 436 #define PLLX_MISC4_DEFAULT_VALUE 0x0 437 #define PLLX_MISC4_WRITE_MASK 0x8000ffff 438 #define PLLX_MISC5_DEFAULT_VALUE 0x0 439 #define PLLX_MISC5_WRITE_MASK 0x0000ffff 440 441 #define PLLX_HW_CTRL_CFG 0x548 442 #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0) 443 444 /* PLLMB */ 445 #define PLLMB_BASE_LOCK (1 << 27) 446 447 #define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18) 448 #define PLLMB_MISC1_IDDQ (1 << 17) 449 #define PLLMB_MISC1_LOCK_ENABLE (1 << 16) 450 451 #define PLLMB_MISC1_DEFAULT_VALUE 0x00030000 452 #define PLLMB_MISC1_WRITE_MASK 0x0007ffff 453 454 /* PLLP */ 455 #define PLLP_BASE_OVERRIDE (1 << 28) 456 #define PLLP_BASE_LOCK (1 << 27) 457 458 #define PLLP_MISC0_LOCK_ENABLE (1 << 18) 459 #define PLLP_MISC0_LOCK_OVERRIDE (1 << 17) 460 #define PLLP_MISC0_IDDQ (1 << 3) 461 462 #define PLLP_MISC1_HSIO_EN_SHIFT 29 463 #define PLLP_MISC1_HSIO_EN (1 << PLLP_MISC1_HSIO_EN_SHIFT) 464 #define PLLP_MISC1_XUSB_EN_SHIFT 28 465 #define PLLP_MISC1_XUSB_EN (1 << PLLP_MISC1_XUSB_EN_SHIFT) 466 467 #define PLLP_MISC0_DEFAULT_VALUE 0x00040008 468 #define PLLP_MISC1_DEFAULT_VALUE 0x0 469 470 #define PLLP_MISC0_WRITE_MASK 0xdc6000f 471 #define PLLP_MISC1_WRITE_MASK 0x70ffffff 472 473 /* PLLU */ 474 #define PLLU_BASE_LOCK (1 << 27) 475 #define PLLU_BASE_OVERRIDE (1 << 24) 476 #define PLLU_BASE_CLKENABLE_USB (1 << 21) 477 #define PLLU_BASE_CLKENABLE_HSIC (1 << 22) 478 #define PLLU_BASE_CLKENABLE_ICUSB (1 << 23) 479 #define PLLU_BASE_CLKENABLE_48M (1 << 25) 480 #define PLLU_BASE_CLKENABLE_ALL (PLLU_BASE_CLKENABLE_USB |\ 481 PLLU_BASE_CLKENABLE_HSIC |\ 482 PLLU_BASE_CLKENABLE_ICUSB |\ 483 PLLU_BASE_CLKENABLE_48M) 484 485 #define PLLU_MISC0_IDDQ (1 << 31) 486 #define PLLU_MISC0_LOCK_ENABLE (1 << 29) 487 #define PLLU_MISC1_LOCK_OVERRIDE (1 << 0) 488 489 #define PLLU_MISC0_DEFAULT_VALUE 0xa0000000 490 #define PLLU_MISC1_DEFAULT_VALUE 0x0 491 492 #define PLLU_MISC0_WRITE_MASK 0xbfffffff 493 #define PLLU_MISC1_WRITE_MASK 0x00000007 494 495 void tegra210_xusb_pll_hw_control_enable(void) 496 { 497 u32 val; 498 499 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); 500 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | 501 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); 502 val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | 503 XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; 504 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); 505 } 506 EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_control_enable); 507 508 void tegra210_xusb_pll_hw_sequence_start(void) 509 { 510 u32 val; 511 512 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); 513 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 514 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); 515 } 516 EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_sequence_start); 517 518 void tegra210_sata_pll_hw_control_enable(void) 519 { 520 u32 val; 521 522 val = readl_relaxed(clk_base + SATA_PLL_CFG0); 523 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; 524 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET | 525 SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ; 526 writel_relaxed(val, clk_base + SATA_PLL_CFG0); 527 } 528 EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_control_enable); 529 530 void tegra210_sata_pll_hw_sequence_start(void) 531 { 532 u32 val; 533 534 val = readl_relaxed(clk_base + SATA_PLL_CFG0); 535 val |= SATA_PLL_CFG0_SEQ_ENABLE; 536 writel_relaxed(val, clk_base + SATA_PLL_CFG0); 537 } 538 EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start); 539 540 void tegra210_set_sata_pll_seq_sw(bool state) 541 { 542 u32 val; 543 544 val = readl_relaxed(clk_base + SATA_PLL_CFG0); 545 if (state) { 546 val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL; 547 val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE; 548 val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; 549 val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE; 550 } else { 551 val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL; 552 val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE; 553 val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; 554 val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE; 555 } 556 writel_relaxed(val, clk_base + SATA_PLL_CFG0); 557 } 558 EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw); 559 560 static void tegra210_generic_mbist_war(struct tegra210_domain_mbist_war *mbist) 561 { 562 u32 val; 563 564 val = readl_relaxed(clk_base + mbist->lvl2_offset); 565 writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset); 566 fence_udelay(1, clk_base); 567 writel_relaxed(val, clk_base + mbist->lvl2_offset); 568 fence_udelay(1, clk_base); 569 } 570 571 static void tegra210_venc_mbist_war(struct tegra210_domain_mbist_war *mbist) 572 { 573 u32 csi_src, ovra, ovre; 574 unsigned long flags = 0; 575 576 spin_lock_irqsave(&pll_d_lock, flags); 577 578 csi_src = readl_relaxed(clk_base + PLLD_BASE); 579 writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE); 580 fence_udelay(1, clk_base); 581 582 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA); 583 writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA); 584 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); 585 writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE); 586 fence_udelay(1, clk_base); 587 588 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA); 589 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); 590 writel_relaxed(csi_src, clk_base + PLLD_BASE); 591 fence_udelay(1, clk_base); 592 593 spin_unlock_irqrestore(&pll_d_lock, flags); 594 } 595 596 static void tegra210_disp_mbist_war(struct tegra210_domain_mbist_war *mbist) 597 { 598 u32 ovra, dsc_top_ctrl; 599 600 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA); 601 writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA); 602 fence_udelay(1, clk_base); 603 604 dsc_top_ctrl = readl_relaxed(dispa_base + DC_COM_DSC_TOP_CTL); 605 writel_relaxed(dsc_top_ctrl | BIT(2), dispa_base + DC_COM_DSC_TOP_CTL); 606 readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND); 607 writel_relaxed(dsc_top_ctrl, dispa_base + DC_COM_DSC_TOP_CTL); 608 readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND); 609 610 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA); 611 fence_udelay(1, clk_base); 612 } 613 614 static void tegra210_vic_mbist_war(struct tegra210_domain_mbist_war *mbist) 615 { 616 u32 ovre, val; 617 618 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); 619 writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE); 620 fence_udelay(1, clk_base); 621 622 val = readl_relaxed(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); 623 writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24), 624 vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); 625 fence_udelay(1, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); 626 627 writel_relaxed(val, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); 628 readl(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); 629 630 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); 631 fence_udelay(1, clk_base); 632 } 633 634 static void tegra210_ape_mbist_war(struct tegra210_domain_mbist_war *mbist) 635 { 636 void __iomem *i2s_base; 637 unsigned int i; 638 u32 ovrc, ovre; 639 640 ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC); 641 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); 642 writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC); 643 writel_relaxed(ovre | BIT(10) | BIT(11), 644 clk_base + LVL2_CLK_GATE_OVRE); 645 fence_udelay(1, clk_base); 646 647 i2s_base = ahub_base + TEGRA210_I2S_BASE; 648 649 for (i = 0; i < TEGRA210_I2S_CTRLS; i++) { 650 u32 i2s_ctrl; 651 652 i2s_ctrl = readl_relaxed(i2s_base + TEGRA210_I2S_CTRL); 653 writel_relaxed(i2s_ctrl | BIT(10), 654 i2s_base + TEGRA210_I2S_CTRL); 655 writel_relaxed(0, i2s_base + TEGRA210_I2S_CG); 656 readl(i2s_base + TEGRA210_I2S_CG); 657 writel_relaxed(1, i2s_base + TEGRA210_I2S_CG); 658 writel_relaxed(i2s_ctrl, i2s_base + TEGRA210_I2S_CTRL); 659 readl(i2s_base + TEGRA210_I2S_CTRL); 660 661 i2s_base += TEGRA210_I2S_SIZE; 662 } 663 664 writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC); 665 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); 666 fence_udelay(1, clk_base); 667 } 668 669 static inline void _pll_misc_chk_default(void __iomem *base, 670 struct tegra_clk_pll_params *params, 671 u8 misc_num, u32 default_val, u32 mask) 672 { 673 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]); 674 675 boot_val &= mask; 676 default_val &= mask; 677 if (boot_val != default_val) { 678 pr_warn("boot misc%d 0x%x: expected 0x%x\n", 679 misc_num, boot_val, default_val); 680 pr_warn(" (comparison mask = 0x%x)\n", mask); 681 params->defaults_set = false; 682 } 683 } 684 685 /* 686 * PLLCX: PLLC, PLLC2, PLLC3, PLLA1 687 * Hybrid PLLs with dynamic ramp. Dynamic ramp is allowed for any transition 688 * that changes NDIV only, while PLL is already locked. 689 */ 690 static void pllcx_check_defaults(struct tegra_clk_pll_params *params) 691 { 692 u32 default_val; 693 694 default_val = PLLCX_MISC0_DEFAULT_VALUE & (~PLLCX_MISC0_RESET); 695 _pll_misc_chk_default(clk_base, params, 0, default_val, 696 PLLCX_MISC0_WRITE_MASK); 697 698 default_val = PLLCX_MISC1_DEFAULT_VALUE & (~PLLCX_MISC1_IDDQ); 699 _pll_misc_chk_default(clk_base, params, 1, default_val, 700 PLLCX_MISC1_WRITE_MASK); 701 702 default_val = PLLCX_MISC2_DEFAULT_VALUE; 703 _pll_misc_chk_default(clk_base, params, 2, default_val, 704 PLLCX_MISC2_WRITE_MASK); 705 706 default_val = PLLCX_MISC3_DEFAULT_VALUE; 707 _pll_misc_chk_default(clk_base, params, 3, default_val, 708 PLLCX_MISC3_WRITE_MASK); 709 } 710 711 static void tegra210_pllcx_set_defaults(const char *name, 712 struct tegra_clk_pll *pllcx) 713 { 714 pllcx->params->defaults_set = true; 715 716 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) { 717 /* PLL is ON: only check if defaults already set */ 718 pllcx_check_defaults(pllcx->params); 719 if (!pllcx->params->defaults_set) 720 pr_warn("%s already enabled. Postponing set full defaults\n", 721 name); 722 return; 723 } 724 725 /* Defaults assert PLL reset, and set IDDQ */ 726 writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE, 727 clk_base + pllcx->params->ext_misc_reg[0]); 728 writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE, 729 clk_base + pllcx->params->ext_misc_reg[1]); 730 writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE, 731 clk_base + pllcx->params->ext_misc_reg[2]); 732 writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE, 733 clk_base + pllcx->params->ext_misc_reg[3]); 734 udelay(1); 735 } 736 737 static void _pllc_set_defaults(struct tegra_clk_pll *pllcx) 738 { 739 tegra210_pllcx_set_defaults("PLL_C", pllcx); 740 } 741 742 static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx) 743 { 744 tegra210_pllcx_set_defaults("PLL_C2", pllcx); 745 } 746 747 static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx) 748 { 749 tegra210_pllcx_set_defaults("PLL_C3", pllcx); 750 } 751 752 static void _plla1_set_defaults(struct tegra_clk_pll *pllcx) 753 { 754 tegra210_pllcx_set_defaults("PLL_A1", pllcx); 755 } 756 757 /* 758 * PLLA 759 * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used. 760 * Fractional SDM is allowed to provide exact audio rates. 761 */ 762 static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla) 763 { 764 u32 mask; 765 u32 val = readl_relaxed(clk_base + plla->params->base_reg); 766 767 plla->params->defaults_set = true; 768 769 if (val & PLL_ENABLE) { 770 /* 771 * PLL is ON: check if defaults already set, then set those 772 * that can be updated in flight. 773 */ 774 if (val & PLLA_BASE_IDDQ) { 775 pr_warn("PLL_A boot enabled with IDDQ set\n"); 776 plla->params->defaults_set = false; 777 } 778 779 pr_warn("PLL_A already enabled. Postponing set full defaults\n"); 780 781 val = PLLA_MISC0_DEFAULT_VALUE; /* ignore lock enable */ 782 mask = PLLA_MISC0_LOCK_ENABLE | PLLA_MISC0_LOCK_OVERRIDE; 783 _pll_misc_chk_default(clk_base, plla->params, 0, val, 784 ~mask & PLLA_MISC0_WRITE_MASK); 785 786 val = PLLA_MISC2_DEFAULT_VALUE; /* ignore all but control bit */ 787 _pll_misc_chk_default(clk_base, plla->params, 2, val, 788 PLLA_MISC2_EN_DYNRAMP); 789 790 /* Enable lock detect */ 791 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]); 792 val &= ~mask; 793 val |= PLLA_MISC0_DEFAULT_VALUE & mask; 794 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]); 795 udelay(1); 796 797 return; 798 } 799 800 /* set IDDQ, enable lock detect, disable dynamic ramp and SDM */ 801 val |= PLLA_BASE_IDDQ; 802 writel_relaxed(val, clk_base + plla->params->base_reg); 803 writel_relaxed(PLLA_MISC0_DEFAULT_VALUE, 804 clk_base + plla->params->ext_misc_reg[0]); 805 writel_relaxed(PLLA_MISC2_DEFAULT_VALUE, 806 clk_base + plla->params->ext_misc_reg[2]); 807 udelay(1); 808 } 809 810 /* 811 * PLLD 812 * PLL with fractional SDM. 813 */ 814 static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld) 815 { 816 u32 val; 817 u32 mask = 0xffff; 818 819 plld->params->defaults_set = true; 820 821 if (readl_relaxed(clk_base + plld->params->base_reg) & 822 PLL_ENABLE) { 823 824 /* 825 * PLL is ON: check if defaults already set, then set those 826 * that can be updated in flight. 827 */ 828 val = PLLD_MISC1_DEFAULT_VALUE; 829 _pll_misc_chk_default(clk_base, plld->params, 1, 830 val, PLLD_MISC1_WRITE_MASK); 831 832 /* ignore lock, DSI and SDM controls, make sure IDDQ not set */ 833 val = PLLD_MISC0_DEFAULT_VALUE & (~PLLD_MISC0_IDDQ); 834 mask |= PLLD_MISC0_DSI_CLKENABLE | PLLD_MISC0_LOCK_ENABLE | 835 PLLD_MISC0_LOCK_OVERRIDE | PLLD_MISC0_EN_SDM; 836 _pll_misc_chk_default(clk_base, plld->params, 0, val, 837 ~mask & PLLD_MISC0_WRITE_MASK); 838 839 if (!plld->params->defaults_set) 840 pr_warn("PLL_D already enabled. Postponing set full defaults\n"); 841 842 /* Enable lock detect */ 843 mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE; 844 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); 845 val &= ~mask; 846 val |= PLLD_MISC0_DEFAULT_VALUE & mask; 847 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); 848 udelay(1); 849 850 return; 851 } 852 853 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); 854 val &= PLLD_MISC0_DSI_CLKENABLE; 855 val |= PLLD_MISC0_DEFAULT_VALUE; 856 /* set IDDQ, enable lock detect, disable SDM */ 857 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); 858 writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base + 859 plld->params->ext_misc_reg[1]); 860 udelay(1); 861 } 862 863 /* 864 * PLLD2, PLLDP 865 * PLL with fractional SDM and Spread Spectrum (SDM is a must if SSC is used). 866 */ 867 static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss, 868 u32 misc0_val, u32 misc1_val, u32 misc2_val, u32 misc3_val) 869 { 870 u32 default_val; 871 u32 val = readl_relaxed(clk_base + plldss->params->base_reg); 872 873 plldss->params->defaults_set = true; 874 875 if (val & PLL_ENABLE) { 876 877 /* 878 * PLL is ON: check if defaults already set, then set those 879 * that can be updated in flight. 880 */ 881 if (val & PLLDSS_BASE_IDDQ) { 882 pr_warn("plldss boot enabled with IDDQ set\n"); 883 plldss->params->defaults_set = false; 884 } 885 886 /* ignore lock enable */ 887 default_val = misc0_val; 888 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val, 889 PLLDSS_MISC0_WRITE_MASK & 890 (~PLLDSS_MISC0_LOCK_ENABLE)); 891 892 /* 893 * If SSC is used, check all settings, otherwise just confirm 894 * that SSC is not used on boot as well. Do nothing when using 895 * this function for PLLC4 that has only MISC0. 896 */ 897 if (plldss->params->ssc_ctrl_en_mask) { 898 default_val = misc1_val; 899 _pll_misc_chk_default(clk_base, plldss->params, 1, 900 default_val, PLLDSS_MISC1_CFG_WRITE_MASK); 901 default_val = misc2_val; 902 _pll_misc_chk_default(clk_base, plldss->params, 2, 903 default_val, PLLDSS_MISC2_CTRL1_WRITE_MASK); 904 default_val = misc3_val; 905 _pll_misc_chk_default(clk_base, plldss->params, 3, 906 default_val, PLLDSS_MISC3_CTRL2_WRITE_MASK); 907 } else if (plldss->params->ext_misc_reg[1]) { 908 default_val = misc1_val; 909 _pll_misc_chk_default(clk_base, plldss->params, 1, 910 default_val, PLLDSS_MISC1_CFG_WRITE_MASK & 911 (~PLLDSS_MISC1_CFG_EN_SDM)); 912 } 913 914 if (!plldss->params->defaults_set) 915 pr_warn("%s already enabled. Postponing set full defaults\n", 916 pll_name); 917 918 /* Enable lock detect */ 919 if (val & PLLDSS_BASE_LOCK_OVERRIDE) { 920 val &= ~PLLDSS_BASE_LOCK_OVERRIDE; 921 writel_relaxed(val, clk_base + 922 plldss->params->base_reg); 923 } 924 925 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]); 926 val &= ~PLLDSS_MISC0_LOCK_ENABLE; 927 val |= misc0_val & PLLDSS_MISC0_LOCK_ENABLE; 928 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]); 929 udelay(1); 930 931 return; 932 } 933 934 /* set IDDQ, enable lock detect, configure SDM/SSC */ 935 val |= PLLDSS_BASE_IDDQ; 936 val &= ~PLLDSS_BASE_LOCK_OVERRIDE; 937 writel_relaxed(val, clk_base + plldss->params->base_reg); 938 939 /* When using this function for PLLC4 exit here */ 940 if (!plldss->params->ext_misc_reg[1]) { 941 writel_relaxed(misc0_val, clk_base + 942 plldss->params->ext_misc_reg[0]); 943 udelay(1); 944 return; 945 } 946 947 writel_relaxed(misc0_val, clk_base + 948 plldss->params->ext_misc_reg[0]); 949 /* if SSC used set by 1st enable */ 950 writel_relaxed(misc1_val & (~PLLDSS_MISC1_CFG_EN_SSC), 951 clk_base + plldss->params->ext_misc_reg[1]); 952 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]); 953 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]); 954 udelay(1); 955 } 956 957 static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2) 958 { 959 plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE, 960 PLLD2_MISC1_CFG_DEFAULT_VALUE, 961 PLLD2_MISC2_CTRL1_DEFAULT_VALUE, 962 PLLD2_MISC3_CTRL2_DEFAULT_VALUE); 963 } 964 965 static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp) 966 { 967 plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE, 968 PLLDP_MISC1_CFG_DEFAULT_VALUE, 969 PLLDP_MISC2_CTRL1_DEFAULT_VALUE, 970 PLLDP_MISC3_CTRL2_DEFAULT_VALUE); 971 } 972 973 /* 974 * PLLC4 975 * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support. 976 * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers. 977 */ 978 static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4) 979 { 980 plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0); 981 } 982 983 /* 984 * PLLRE 985 * VCO is exposed to the clock tree directly along with post-divider output 986 */ 987 static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre) 988 { 989 u32 mask; 990 u32 val = readl_relaxed(clk_base + pllre->params->base_reg); 991 992 pllre->params->defaults_set = true; 993 994 if (val & PLL_ENABLE) { 995 pr_warn("PLL_RE already enabled. Postponing set full defaults\n"); 996 997 /* 998 * PLL is ON: check if defaults already set, then set those 999 * that can be updated in flight. 1000 */ 1001 val &= PLLRE_BASE_DEFAULT_MASK; 1002 if (val != PLLRE_BASE_DEFAULT_VALUE) { 1003 pr_warn("pllre boot base 0x%x : expected 0x%x\n", 1004 val, PLLRE_BASE_DEFAULT_VALUE); 1005 pr_warn("(comparison mask = 0x%x)\n", 1006 PLLRE_BASE_DEFAULT_MASK); 1007 pllre->params->defaults_set = false; 1008 } 1009 1010 /* Ignore lock enable */ 1011 val = PLLRE_MISC0_DEFAULT_VALUE & (~PLLRE_MISC0_IDDQ); 1012 mask = PLLRE_MISC0_LOCK_ENABLE | PLLRE_MISC0_LOCK_OVERRIDE; 1013 _pll_misc_chk_default(clk_base, pllre->params, 0, val, 1014 ~mask & PLLRE_MISC0_WRITE_MASK); 1015 1016 /* Enable lock detect */ 1017 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]); 1018 val &= ~mask; 1019 val |= PLLRE_MISC0_DEFAULT_VALUE & mask; 1020 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]); 1021 udelay(1); 1022 1023 return; 1024 } 1025 1026 /* set IDDQ, enable lock detect */ 1027 val &= ~PLLRE_BASE_DEFAULT_MASK; 1028 val |= PLLRE_BASE_DEFAULT_VALUE & PLLRE_BASE_DEFAULT_MASK; 1029 writel_relaxed(val, clk_base + pllre->params->base_reg); 1030 writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE, 1031 clk_base + pllre->params->ext_misc_reg[0]); 1032 udelay(1); 1033 } 1034 1035 static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b) 1036 { 1037 unsigned long input_rate; 1038 1039 /* cf rate */ 1040 if (!IS_ERR_OR_NULL(hw->clk)) 1041 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); 1042 else 1043 input_rate = 38400000; 1044 1045 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); 1046 1047 switch (input_rate) { 1048 case 12000000: 1049 case 12800000: 1050 case 13000000: 1051 *step_a = 0x2B; 1052 *step_b = 0x0B; 1053 return; 1054 case 19200000: 1055 *step_a = 0x12; 1056 *step_b = 0x08; 1057 return; 1058 case 38400000: 1059 *step_a = 0x04; 1060 *step_b = 0x05; 1061 return; 1062 default: 1063 pr_err("%s: Unexpected reference rate %lu\n", 1064 __func__, input_rate); 1065 BUG(); 1066 } 1067 } 1068 1069 static void pllx_check_defaults(struct tegra_clk_pll *pll) 1070 { 1071 u32 default_val; 1072 1073 default_val = PLLX_MISC0_DEFAULT_VALUE; 1074 /* ignore lock enable */ 1075 _pll_misc_chk_default(clk_base, pll->params, 0, default_val, 1076 PLLX_MISC0_WRITE_MASK & (~PLLX_MISC0_LOCK_ENABLE)); 1077 1078 default_val = PLLX_MISC1_DEFAULT_VALUE; 1079 _pll_misc_chk_default(clk_base, pll->params, 1, default_val, 1080 PLLX_MISC1_WRITE_MASK); 1081 1082 /* ignore all but control bit */ 1083 default_val = PLLX_MISC2_DEFAULT_VALUE; 1084 _pll_misc_chk_default(clk_base, pll->params, 2, 1085 default_val, PLLX_MISC2_EN_DYNRAMP); 1086 1087 default_val = PLLX_MISC3_DEFAULT_VALUE & (~PLLX_MISC3_IDDQ); 1088 _pll_misc_chk_default(clk_base, pll->params, 3, default_val, 1089 PLLX_MISC3_WRITE_MASK); 1090 1091 default_val = PLLX_MISC4_DEFAULT_VALUE; 1092 _pll_misc_chk_default(clk_base, pll->params, 4, default_val, 1093 PLLX_MISC4_WRITE_MASK); 1094 1095 default_val = PLLX_MISC5_DEFAULT_VALUE; 1096 _pll_misc_chk_default(clk_base, pll->params, 5, default_val, 1097 PLLX_MISC5_WRITE_MASK); 1098 } 1099 1100 static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx) 1101 { 1102 u32 val; 1103 u32 step_a, step_b; 1104 1105 pllx->params->defaults_set = true; 1106 1107 /* Get ready dyn ramp state machine settings */ 1108 pllx_get_dyn_steps(&pllx->hw, &step_a, &step_b); 1109 val = PLLX_MISC2_DEFAULT_VALUE & (~PLLX_MISC2_DYNRAMP_STEPA_MASK) & 1110 (~PLLX_MISC2_DYNRAMP_STEPB_MASK); 1111 val |= step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT; 1112 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT; 1113 1114 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { 1115 1116 /* 1117 * PLL is ON: check if defaults already set, then set those 1118 * that can be updated in flight. 1119 */ 1120 pllx_check_defaults(pllx); 1121 1122 if (!pllx->params->defaults_set) 1123 pr_warn("PLL_X already enabled. Postponing set full defaults\n"); 1124 /* Configure dyn ramp, disable lock override */ 1125 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); 1126 1127 /* Enable lock detect */ 1128 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]); 1129 val &= ~PLLX_MISC0_LOCK_ENABLE; 1130 val |= PLLX_MISC0_DEFAULT_VALUE & PLLX_MISC0_LOCK_ENABLE; 1131 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]); 1132 udelay(1); 1133 1134 return; 1135 } 1136 1137 /* Enable lock detect and CPU output */ 1138 writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base + 1139 pllx->params->ext_misc_reg[0]); 1140 1141 /* Setup */ 1142 writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base + 1143 pllx->params->ext_misc_reg[1]); 1144 1145 /* Configure dyn ramp state machine, disable lock override */ 1146 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); 1147 1148 /* Set IDDQ */ 1149 writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base + 1150 pllx->params->ext_misc_reg[3]); 1151 1152 /* Disable SDM */ 1153 writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base + 1154 pllx->params->ext_misc_reg[4]); 1155 writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base + 1156 pllx->params->ext_misc_reg[5]); 1157 udelay(1); 1158 } 1159 1160 /* PLLMB */ 1161 static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb) 1162 { 1163 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg); 1164 1165 pllmb->params->defaults_set = true; 1166 1167 if (val & PLL_ENABLE) { 1168 1169 /* 1170 * PLL is ON: check if defaults already set, then set those 1171 * that can be updated in flight. 1172 */ 1173 val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ); 1174 mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE; 1175 _pll_misc_chk_default(clk_base, pllmb->params, 0, val, 1176 ~mask & PLLMB_MISC1_WRITE_MASK); 1177 1178 if (!pllmb->params->defaults_set) 1179 pr_warn("PLL_MB already enabled. Postponing set full defaults\n"); 1180 /* Enable lock detect */ 1181 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); 1182 val &= ~mask; 1183 val |= PLLMB_MISC1_DEFAULT_VALUE & mask; 1184 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]); 1185 udelay(1); 1186 1187 return; 1188 } 1189 1190 /* set IDDQ, enable lock detect */ 1191 writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE, 1192 clk_base + pllmb->params->ext_misc_reg[0]); 1193 udelay(1); 1194 } 1195 1196 /* 1197 * PLLP 1198 * VCO is exposed to the clock tree directly along with post-divider output. 1199 * Both VCO and post-divider output rates are fixed at 408MHz and 204MHz, 1200 * respectively. 1201 */ 1202 static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled) 1203 { 1204 u32 val, mask; 1205 1206 /* Ignore lock enable (will be set), make sure not in IDDQ if enabled */ 1207 val = PLLP_MISC0_DEFAULT_VALUE & (~PLLP_MISC0_IDDQ); 1208 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE; 1209 if (!enabled) 1210 mask |= PLLP_MISC0_IDDQ; 1211 _pll_misc_chk_default(clk_base, pll->params, 0, val, 1212 ~mask & PLLP_MISC0_WRITE_MASK); 1213 1214 /* Ignore branch controls */ 1215 val = PLLP_MISC1_DEFAULT_VALUE; 1216 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN; 1217 _pll_misc_chk_default(clk_base, pll->params, 1, val, 1218 ~mask & PLLP_MISC1_WRITE_MASK); 1219 } 1220 1221 static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp) 1222 { 1223 u32 mask; 1224 u32 val = readl_relaxed(clk_base + pllp->params->base_reg); 1225 1226 pllp->params->defaults_set = true; 1227 1228 if (val & PLL_ENABLE) { 1229 1230 /* 1231 * PLL is ON: check if defaults already set, then set those 1232 * that can be updated in flight. 1233 */ 1234 pllp_check_defaults(pllp, true); 1235 if (!pllp->params->defaults_set) 1236 pr_warn("PLL_P already enabled. Postponing set full defaults\n"); 1237 1238 /* Enable lock detect */ 1239 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); 1240 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE; 1241 val &= ~mask; 1242 val |= PLLP_MISC0_DEFAULT_VALUE & mask; 1243 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]); 1244 udelay(1); 1245 1246 return; 1247 } 1248 1249 /* set IDDQ, enable lock detect */ 1250 writel_relaxed(PLLP_MISC0_DEFAULT_VALUE, 1251 clk_base + pllp->params->ext_misc_reg[0]); 1252 1253 /* Preserve branch control */ 1254 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]); 1255 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN; 1256 val &= mask; 1257 val |= ~mask & PLLP_MISC1_DEFAULT_VALUE; 1258 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]); 1259 udelay(1); 1260 } 1261 1262 /* 1263 * PLLU 1264 * VCO is exposed to the clock tree directly along with post-divider output. 1265 * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz, 1266 * respectively. 1267 */ 1268 static void pllu_check_defaults(struct tegra_clk_pll_params *params, 1269 bool hw_control) 1270 { 1271 u32 val, mask; 1272 1273 /* Ignore lock enable (will be set) and IDDQ if under h/w control */ 1274 val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ); 1275 mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0); 1276 _pll_misc_chk_default(clk_base, params, 0, val, 1277 ~mask & PLLU_MISC0_WRITE_MASK); 1278 1279 val = PLLU_MISC1_DEFAULT_VALUE; 1280 mask = PLLU_MISC1_LOCK_OVERRIDE; 1281 _pll_misc_chk_default(clk_base, params, 1, val, 1282 ~mask & PLLU_MISC1_WRITE_MASK); 1283 } 1284 1285 static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu) 1286 { 1287 u32 val = readl_relaxed(clk_base + pllu->base_reg); 1288 1289 pllu->defaults_set = true; 1290 1291 if (val & PLL_ENABLE) { 1292 1293 /* 1294 * PLL is ON: check if defaults already set, then set those 1295 * that can be updated in flight. 1296 */ 1297 pllu_check_defaults(pllu, false); 1298 if (!pllu->defaults_set) 1299 pr_warn("PLL_U already enabled. Postponing set full defaults\n"); 1300 1301 /* Enable lock detect */ 1302 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]); 1303 val &= ~PLLU_MISC0_LOCK_ENABLE; 1304 val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE; 1305 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]); 1306 1307 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]); 1308 val &= ~PLLU_MISC1_LOCK_OVERRIDE; 1309 val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE; 1310 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]); 1311 udelay(1); 1312 1313 return; 1314 } 1315 1316 /* set IDDQ, enable lock detect */ 1317 writel_relaxed(PLLU_MISC0_DEFAULT_VALUE, 1318 clk_base + pllu->ext_misc_reg[0]); 1319 writel_relaxed(PLLU_MISC1_DEFAULT_VALUE, 1320 clk_base + pllu->ext_misc_reg[1]); 1321 udelay(1); 1322 } 1323 1324 #define mask(w) ((1 << (w)) - 1) 1325 #define divm_mask(p) mask(p->params->div_nmp->divm_width) 1326 #define divn_mask(p) mask(p->params->div_nmp->divn_width) 1327 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ 1328 mask(p->params->div_nmp->divp_width)) 1329 1330 #define divm_shift(p) ((p)->params->div_nmp->divm_shift) 1331 #define divn_shift(p) ((p)->params->div_nmp->divn_shift) 1332 #define divp_shift(p) ((p)->params->div_nmp->divp_shift) 1333 1334 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p)) 1335 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p)) 1336 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p)) 1337 1338 #define PLL_LOCKDET_DELAY 2 /* Lock detection safety delays */ 1339 static int tegra210_wait_for_mask(struct tegra_clk_pll *pll, 1340 u32 reg, u32 mask) 1341 { 1342 int i; 1343 u32 val = 0; 1344 1345 for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) { 1346 udelay(PLL_LOCKDET_DELAY); 1347 val = readl_relaxed(clk_base + reg); 1348 if ((val & mask) == mask) { 1349 udelay(PLL_LOCKDET_DELAY); 1350 return 0; 1351 } 1352 } 1353 return -ETIMEDOUT; 1354 } 1355 1356 static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll *pllx, 1357 struct tegra_clk_pll_freq_table *cfg) 1358 { 1359 u32 val, base, ndiv_new_mask; 1360 1361 ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift) 1362 << PLLX_MISC2_NDIV_NEW_SHIFT; 1363 1364 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); 1365 val &= (~ndiv_new_mask); 1366 val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT; 1367 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); 1368 udelay(1); 1369 1370 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); 1371 val |= PLLX_MISC2_EN_DYNRAMP; 1372 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); 1373 udelay(1); 1374 1375 tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2], 1376 PLLX_MISC2_DYNRAMP_DONE); 1377 1378 base = readl_relaxed(clk_base + pllx->params->base_reg) & 1379 (~divn_mask_shifted(pllx)); 1380 base |= cfg->n << pllx->params->div_nmp->divn_shift; 1381 writel_relaxed(base, clk_base + pllx->params->base_reg); 1382 udelay(1); 1383 1384 val &= ~PLLX_MISC2_EN_DYNRAMP; 1385 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); 1386 udelay(1); 1387 1388 pr_debug("%s: dynamic ramp to m = %u n = %u p = %u, Fout = %lu kHz\n", 1389 __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p, 1390 cfg->input_rate / cfg->m * cfg->n / 1391 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000); 1392 1393 return 0; 1394 } 1395 1396 /* 1397 * Common configuration for PLLs with fixed input divider policy: 1398 * - always set fixed M-value based on the reference rate 1399 * - always set P-value value 1:1 for output rates above VCO minimum, and 1400 * choose minimum necessary P-value for output rates below VCO maximum 1401 * - calculate N-value based on selected M and P 1402 * - calculate SDM_DIN fractional part 1403 */ 1404 static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw, 1405 struct tegra_clk_pll_freq_table *cfg, 1406 unsigned long rate, unsigned long input_rate) 1407 { 1408 struct tegra_clk_pll *pll = to_clk_pll(hw); 1409 struct tegra_clk_pll_params *params = pll->params; 1410 int p; 1411 unsigned long cf, p_rate; 1412 u32 pdiv; 1413 1414 if (!rate) 1415 return -EINVAL; 1416 1417 if (!(params->flags & TEGRA_PLL_VCO_OUT)) { 1418 p = DIV_ROUND_UP(params->vco_min, rate); 1419 p = params->round_p_to_pdiv(p, &pdiv); 1420 } else { 1421 p = rate >= params->vco_min ? 1 : -EINVAL; 1422 } 1423 1424 if (p < 0) 1425 return -EINVAL; 1426 1427 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate); 1428 cfg->p = p; 1429 1430 /* Store P as HW value, as that is what is expected */ 1431 cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p); 1432 1433 p_rate = rate * p; 1434 if (p_rate > params->vco_max) 1435 p_rate = params->vco_max; 1436 cf = input_rate / cfg->m; 1437 cfg->n = p_rate / cf; 1438 1439 cfg->sdm_data = 0; 1440 cfg->output_rate = input_rate; 1441 if (params->sdm_ctrl_reg) { 1442 unsigned long rem = p_rate - cf * cfg->n; 1443 /* If ssc is enabled SDM enabled as well, even for integer n */ 1444 if (rem || params->ssc_ctrl_reg) { 1445 u64 s = rem * PLL_SDM_COEFF; 1446 1447 do_div(s, cf); 1448 s -= PLL_SDM_COEFF / 2; 1449 cfg->sdm_data = sdin_din_to_data(s); 1450 } 1451 cfg->output_rate *= sdin_get_n_eff(cfg); 1452 cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF; 1453 } else { 1454 cfg->output_rate *= cfg->n; 1455 cfg->output_rate /= p * cfg->m; 1456 } 1457 1458 cfg->input_rate = input_rate; 1459 1460 return 0; 1461 } 1462 1463 /* 1464 * clk_pll_set_gain - set gain to m, n to calculate correct VCO rate 1465 * 1466 * @cfg: struct tegra_clk_pll_freq_table * cfg 1467 * 1468 * For Normal mode: 1469 * Fvco = Fref * NDIV / MDIV 1470 * 1471 * For fractional mode: 1472 * Fvco = Fref * (NDIV + 0.5 + SDM_DIN / PLL_SDM_COEFF) / MDIV 1473 */ 1474 static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg) 1475 { 1476 cfg->n = sdin_get_n_eff(cfg); 1477 cfg->m *= PLL_SDM_COEFF; 1478 } 1479 1480 static unsigned long 1481 tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params, 1482 unsigned long parent_rate) 1483 { 1484 unsigned long vco_min = params->vco_min; 1485 1486 params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF); 1487 vco_min = min(vco_min, params->vco_min); 1488 1489 return vco_min; 1490 } 1491 1492 static struct div_nmp pllx_nmp = { 1493 .divm_shift = 0, 1494 .divm_width = 8, 1495 .divn_shift = 8, 1496 .divn_width = 8, 1497 .divp_shift = 20, 1498 .divp_width = 5, 1499 }; 1500 /* 1501 * PLL post divider maps - two types: quasi-linear and exponential 1502 * post divider. 1503 */ 1504 #define PLL_QLIN_PDIV_MAX 16 1505 static const struct pdiv_map pll_qlin_pdiv_to_hw[] = { 1506 { .pdiv = 1, .hw_val = 0 }, 1507 { .pdiv = 2, .hw_val = 1 }, 1508 { .pdiv = 3, .hw_val = 2 }, 1509 { .pdiv = 4, .hw_val = 3 }, 1510 { .pdiv = 5, .hw_val = 4 }, 1511 { .pdiv = 6, .hw_val = 5 }, 1512 { .pdiv = 8, .hw_val = 6 }, 1513 { .pdiv = 9, .hw_val = 7 }, 1514 { .pdiv = 10, .hw_val = 8 }, 1515 { .pdiv = 12, .hw_val = 9 }, 1516 { .pdiv = 15, .hw_val = 10 }, 1517 { .pdiv = 16, .hw_val = 11 }, 1518 { .pdiv = 18, .hw_val = 12 }, 1519 { .pdiv = 20, .hw_val = 13 }, 1520 { .pdiv = 24, .hw_val = 14 }, 1521 { .pdiv = 30, .hw_val = 15 }, 1522 { .pdiv = 32, .hw_val = 16 }, 1523 }; 1524 1525 static u32 pll_qlin_p_to_pdiv(u32 p, u32 *pdiv) 1526 { 1527 int i; 1528 1529 if (p) { 1530 for (i = 0; i <= PLL_QLIN_PDIV_MAX; i++) { 1531 if (p <= pll_qlin_pdiv_to_hw[i].pdiv) { 1532 if (pdiv) 1533 *pdiv = i; 1534 return pll_qlin_pdiv_to_hw[i].pdiv; 1535 } 1536 } 1537 } 1538 1539 return -EINVAL; 1540 } 1541 1542 #define PLL_EXPO_PDIV_MAX 7 1543 static const struct pdiv_map pll_expo_pdiv_to_hw[] = { 1544 { .pdiv = 1, .hw_val = 0 }, 1545 { .pdiv = 2, .hw_val = 1 }, 1546 { .pdiv = 4, .hw_val = 2 }, 1547 { .pdiv = 8, .hw_val = 3 }, 1548 { .pdiv = 16, .hw_val = 4 }, 1549 { .pdiv = 32, .hw_val = 5 }, 1550 { .pdiv = 64, .hw_val = 6 }, 1551 { .pdiv = 128, .hw_val = 7 }, 1552 }; 1553 1554 static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv) 1555 { 1556 if (p) { 1557 u32 i = fls(p); 1558 1559 if (i == ffs(p)) 1560 i--; 1561 1562 if (i <= PLL_EXPO_PDIV_MAX) { 1563 if (pdiv) 1564 *pdiv = i; 1565 return 1 << i; 1566 } 1567 } 1568 return -EINVAL; 1569 } 1570 1571 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 1572 /* 1 GHz */ 1573 { 12000000, 1000000000, 166, 1, 2, 0 }, /* actual: 996.0 MHz */ 1574 { 13000000, 1000000000, 153, 1, 2, 0 }, /* actual: 994.0 MHz */ 1575 { 38400000, 1000000000, 156, 3, 2, 0 }, /* actual: 998.4 MHz */ 1576 { 0, 0, 0, 0, 0, 0 }, 1577 }; 1578 1579 static struct tegra_clk_pll_params pll_x_params = { 1580 .input_min = 12000000, 1581 .input_max = 800000000, 1582 .cf_min = 12000000, 1583 .cf_max = 38400000, 1584 .vco_min = 1350000000, 1585 .vco_max = 3000000000UL, 1586 .base_reg = PLLX_BASE, 1587 .misc_reg = PLLX_MISC0, 1588 .lock_mask = PLL_BASE_LOCK, 1589 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 1590 .lock_delay = 300, 1591 .ext_misc_reg[0] = PLLX_MISC0, 1592 .ext_misc_reg[1] = PLLX_MISC1, 1593 .ext_misc_reg[2] = PLLX_MISC2, 1594 .ext_misc_reg[3] = PLLX_MISC3, 1595 .ext_misc_reg[4] = PLLX_MISC4, 1596 .ext_misc_reg[5] = PLLX_MISC5, 1597 .iddq_reg = PLLX_MISC3, 1598 .iddq_bit_idx = PLLXP_IDDQ_BIT, 1599 .max_p = PLL_QLIN_PDIV_MAX, 1600 .mdiv_default = 2, 1601 .dyn_ramp_reg = PLLX_MISC2, 1602 .stepa_shift = 16, 1603 .stepb_shift = 24, 1604 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1605 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1606 .div_nmp = &pllx_nmp, 1607 .freq_table = pll_x_freq_table, 1608 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 1609 .dyn_ramp = tegra210_pllx_dyn_ramp, 1610 .set_defaults = tegra210_pllx_set_defaults, 1611 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1612 }; 1613 1614 static struct div_nmp pllc_nmp = { 1615 .divm_shift = 0, 1616 .divm_width = 8, 1617 .divn_shift = 10, 1618 .divn_width = 8, 1619 .divp_shift = 20, 1620 .divp_width = 5, 1621 }; 1622 1623 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { 1624 { 12000000, 510000000, 85, 1, 2, 0 }, 1625 { 13000000, 510000000, 78, 1, 2, 0 }, /* actual: 507.0 MHz */ 1626 { 38400000, 510000000, 79, 3, 2, 0 }, /* actual: 505.6 MHz */ 1627 { 0, 0, 0, 0, 0, 0 }, 1628 }; 1629 1630 static struct tegra_clk_pll_params pll_c_params = { 1631 .input_min = 12000000, 1632 .input_max = 700000000, 1633 .cf_min = 12000000, 1634 .cf_max = 50000000, 1635 .vco_min = 600000000, 1636 .vco_max = 1200000000, 1637 .base_reg = PLLC_BASE, 1638 .misc_reg = PLLC_MISC0, 1639 .lock_mask = PLL_BASE_LOCK, 1640 .lock_delay = 300, 1641 .iddq_reg = PLLC_MISC1, 1642 .iddq_bit_idx = PLLCX_IDDQ_BIT, 1643 .reset_reg = PLLC_MISC0, 1644 .reset_bit_idx = PLLCX_RESET_BIT, 1645 .max_p = PLL_QLIN_PDIV_MAX, 1646 .ext_misc_reg[0] = PLLC_MISC0, 1647 .ext_misc_reg[1] = PLLC_MISC1, 1648 .ext_misc_reg[2] = PLLC_MISC2, 1649 .ext_misc_reg[3] = PLLC_MISC3, 1650 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1651 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1652 .mdiv_default = 3, 1653 .div_nmp = &pllc_nmp, 1654 .freq_table = pll_cx_freq_table, 1655 .flags = TEGRA_PLL_USE_LOCK, 1656 .set_defaults = _pllc_set_defaults, 1657 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1658 }; 1659 1660 static struct div_nmp pllcx_nmp = { 1661 .divm_shift = 0, 1662 .divm_width = 8, 1663 .divn_shift = 10, 1664 .divn_width = 8, 1665 .divp_shift = 20, 1666 .divp_width = 5, 1667 }; 1668 1669 static struct tegra_clk_pll_params pll_c2_params = { 1670 .input_min = 12000000, 1671 .input_max = 700000000, 1672 .cf_min = 12000000, 1673 .cf_max = 50000000, 1674 .vco_min = 600000000, 1675 .vco_max = 1200000000, 1676 .base_reg = PLLC2_BASE, 1677 .misc_reg = PLLC2_MISC0, 1678 .iddq_reg = PLLC2_MISC1, 1679 .iddq_bit_idx = PLLCX_IDDQ_BIT, 1680 .reset_reg = PLLC2_MISC0, 1681 .reset_bit_idx = PLLCX_RESET_BIT, 1682 .lock_mask = PLLCX_BASE_LOCK, 1683 .lock_delay = 300, 1684 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1685 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1686 .mdiv_default = 3, 1687 .div_nmp = &pllcx_nmp, 1688 .max_p = PLL_QLIN_PDIV_MAX, 1689 .ext_misc_reg[0] = PLLC2_MISC0, 1690 .ext_misc_reg[1] = PLLC2_MISC1, 1691 .ext_misc_reg[2] = PLLC2_MISC2, 1692 .ext_misc_reg[3] = PLLC2_MISC3, 1693 .freq_table = pll_cx_freq_table, 1694 .flags = TEGRA_PLL_USE_LOCK, 1695 .set_defaults = _pllc2_set_defaults, 1696 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1697 }; 1698 1699 static struct tegra_clk_pll_params pll_c3_params = { 1700 .input_min = 12000000, 1701 .input_max = 700000000, 1702 .cf_min = 12000000, 1703 .cf_max = 50000000, 1704 .vco_min = 600000000, 1705 .vco_max = 1200000000, 1706 .base_reg = PLLC3_BASE, 1707 .misc_reg = PLLC3_MISC0, 1708 .lock_mask = PLLCX_BASE_LOCK, 1709 .lock_delay = 300, 1710 .iddq_reg = PLLC3_MISC1, 1711 .iddq_bit_idx = PLLCX_IDDQ_BIT, 1712 .reset_reg = PLLC3_MISC0, 1713 .reset_bit_idx = PLLCX_RESET_BIT, 1714 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1715 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1716 .mdiv_default = 3, 1717 .div_nmp = &pllcx_nmp, 1718 .max_p = PLL_QLIN_PDIV_MAX, 1719 .ext_misc_reg[0] = PLLC3_MISC0, 1720 .ext_misc_reg[1] = PLLC3_MISC1, 1721 .ext_misc_reg[2] = PLLC3_MISC2, 1722 .ext_misc_reg[3] = PLLC3_MISC3, 1723 .freq_table = pll_cx_freq_table, 1724 .flags = TEGRA_PLL_USE_LOCK, 1725 .set_defaults = _pllc3_set_defaults, 1726 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1727 }; 1728 1729 static struct div_nmp pllss_nmp = { 1730 .divm_shift = 0, 1731 .divm_width = 8, 1732 .divn_shift = 8, 1733 .divn_width = 8, 1734 .divp_shift = 19, 1735 .divp_width = 5, 1736 }; 1737 1738 static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = { 1739 { 12000000, 600000000, 50, 1, 1, 0 }, 1740 { 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */ 1741 { 38400000, 600000000, 62, 4, 1, 0 }, /* actual: 595.2 MHz */ 1742 { 0, 0, 0, 0, 0, 0 }, 1743 }; 1744 1745 static const struct clk_div_table pll_vco_post_div_table[] = { 1746 { .val = 0, .div = 1 }, 1747 { .val = 1, .div = 2 }, 1748 { .val = 2, .div = 3 }, 1749 { .val = 3, .div = 4 }, 1750 { .val = 4, .div = 5 }, 1751 { .val = 5, .div = 6 }, 1752 { .val = 6, .div = 8 }, 1753 { .val = 7, .div = 10 }, 1754 { .val = 8, .div = 12 }, 1755 { .val = 9, .div = 16 }, 1756 { .val = 10, .div = 12 }, 1757 { .val = 11, .div = 16 }, 1758 { .val = 12, .div = 20 }, 1759 { .val = 13, .div = 24 }, 1760 { .val = 14, .div = 32 }, 1761 { .val = 0, .div = 0 }, 1762 }; 1763 1764 static struct tegra_clk_pll_params pll_c4_vco_params = { 1765 .input_min = 9600000, 1766 .input_max = 800000000, 1767 .cf_min = 9600000, 1768 .cf_max = 19200000, 1769 .vco_min = 500000000, 1770 .vco_max = 1080000000, 1771 .base_reg = PLLC4_BASE, 1772 .misc_reg = PLLC4_MISC0, 1773 .lock_mask = PLL_BASE_LOCK, 1774 .lock_delay = 300, 1775 .max_p = PLL_QLIN_PDIV_MAX, 1776 .ext_misc_reg[0] = PLLC4_MISC0, 1777 .iddq_reg = PLLC4_BASE, 1778 .iddq_bit_idx = PLLSS_IDDQ_BIT, 1779 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1780 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1781 .mdiv_default = 3, 1782 .div_nmp = &pllss_nmp, 1783 .freq_table = pll_c4_vco_freq_table, 1784 .set_defaults = tegra210_pllc4_set_defaults, 1785 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, 1786 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1787 }; 1788 1789 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 1790 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */ 1791 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */ 1792 { 38400000, 297600000, 93, 4, 3, 0 }, 1793 { 38400000, 400000000, 125, 4, 3, 0 }, 1794 { 38400000, 532800000, 111, 4, 2, 0 }, 1795 { 38400000, 665600000, 104, 3, 2, 0 }, 1796 { 38400000, 800000000, 125, 3, 2, 0 }, 1797 { 38400000, 931200000, 97, 4, 1, 0 }, 1798 { 38400000, 1065600000, 111, 4, 1, 0 }, 1799 { 38400000, 1200000000, 125, 4, 1, 0 }, 1800 { 38400000, 1331200000, 104, 3, 1, 0 }, 1801 { 38400000, 1459200000, 76, 2, 1, 0 }, 1802 { 38400000, 1600000000, 125, 3, 1, 0 }, 1803 { 0, 0, 0, 0, 0, 0 }, 1804 }; 1805 1806 static struct div_nmp pllm_nmp = { 1807 .divm_shift = 0, 1808 .divm_width = 8, 1809 .override_divm_shift = 0, 1810 .divn_shift = 8, 1811 .divn_width = 8, 1812 .override_divn_shift = 8, 1813 .divp_shift = 20, 1814 .divp_width = 5, 1815 .override_divp_shift = 27, 1816 }; 1817 1818 static struct tegra_clk_pll_params pll_m_params = { 1819 .input_min = 9600000, 1820 .input_max = 500000000, 1821 .cf_min = 9600000, 1822 .cf_max = 19200000, 1823 .vco_min = 800000000, 1824 .vco_max = 1866000000, 1825 .base_reg = PLLM_BASE, 1826 .misc_reg = PLLM_MISC2, 1827 .lock_mask = PLL_BASE_LOCK, 1828 .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE, 1829 .lock_delay = 300, 1830 .iddq_reg = PLLM_MISC2, 1831 .iddq_bit_idx = PLLM_IDDQ_BIT, 1832 .max_p = PLL_QLIN_PDIV_MAX, 1833 .ext_misc_reg[0] = PLLM_MISC2, 1834 .ext_misc_reg[1] = PLLM_MISC1, 1835 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1836 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1837 .div_nmp = &pllm_nmp, 1838 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 1839 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, 1840 .freq_table = pll_m_freq_table, 1841 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 1842 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1843 }; 1844 1845 static struct tegra_clk_pll_params pll_mb_params = { 1846 .input_min = 9600000, 1847 .input_max = 500000000, 1848 .cf_min = 9600000, 1849 .cf_max = 19200000, 1850 .vco_min = 800000000, 1851 .vco_max = 1866000000, 1852 .base_reg = PLLMB_BASE, 1853 .misc_reg = PLLMB_MISC1, 1854 .lock_mask = PLL_BASE_LOCK, 1855 .lock_delay = 300, 1856 .iddq_reg = PLLMB_MISC1, 1857 .iddq_bit_idx = PLLMB_IDDQ_BIT, 1858 .max_p = PLL_QLIN_PDIV_MAX, 1859 .ext_misc_reg[0] = PLLMB_MISC1, 1860 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1861 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1862 .div_nmp = &pllm_nmp, 1863 .freq_table = pll_m_freq_table, 1864 .flags = TEGRA_PLL_USE_LOCK, 1865 .set_defaults = tegra210_pllmb_set_defaults, 1866 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1867 }; 1868 1869 1870 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 1871 /* PLLE special case: use cpcon field to store cml divider value */ 1872 { 672000000, 100000000, 125, 42, 0, 13 }, 1873 { 624000000, 100000000, 125, 39, 0, 13 }, 1874 { 336000000, 100000000, 125, 21, 0, 13 }, 1875 { 312000000, 100000000, 200, 26, 0, 14 }, 1876 { 38400000, 100000000, 125, 2, 0, 14 }, 1877 { 12000000, 100000000, 200, 1, 0, 14 }, 1878 { 0, 0, 0, 0, 0, 0 }, 1879 }; 1880 1881 static struct div_nmp plle_nmp = { 1882 .divm_shift = 0, 1883 .divm_width = 8, 1884 .divn_shift = 8, 1885 .divn_width = 8, 1886 .divp_shift = 24, 1887 .divp_width = 5, 1888 }; 1889 1890 static struct tegra_clk_pll_params pll_e_params = { 1891 .input_min = 12000000, 1892 .input_max = 800000000, 1893 .cf_min = 12000000, 1894 .cf_max = 38400000, 1895 .vco_min = 1600000000, 1896 .vco_max = 2500000000U, 1897 .base_reg = PLLE_BASE, 1898 .misc_reg = PLLE_MISC0, 1899 .aux_reg = PLLE_AUX, 1900 .lock_mask = PLLE_MISC_LOCK, 1901 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 1902 .lock_delay = 300, 1903 .div_nmp = &plle_nmp, 1904 .freq_table = pll_e_freq_table, 1905 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK | 1906 TEGRA_PLL_HAS_LOCK_ENABLE, 1907 .fixed_rate = 100000000, 1908 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1909 }; 1910 1911 static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = { 1912 { 12000000, 672000000, 56, 1, 1, 0 }, 1913 { 13000000, 672000000, 51, 1, 1, 0 }, /* actual: 663.0 MHz */ 1914 { 38400000, 672000000, 70, 4, 1, 0 }, 1915 { 0, 0, 0, 0, 0, 0 }, 1916 }; 1917 1918 static struct div_nmp pllre_nmp = { 1919 .divm_shift = 0, 1920 .divm_width = 8, 1921 .divn_shift = 8, 1922 .divn_width = 8, 1923 .divp_shift = 16, 1924 .divp_width = 5, 1925 }; 1926 1927 static struct tegra_clk_pll_params pll_re_vco_params = { 1928 .input_min = 9600000, 1929 .input_max = 800000000, 1930 .cf_min = 9600000, 1931 .cf_max = 19200000, 1932 .vco_min = 350000000, 1933 .vco_max = 700000000, 1934 .base_reg = PLLRE_BASE, 1935 .misc_reg = PLLRE_MISC0, 1936 .lock_mask = PLLRE_MISC_LOCK, 1937 .lock_delay = 300, 1938 .max_p = PLL_QLIN_PDIV_MAX, 1939 .ext_misc_reg[0] = PLLRE_MISC0, 1940 .iddq_reg = PLLRE_MISC0, 1941 .iddq_bit_idx = PLLRE_IDDQ_BIT, 1942 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 1943 .pdiv_tohw = pll_qlin_pdiv_to_hw, 1944 .div_nmp = &pllre_nmp, 1945 .freq_table = pll_re_vco_freq_table, 1946 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT, 1947 .set_defaults = tegra210_pllre_set_defaults, 1948 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1949 }; 1950 1951 static struct div_nmp pllp_nmp = { 1952 .divm_shift = 0, 1953 .divm_width = 8, 1954 .divn_shift = 10, 1955 .divn_width = 8, 1956 .divp_shift = 20, 1957 .divp_width = 5, 1958 }; 1959 1960 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 1961 { 12000000, 408000000, 34, 1, 1, 0 }, 1962 { 38400000, 408000000, 85, 8, 1, 0 }, /* cf = 4.8MHz, allowed exception */ 1963 { 0, 0, 0, 0, 0, 0 }, 1964 }; 1965 1966 static struct tegra_clk_pll_params pll_p_params = { 1967 .input_min = 9600000, 1968 .input_max = 800000000, 1969 .cf_min = 9600000, 1970 .cf_max = 19200000, 1971 .vco_min = 350000000, 1972 .vco_max = 700000000, 1973 .base_reg = PLLP_BASE, 1974 .misc_reg = PLLP_MISC0, 1975 .lock_mask = PLL_BASE_LOCK, 1976 .lock_delay = 300, 1977 .iddq_reg = PLLP_MISC0, 1978 .iddq_bit_idx = PLLXP_IDDQ_BIT, 1979 .ext_misc_reg[0] = PLLP_MISC0, 1980 .ext_misc_reg[1] = PLLP_MISC1, 1981 .div_nmp = &pllp_nmp, 1982 .freq_table = pll_p_freq_table, 1983 .fixed_rate = 408000000, 1984 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, 1985 .set_defaults = tegra210_pllp_set_defaults, 1986 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 1987 }; 1988 1989 static struct tegra_clk_pll_params pll_a1_params = { 1990 .input_min = 12000000, 1991 .input_max = 700000000, 1992 .cf_min = 12000000, 1993 .cf_max = 50000000, 1994 .vco_min = 600000000, 1995 .vco_max = 1200000000, 1996 .base_reg = PLLA1_BASE, 1997 .misc_reg = PLLA1_MISC0, 1998 .lock_mask = PLLCX_BASE_LOCK, 1999 .lock_delay = 300, 2000 .iddq_reg = PLLA1_MISC1, 2001 .iddq_bit_idx = PLLCX_IDDQ_BIT, 2002 .reset_reg = PLLA1_MISC0, 2003 .reset_bit_idx = PLLCX_RESET_BIT, 2004 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 2005 .pdiv_tohw = pll_qlin_pdiv_to_hw, 2006 .div_nmp = &pllc_nmp, 2007 .ext_misc_reg[0] = PLLA1_MISC0, 2008 .ext_misc_reg[1] = PLLA1_MISC1, 2009 .ext_misc_reg[2] = PLLA1_MISC2, 2010 .ext_misc_reg[3] = PLLA1_MISC3, 2011 .freq_table = pll_cx_freq_table, 2012 .flags = TEGRA_PLL_USE_LOCK, 2013 .set_defaults = _plla1_set_defaults, 2014 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 2015 }; 2016 2017 static struct div_nmp plla_nmp = { 2018 .divm_shift = 0, 2019 .divm_width = 8, 2020 .divn_shift = 8, 2021 .divn_width = 8, 2022 .divp_shift = 20, 2023 .divp_width = 5, 2024 }; 2025 2026 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 2027 { 12000000, 282240000, 47, 1, 2, 1, 0xf148 }, /* actual: 282240234 */ 2028 { 12000000, 368640000, 61, 1, 2, 1, 0xfe15 }, /* actual: 368640381 */ 2029 { 12000000, 240000000, 60, 1, 3, 1, 0 }, 2030 { 13000000, 282240000, 43, 1, 2, 1, 0xfd7d }, /* actual: 282239807 */ 2031 { 13000000, 368640000, 56, 1, 2, 1, 0x06d8 }, /* actual: 368640137 */ 2032 { 13000000, 240000000, 55, 1, 3, 1, 0 }, /* actual: 238.3 MHz */ 2033 { 38400000, 282240000, 44, 3, 2, 1, 0xf333 }, /* actual: 282239844 */ 2034 { 38400000, 368640000, 57, 3, 2, 1, 0x0333 }, /* actual: 368639844 */ 2035 { 38400000, 240000000, 75, 3, 3, 1, 0 }, 2036 { 0, 0, 0, 0, 0, 0, 0 }, 2037 }; 2038 2039 static struct tegra_clk_pll_params pll_a_params = { 2040 .input_min = 12000000, 2041 .input_max = 800000000, 2042 .cf_min = 12000000, 2043 .cf_max = 19200000, 2044 .vco_min = 500000000, 2045 .vco_max = 1000000000, 2046 .base_reg = PLLA_BASE, 2047 .misc_reg = PLLA_MISC0, 2048 .lock_mask = PLL_BASE_LOCK, 2049 .lock_delay = 300, 2050 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 2051 .pdiv_tohw = pll_qlin_pdiv_to_hw, 2052 .iddq_reg = PLLA_BASE, 2053 .iddq_bit_idx = PLLA_IDDQ_BIT, 2054 .div_nmp = &plla_nmp, 2055 .sdm_din_reg = PLLA_MISC1, 2056 .sdm_din_mask = PLLA_SDM_DIN_MASK, 2057 .sdm_ctrl_reg = PLLA_MISC2, 2058 .sdm_ctrl_en_mask = PLLA_SDM_EN_MASK, 2059 .ext_misc_reg[0] = PLLA_MISC0, 2060 .ext_misc_reg[1] = PLLA_MISC1, 2061 .ext_misc_reg[2] = PLLA_MISC2, 2062 .freq_table = pll_a_freq_table, 2063 .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW, 2064 .set_defaults = tegra210_plla_set_defaults, 2065 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 2066 .set_gain = tegra210_clk_pll_set_gain, 2067 .adjust_vco = tegra210_clk_adjust_vco_min, 2068 }; 2069 2070 static struct div_nmp plld_nmp = { 2071 .divm_shift = 0, 2072 .divm_width = 8, 2073 .divn_shift = 11, 2074 .divn_width = 8, 2075 .divp_shift = 20, 2076 .divp_width = 3, 2077 }; 2078 2079 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 2080 { 12000000, 594000000, 99, 1, 2, 0, 0 }, 2081 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */ 2082 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 }, 2083 { 0, 0, 0, 0, 0, 0, 0 }, 2084 }; 2085 2086 static struct tegra_clk_pll_params pll_d_params = { 2087 .input_min = 12000000, 2088 .input_max = 800000000, 2089 .cf_min = 12000000, 2090 .cf_max = 38400000, 2091 .vco_min = 750000000, 2092 .vco_max = 1500000000, 2093 .base_reg = PLLD_BASE, 2094 .misc_reg = PLLD_MISC0, 2095 .lock_mask = PLL_BASE_LOCK, 2096 .lock_delay = 1000, 2097 .iddq_reg = PLLD_MISC0, 2098 .iddq_bit_idx = PLLD_IDDQ_BIT, 2099 .round_p_to_pdiv = pll_expo_p_to_pdiv, 2100 .pdiv_tohw = pll_expo_pdiv_to_hw, 2101 .div_nmp = &plld_nmp, 2102 .sdm_din_reg = PLLD_MISC0, 2103 .sdm_din_mask = PLLA_SDM_DIN_MASK, 2104 .sdm_ctrl_reg = PLLD_MISC0, 2105 .sdm_ctrl_en_mask = PLLD_SDM_EN_MASK, 2106 .ext_misc_reg[0] = PLLD_MISC0, 2107 .ext_misc_reg[1] = PLLD_MISC1, 2108 .freq_table = pll_d_freq_table, 2109 .flags = TEGRA_PLL_USE_LOCK, 2110 .mdiv_default = 1, 2111 .set_defaults = tegra210_plld_set_defaults, 2112 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 2113 .set_gain = tegra210_clk_pll_set_gain, 2114 .adjust_vco = tegra210_clk_adjust_vco_min, 2115 }; 2116 2117 static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = { 2118 { 12000000, 594000000, 99, 1, 2, 0, 0xf000 }, 2119 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */ 2120 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 }, 2121 { 0, 0, 0, 0, 0, 0, 0 }, 2122 }; 2123 2124 /* s/w policy, always tegra_pll_ref */ 2125 static struct tegra_clk_pll_params pll_d2_params = { 2126 .input_min = 12000000, 2127 .input_max = 800000000, 2128 .cf_min = 12000000, 2129 .cf_max = 38400000, 2130 .vco_min = 750000000, 2131 .vco_max = 1500000000, 2132 .base_reg = PLLD2_BASE, 2133 .misc_reg = PLLD2_MISC0, 2134 .lock_mask = PLL_BASE_LOCK, 2135 .lock_delay = 300, 2136 .iddq_reg = PLLD2_BASE, 2137 .iddq_bit_idx = PLLSS_IDDQ_BIT, 2138 .sdm_din_reg = PLLD2_MISC3, 2139 .sdm_din_mask = PLLA_SDM_DIN_MASK, 2140 .sdm_ctrl_reg = PLLD2_MISC1, 2141 .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK, 2142 /* disable spread-spectrum for pll_d2 */ 2143 .ssc_ctrl_reg = 0, 2144 .ssc_ctrl_en_mask = 0, 2145 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 2146 .pdiv_tohw = pll_qlin_pdiv_to_hw, 2147 .div_nmp = &pllss_nmp, 2148 .ext_misc_reg[0] = PLLD2_MISC0, 2149 .ext_misc_reg[1] = PLLD2_MISC1, 2150 .ext_misc_reg[2] = PLLD2_MISC2, 2151 .ext_misc_reg[3] = PLLD2_MISC3, 2152 .max_p = PLL_QLIN_PDIV_MAX, 2153 .mdiv_default = 1, 2154 .freq_table = tegra210_pll_d2_freq_table, 2155 .set_defaults = tegra210_plld2_set_defaults, 2156 .flags = TEGRA_PLL_USE_LOCK, 2157 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 2158 .set_gain = tegra210_clk_pll_set_gain, 2159 .adjust_vco = tegra210_clk_adjust_vco_min, 2160 }; 2161 2162 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = { 2163 { 12000000, 270000000, 90, 1, 4, 0, 0xf000 }, 2164 { 13000000, 270000000, 83, 1, 4, 0, 0xf000 }, /* actual: 269.8 MHz */ 2165 { 38400000, 270000000, 28, 1, 4, 0, 0xf400 }, 2166 { 0, 0, 0, 0, 0, 0, 0 }, 2167 }; 2168 2169 static struct tegra_clk_pll_params pll_dp_params = { 2170 .input_min = 12000000, 2171 .input_max = 800000000, 2172 .cf_min = 12000000, 2173 .cf_max = 38400000, 2174 .vco_min = 750000000, 2175 .vco_max = 1500000000, 2176 .base_reg = PLLDP_BASE, 2177 .misc_reg = PLLDP_MISC, 2178 .lock_mask = PLL_BASE_LOCK, 2179 .lock_delay = 300, 2180 .iddq_reg = PLLDP_BASE, 2181 .iddq_bit_idx = PLLSS_IDDQ_BIT, 2182 .sdm_din_reg = PLLDP_SS_CTRL2, 2183 .sdm_din_mask = PLLA_SDM_DIN_MASK, 2184 .sdm_ctrl_reg = PLLDP_SS_CFG, 2185 .sdm_ctrl_en_mask = PLLDP_SDM_EN_MASK, 2186 .ssc_ctrl_reg = PLLDP_SS_CFG, 2187 .ssc_ctrl_en_mask = PLLDP_SSC_EN_MASK, 2188 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 2189 .pdiv_tohw = pll_qlin_pdiv_to_hw, 2190 .div_nmp = &pllss_nmp, 2191 .ext_misc_reg[0] = PLLDP_MISC, 2192 .ext_misc_reg[1] = PLLDP_SS_CFG, 2193 .ext_misc_reg[2] = PLLDP_SS_CTRL1, 2194 .ext_misc_reg[3] = PLLDP_SS_CTRL2, 2195 .max_p = PLL_QLIN_PDIV_MAX, 2196 .mdiv_default = 1, 2197 .freq_table = pll_dp_freq_table, 2198 .set_defaults = tegra210_plldp_set_defaults, 2199 .flags = TEGRA_PLL_USE_LOCK, 2200 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 2201 .set_gain = tegra210_clk_pll_set_gain, 2202 .adjust_vco = tegra210_clk_adjust_vco_min, 2203 }; 2204 2205 static struct div_nmp pllu_nmp = { 2206 .divm_shift = 0, 2207 .divm_width = 8, 2208 .divn_shift = 8, 2209 .divn_width = 8, 2210 .divp_shift = 16, 2211 .divp_width = 5, 2212 }; 2213 2214 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 2215 { 12000000, 480000000, 40, 1, 0, 0 }, 2216 { 13000000, 480000000, 36, 1, 0, 0 }, /* actual: 468.0 MHz */ 2217 { 38400000, 480000000, 25, 2, 0, 0 }, 2218 { 0, 0, 0, 0, 0, 0 }, 2219 }; 2220 2221 static struct tegra_clk_pll_params pll_u_vco_params = { 2222 .input_min = 9600000, 2223 .input_max = 800000000, 2224 .cf_min = 9600000, 2225 .cf_max = 19200000, 2226 .vco_min = 350000000, 2227 .vco_max = 700000000, 2228 .base_reg = PLLU_BASE, 2229 .misc_reg = PLLU_MISC0, 2230 .lock_mask = PLL_BASE_LOCK, 2231 .lock_delay = 1000, 2232 .iddq_reg = PLLU_MISC0, 2233 .iddq_bit_idx = PLLU_IDDQ_BIT, 2234 .ext_misc_reg[0] = PLLU_MISC0, 2235 .ext_misc_reg[1] = PLLU_MISC1, 2236 .round_p_to_pdiv = pll_qlin_p_to_pdiv, 2237 .pdiv_tohw = pll_qlin_pdiv_to_hw, 2238 .div_nmp = &pllu_nmp, 2239 .freq_table = pll_u_freq_table, 2240 .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, 2241 }; 2242 2243 struct utmi_clk_param { 2244 /* Oscillator Frequency in KHz */ 2245 u32 osc_frequency; 2246 /* UTMIP PLL Enable Delay Count */ 2247 u8 enable_delay_count; 2248 /* UTMIP PLL Stable count */ 2249 u16 stable_count; 2250 /* UTMIP PLL Active delay count */ 2251 u8 active_delay_count; 2252 /* UTMIP PLL Xtal frequency count */ 2253 u16 xtal_freq_count; 2254 }; 2255 2256 static const struct utmi_clk_param utmi_parameters[] = { 2257 { 2258 .osc_frequency = 38400000, .enable_delay_count = 0x0, 2259 .stable_count = 0x0, .active_delay_count = 0x6, 2260 .xtal_freq_count = 0x80 2261 }, { 2262 .osc_frequency = 13000000, .enable_delay_count = 0x02, 2263 .stable_count = 0x33, .active_delay_count = 0x05, 2264 .xtal_freq_count = 0x7f 2265 }, { 2266 .osc_frequency = 19200000, .enable_delay_count = 0x03, 2267 .stable_count = 0x4b, .active_delay_count = 0x06, 2268 .xtal_freq_count = 0xbb 2269 }, { 2270 .osc_frequency = 12000000, .enable_delay_count = 0x02, 2271 .stable_count = 0x2f, .active_delay_count = 0x08, 2272 .xtal_freq_count = 0x76 2273 }, { 2274 .osc_frequency = 26000000, .enable_delay_count = 0x04, 2275 .stable_count = 0x66, .active_delay_count = 0x09, 2276 .xtal_freq_count = 0xfe 2277 }, { 2278 .osc_frequency = 16800000, .enable_delay_count = 0x03, 2279 .stable_count = 0x41, .active_delay_count = 0x0a, 2280 .xtal_freq_count = 0xa4 2281 }, 2282 }; 2283 2284 static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { 2285 [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true }, 2286 [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true }, 2287 [tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true }, 2288 [tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true }, 2289 [tegra_clk_sdmmc2_9] = { .dt_id = TEGRA210_CLK_SDMMC2, .present = true }, 2290 [tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true }, 2291 [tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true }, 2292 [tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true }, 2293 [tegra_clk_sdmmc4_9] = { .dt_id = TEGRA210_CLK_SDMMC4, .present = true }, 2294 [tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true }, 2295 [tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true }, 2296 [tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true }, 2297 [tegra_clk_isp_9] = { .dt_id = TEGRA210_CLK_ISP, .present = true }, 2298 [tegra_clk_disp2_8] = { .dt_id = TEGRA210_CLK_DISP2, .present = true }, 2299 [tegra_clk_disp1_8] = { .dt_id = TEGRA210_CLK_DISP1, .present = true }, 2300 [tegra_clk_host1x_9] = { .dt_id = TEGRA210_CLK_HOST1X, .present = true }, 2301 [tegra_clk_i2s0] = { .dt_id = TEGRA210_CLK_I2S0, .present = true }, 2302 [tegra_clk_apbdma] = { .dt_id = TEGRA210_CLK_APBDMA, .present = true }, 2303 [tegra_clk_kfuse] = { .dt_id = TEGRA210_CLK_KFUSE, .present = true }, 2304 [tegra_clk_sbc1_9] = { .dt_id = TEGRA210_CLK_SBC1, .present = true }, 2305 [tegra_clk_sbc2_9] = { .dt_id = TEGRA210_CLK_SBC2, .present = true }, 2306 [tegra_clk_sbc3_9] = { .dt_id = TEGRA210_CLK_SBC3, .present = true }, 2307 [tegra_clk_i2c5] = { .dt_id = TEGRA210_CLK_I2C5, .present = true }, 2308 [tegra_clk_csi] = { .dt_id = TEGRA210_CLK_CSI, .present = true }, 2309 [tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true }, 2310 [tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true }, 2311 [tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true }, 2312 [tegra_clk_emc] = { .dt_id = TEGRA210_CLK_EMC, .present = true }, 2313 [tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true }, 2314 [tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true }, 2315 [tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true }, 2316 [tegra_clk_i2c3] = { .dt_id = TEGRA210_CLK_I2C3, .present = true }, 2317 [tegra_clk_sbc4_9] = { .dt_id = TEGRA210_CLK_SBC4, .present = true }, 2318 [tegra_clk_sdmmc3_9] = { .dt_id = TEGRA210_CLK_SDMMC3, .present = true }, 2319 [tegra_clk_pcie] = { .dt_id = TEGRA210_CLK_PCIE, .present = true }, 2320 [tegra_clk_owr_8] = { .dt_id = TEGRA210_CLK_OWR, .present = true }, 2321 [tegra_clk_afi] = { .dt_id = TEGRA210_CLK_AFI, .present = true }, 2322 [tegra_clk_csite_8] = { .dt_id = TEGRA210_CLK_CSITE, .present = true }, 2323 [tegra_clk_soc_therm_8] = { .dt_id = TEGRA210_CLK_SOC_THERM, .present = true }, 2324 [tegra_clk_dtv] = { .dt_id = TEGRA210_CLK_DTV, .present = true }, 2325 [tegra_clk_i2cslow] = { .dt_id = TEGRA210_CLK_I2CSLOW, .present = true }, 2326 [tegra_clk_tsec_8] = { .dt_id = TEGRA210_CLK_TSEC, .present = true }, 2327 [tegra_clk_xusb_host] = { .dt_id = TEGRA210_CLK_XUSB_HOST, .present = true }, 2328 [tegra_clk_csus] = { .dt_id = TEGRA210_CLK_CSUS, .present = true }, 2329 [tegra_clk_mselect] = { .dt_id = TEGRA210_CLK_MSELECT, .present = true }, 2330 [tegra_clk_tsensor] = { .dt_id = TEGRA210_CLK_TSENSOR, .present = true }, 2331 [tegra_clk_i2s3] = { .dt_id = TEGRA210_CLK_I2S3, .present = true }, 2332 [tegra_clk_i2s4] = { .dt_id = TEGRA210_CLK_I2S4, .present = true }, 2333 [tegra_clk_i2c4] = { .dt_id = TEGRA210_CLK_I2C4, .present = true }, 2334 [tegra_clk_d_audio] = { .dt_id = TEGRA210_CLK_D_AUDIO, .present = true }, 2335 [tegra_clk_hda2codec_2x_8] = { .dt_id = TEGRA210_CLK_HDA2CODEC_2X, .present = true }, 2336 [tegra_clk_spdif_2x] = { .dt_id = TEGRA210_CLK_SPDIF_2X, .present = true }, 2337 [tegra_clk_actmon] = { .dt_id = TEGRA210_CLK_ACTMON, .present = true }, 2338 [tegra_clk_extern1] = { .dt_id = TEGRA210_CLK_EXTERN1, .present = true }, 2339 [tegra_clk_extern2] = { .dt_id = TEGRA210_CLK_EXTERN2, .present = true }, 2340 [tegra_clk_extern3] = { .dt_id = TEGRA210_CLK_EXTERN3, .present = true }, 2341 [tegra_clk_sata_oob_8] = { .dt_id = TEGRA210_CLK_SATA_OOB, .present = true }, 2342 [tegra_clk_sata_8] = { .dt_id = TEGRA210_CLK_SATA, .present = true }, 2343 [tegra_clk_hda_8] = { .dt_id = TEGRA210_CLK_HDA, .present = true }, 2344 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA210_CLK_HDA2HDMI, .present = true }, 2345 [tegra_clk_cilab] = { .dt_id = TEGRA210_CLK_CILAB, .present = true }, 2346 [tegra_clk_cilcd] = { .dt_id = TEGRA210_CLK_CILCD, .present = true }, 2347 [tegra_clk_cile] = { .dt_id = TEGRA210_CLK_CILE, .present = true }, 2348 [tegra_clk_dsialp] = { .dt_id = TEGRA210_CLK_DSIALP, .present = true }, 2349 [tegra_clk_dsiblp] = { .dt_id = TEGRA210_CLK_DSIBLP, .present = true }, 2350 [tegra_clk_entropy_8] = { .dt_id = TEGRA210_CLK_ENTROPY, .present = true }, 2351 [tegra_clk_xusb_ss] = { .dt_id = TEGRA210_CLK_XUSB_SS, .present = true }, 2352 [tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true }, 2353 [tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true }, 2354 [tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true }, 2355 [tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true }, 2356 [tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true }, 2357 [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true }, 2358 [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true }, 2359 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true }, 2360 [tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true }, 2361 [tegra_clk_sor1_src] = { .dt_id = TEGRA210_CLK_SOR1_SRC, .present = true }, 2362 [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true }, 2363 [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, }, 2364 [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true }, 2365 [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true }, 2366 [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true }, 2367 [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true }, 2368 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true }, 2369 [tegra_clk_fuse] = { .dt_id = TEGRA210_CLK_FUSE, .present = true }, 2370 [tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true }, 2371 [tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true }, 2372 [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true }, 2373 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true }, 2374 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true }, 2375 [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true }, 2376 [tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true }, 2377 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true }, 2378 [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true }, 2379 [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true }, 2380 [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true }, 2381 [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true }, 2382 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true }, 2383 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true }, 2384 [tegra_clk_pll_p_out4_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT4, .present = true }, 2385 [tegra_clk_pll_p_out_hsio] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_HSIO, .present = true }, 2386 [tegra_clk_pll_p_out_xusb] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_XUSB, .present = true }, 2387 [tegra_clk_pll_p_out_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_CPU, .present = true }, 2388 [tegra_clk_pll_p_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_ADSP, .present = true }, 2389 [tegra_clk_pll_a] = { .dt_id = TEGRA210_CLK_PLL_A, .present = true }, 2390 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0, .present = true }, 2391 [tegra_clk_pll_d] = { .dt_id = TEGRA210_CLK_PLL_D, .present = true }, 2392 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA210_CLK_PLL_D_OUT0, .present = true }, 2393 [tegra_clk_pll_d2] = { .dt_id = TEGRA210_CLK_PLL_D2, .present = true }, 2394 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA210_CLK_PLL_D2_OUT0, .present = true }, 2395 [tegra_clk_pll_u] = { .dt_id = TEGRA210_CLK_PLL_U, .present = true }, 2396 [tegra_clk_pll_u_out] = { .dt_id = TEGRA210_CLK_PLL_U_OUT, .present = true }, 2397 [tegra_clk_pll_u_out1] = { .dt_id = TEGRA210_CLK_PLL_U_OUT1, .present = true }, 2398 [tegra_clk_pll_u_out2] = { .dt_id = TEGRA210_CLK_PLL_U_OUT2, .present = true }, 2399 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA210_CLK_PLL_U_480M, .present = true }, 2400 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA210_CLK_PLL_U_60M, .present = true }, 2401 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA210_CLK_PLL_U_48M, .present = true }, 2402 [tegra_clk_pll_x] = { .dt_id = TEGRA210_CLK_PLL_X, .present = true }, 2403 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA210_CLK_PLL_X_OUT0, .present = true }, 2404 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA210_CLK_PLL_RE_VCO, .present = true }, 2405 [tegra_clk_pll_re_out] = { .dt_id = TEGRA210_CLK_PLL_RE_OUT, .present = true }, 2406 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC, .present = true }, 2407 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA210_CLK_I2S0_SYNC, .present = true }, 2408 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA210_CLK_I2S1_SYNC, .present = true }, 2409 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA210_CLK_I2S2_SYNC, .present = true }, 2410 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA210_CLK_I2S3_SYNC, .present = true }, 2411 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA210_CLK_I2S4_SYNC, .present = true }, 2412 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA210_CLK_VIMCLK_SYNC, .present = true }, 2413 [tegra_clk_audio0] = { .dt_id = TEGRA210_CLK_AUDIO0, .present = true }, 2414 [tegra_clk_audio1] = { .dt_id = TEGRA210_CLK_AUDIO1, .present = true }, 2415 [tegra_clk_audio2] = { .dt_id = TEGRA210_CLK_AUDIO2, .present = true }, 2416 [tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true }, 2417 [tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true }, 2418 [tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true }, 2419 [tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true }, 2420 [tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true }, 2421 [tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true }, 2422 [tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true }, 2423 [tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true }, 2424 [tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true }, 2425 [tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true }, 2426 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA210_CLK_XUSB_FS_SRC, .present = true }, 2427 [tegra_clk_xusb_ss_src_8] = { .dt_id = TEGRA210_CLK_XUSB_SS_SRC, .present = true }, 2428 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA210_CLK_XUSB_SS_DIV2, .present = true }, 2429 [tegra_clk_xusb_dev_src_8] = { .dt_id = TEGRA210_CLK_XUSB_DEV_SRC, .present = true }, 2430 [tegra_clk_xusb_dev] = { .dt_id = TEGRA210_CLK_XUSB_DEV, .present = true }, 2431 [tegra_clk_xusb_hs_src_4] = { .dt_id = TEGRA210_CLK_XUSB_HS_SRC, .present = true }, 2432 [tegra_clk_xusb_ssp_src] = { .dt_id = TEGRA210_CLK_XUSB_SSP_SRC, .present = true }, 2433 [tegra_clk_usb2_hsic_trk] = { .dt_id = TEGRA210_CLK_USB2_HSIC_TRK, .present = true }, 2434 [tegra_clk_hsic_trk] = { .dt_id = TEGRA210_CLK_HSIC_TRK, .present = true }, 2435 [tegra_clk_usb2_trk] = { .dt_id = TEGRA210_CLK_USB2_TRK, .present = true }, 2436 [tegra_clk_sclk] = { .dt_id = TEGRA210_CLK_SCLK, .present = true }, 2437 [tegra_clk_sclk_mux] = { .dt_id = TEGRA210_CLK_SCLK_MUX, .present = true }, 2438 [tegra_clk_hclk] = { .dt_id = TEGRA210_CLK_HCLK, .present = true }, 2439 [tegra_clk_pclk] = { .dt_id = TEGRA210_CLK_PCLK, .present = true }, 2440 [tegra_clk_cclk_g] = { .dt_id = TEGRA210_CLK_CCLK_G, .present = true }, 2441 [tegra_clk_cclk_lp] = { .dt_id = TEGRA210_CLK_CCLK_LP, .present = true }, 2442 [tegra_clk_dfll_ref] = { .dt_id = TEGRA210_CLK_DFLL_REF, .present = true }, 2443 [tegra_clk_dfll_soc] = { .dt_id = TEGRA210_CLK_DFLL_SOC, .present = true }, 2444 [tegra_clk_vi_sensor2_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR2, .present = true }, 2445 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA210_CLK_PLL_P_OUT5, .present = true }, 2446 [tegra_clk_pll_c4] = { .dt_id = TEGRA210_CLK_PLL_C4, .present = true }, 2447 [tegra_clk_pll_dp] = { .dt_id = TEGRA210_CLK_PLL_DP, .present = true }, 2448 [tegra_clk_audio0_mux] = { .dt_id = TEGRA210_CLK_AUDIO0_MUX, .present = true }, 2449 [tegra_clk_audio1_mux] = { .dt_id = TEGRA210_CLK_AUDIO1_MUX, .present = true }, 2450 [tegra_clk_audio2_mux] = { .dt_id = TEGRA210_CLK_AUDIO2_MUX, .present = true }, 2451 [tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true }, 2452 [tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true }, 2453 [tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true }, 2454 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true }, 2455 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true }, 2456 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true }, 2457 [tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true }, 2458 [tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true }, 2459 [tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true }, 2460 [tegra_clk_sdmmc_legacy] = { .dt_id = TEGRA210_CLK_SDMMC_LEGACY, .present = true }, 2461 [tegra_clk_tsecb] = { .dt_id = TEGRA210_CLK_TSECB, .present = true }, 2462 [tegra_clk_uartape] = { .dt_id = TEGRA210_CLK_UARTAPE, .present = true }, 2463 [tegra_clk_vi_i2c] = { .dt_id = TEGRA210_CLK_VI_I2C, .present = true }, 2464 [tegra_clk_ape] = { .dt_id = TEGRA210_CLK_APE, .present = true }, 2465 [tegra_clk_dbgapb] = { .dt_id = TEGRA210_CLK_DBGAPB, .present = true }, 2466 [tegra_clk_nvdec] = { .dt_id = TEGRA210_CLK_NVDEC, .present = true }, 2467 [tegra_clk_nvenc] = { .dt_id = TEGRA210_CLK_NVENC, .present = true }, 2468 [tegra_clk_nvjpg] = { .dt_id = TEGRA210_CLK_NVJPG, .present = true }, 2469 [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true }, 2470 [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true }, 2471 [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true }, 2472 [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true }, 2473 [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true }, 2474 [tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true }, 2475 [tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true }, 2476 [tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true }, 2477 [tegra_clk_dmic1] = { .dt_id = TEGRA210_CLK_DMIC1, .present = true }, 2478 [tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true }, 2479 [tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true }, 2480 [tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true }, 2481 [tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true }, 2482 [tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true }, 2483 [tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true }, 2484 [tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true }, 2485 [tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true }, 2486 [tegra_clk_dp2] = { .dt_id = TEGRA210_CLK_DP2, .present = true }, 2487 [tegra_clk_iqc1] = { .dt_id = TEGRA210_CLK_IQC1, .present = true }, 2488 [tegra_clk_iqc2] = { .dt_id = TEGRA210_CLK_IQC2, .present = true }, 2489 [tegra_clk_pll_a_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT_ADSP, .present = true }, 2490 [tegra_clk_pll_a_out0_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP, .present = true }, 2491 [tegra_clk_adsp] = { .dt_id = TEGRA210_CLK_ADSP, .present = true }, 2492 [tegra_clk_adsp_neon] = { .dt_id = TEGRA210_CLK_ADSP_NEON, .present = true }, 2493 }; 2494 2495 static struct tegra_devclk devclks[] __initdata = { 2496 { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M }, 2497 { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF }, 2498 { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K }, 2499 { .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 }, 2500 { .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 }, 2501 { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C }, 2502 { .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 }, 2503 { .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 }, 2504 { .con_id = "pll_c3", .dt_id = TEGRA210_CLK_PLL_C3 }, 2505 { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P }, 2506 { .con_id = "pll_p_out1", .dt_id = TEGRA210_CLK_PLL_P_OUT1 }, 2507 { .con_id = "pll_p_out2", .dt_id = TEGRA210_CLK_PLL_P_OUT2 }, 2508 { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 }, 2509 { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 }, 2510 { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M }, 2511 { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X }, 2512 { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 }, 2513 { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U }, 2514 { .con_id = "pll_u_out", .dt_id = TEGRA210_CLK_PLL_U_OUT }, 2515 { .con_id = "pll_u_out1", .dt_id = TEGRA210_CLK_PLL_U_OUT1 }, 2516 { .con_id = "pll_u_out2", .dt_id = TEGRA210_CLK_PLL_U_OUT2 }, 2517 { .con_id = "pll_u_480M", .dt_id = TEGRA210_CLK_PLL_U_480M }, 2518 { .con_id = "pll_u_60M", .dt_id = TEGRA210_CLK_PLL_U_60M }, 2519 { .con_id = "pll_u_48M", .dt_id = TEGRA210_CLK_PLL_U_48M }, 2520 { .con_id = "pll_d", .dt_id = TEGRA210_CLK_PLL_D }, 2521 { .con_id = "pll_d_out0", .dt_id = TEGRA210_CLK_PLL_D_OUT0 }, 2522 { .con_id = "pll_d2", .dt_id = TEGRA210_CLK_PLL_D2 }, 2523 { .con_id = "pll_d2_out0", .dt_id = TEGRA210_CLK_PLL_D2_OUT0 }, 2524 { .con_id = "pll_a", .dt_id = TEGRA210_CLK_PLL_A }, 2525 { .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 }, 2526 { .con_id = "pll_re_vco", .dt_id = TEGRA210_CLK_PLL_RE_VCO }, 2527 { .con_id = "pll_re_out", .dt_id = TEGRA210_CLK_PLL_RE_OUT }, 2528 { .con_id = "spdif_in_sync", .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC }, 2529 { .con_id = "i2s0_sync", .dt_id = TEGRA210_CLK_I2S0_SYNC }, 2530 { .con_id = "i2s1_sync", .dt_id = TEGRA210_CLK_I2S1_SYNC }, 2531 { .con_id = "i2s2_sync", .dt_id = TEGRA210_CLK_I2S2_SYNC }, 2532 { .con_id = "i2s3_sync", .dt_id = TEGRA210_CLK_I2S3_SYNC }, 2533 { .con_id = "i2s4_sync", .dt_id = TEGRA210_CLK_I2S4_SYNC }, 2534 { .con_id = "vimclk_sync", .dt_id = TEGRA210_CLK_VIMCLK_SYNC }, 2535 { .con_id = "audio0", .dt_id = TEGRA210_CLK_AUDIO0 }, 2536 { .con_id = "audio1", .dt_id = TEGRA210_CLK_AUDIO1 }, 2537 { .con_id = "audio2", .dt_id = TEGRA210_CLK_AUDIO2 }, 2538 { .con_id = "audio3", .dt_id = TEGRA210_CLK_AUDIO3 }, 2539 { .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 }, 2540 { .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF }, 2541 { .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X }, 2542 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 }, 2543 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 }, 2544 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 }, 2545 { .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK }, 2546 { .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G }, 2547 { .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP }, 2548 { .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK }, 2549 { .con_id = "hclk", .dt_id = TEGRA210_CLK_HCLK }, 2550 { .con_id = "pclk", .dt_id = TEGRA210_CLK_PCLK }, 2551 { .con_id = "fuse", .dt_id = TEGRA210_CLK_FUSE }, 2552 { .dev_id = "rtc-tegra", .dt_id = TEGRA210_CLK_RTC }, 2553 { .dev_id = "timer", .dt_id = TEGRA210_CLK_TIMER }, 2554 { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 }, 2555 { .con_id = "pll_c4_out1", .dt_id = TEGRA210_CLK_PLL_C4_OUT1 }, 2556 { .con_id = "pll_c4_out2", .dt_id = TEGRA210_CLK_PLL_C4_OUT2 }, 2557 { .con_id = "pll_c4_out3", .dt_id = TEGRA210_CLK_PLL_C4_OUT3 }, 2558 { .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX }, 2559 { .con_id = "sor0", .dt_id = TEGRA210_CLK_SOR0 }, 2560 }; 2561 2562 static struct tegra_audio_clk_info tegra210_audio_plls[] = { 2563 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_ref" }, 2564 { "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" }, 2565 }; 2566 2567 static const char * const aclk_parents[] = { 2568 "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3", 2569 "clk_m" 2570 }; 2571 2572 static const unsigned int nvjpg_slcg_clkids[] = { TEGRA210_CLK_NVDEC }; 2573 static const unsigned int nvdec_slcg_clkids[] = { TEGRA210_CLK_NVJPG }; 2574 static const unsigned int sor_slcg_clkids[] = { TEGRA210_CLK_HDA2CODEC_2X, 2575 TEGRA210_CLK_HDA2HDMI, TEGRA210_CLK_DISP1, TEGRA210_CLK_DISP2 }; 2576 static const unsigned int disp_slcg_clkids[] = { TEGRA210_CLK_LA, 2577 TEGRA210_CLK_HOST1X}; 2578 static const unsigned int xusba_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST, 2579 TEGRA210_CLK_XUSB_DEV }; 2580 static const unsigned int xusbb_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST, 2581 TEGRA210_CLK_XUSB_SS }; 2582 static const unsigned int xusbc_slcg_clkids[] = { TEGRA210_CLK_XUSB_DEV, 2583 TEGRA210_CLK_XUSB_SS }; 2584 static const unsigned int venc_slcg_clkids[] = { TEGRA210_CLK_HOST1X, 2585 TEGRA210_CLK_PLL_D }; 2586 static const unsigned int ape_slcg_clkids[] = { TEGRA210_CLK_ACLK, 2587 TEGRA210_CLK_I2S0, TEGRA210_CLK_I2S1, TEGRA210_CLK_I2S2, 2588 TEGRA210_CLK_I2S3, TEGRA210_CLK_I2S4, TEGRA210_CLK_SPDIF_OUT, 2589 TEGRA210_CLK_D_AUDIO }; 2590 static const unsigned int vic_slcg_clkids[] = { TEGRA210_CLK_HOST1X }; 2591 2592 static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = { 2593 [TEGRA_POWERGATE_VENC] = { 2594 .handle_lvl2_ovr = tegra210_venc_mbist_war, 2595 .num_clks = ARRAY_SIZE(venc_slcg_clkids), 2596 .clk_init_data = venc_slcg_clkids, 2597 }, 2598 [TEGRA_POWERGATE_SATA] = { 2599 .handle_lvl2_ovr = tegra210_generic_mbist_war, 2600 .lvl2_offset = LVL2_CLK_GATE_OVRC, 2601 .lvl2_mask = BIT(0) | BIT(17) | BIT(19), 2602 }, 2603 [TEGRA_POWERGATE_MPE] = { 2604 .handle_lvl2_ovr = tegra210_generic_mbist_war, 2605 .lvl2_offset = LVL2_CLK_GATE_OVRE, 2606 .lvl2_mask = BIT(2), 2607 }, 2608 [TEGRA_POWERGATE_SOR] = { 2609 .handle_lvl2_ovr = tegra210_generic_mbist_war, 2610 .num_clks = ARRAY_SIZE(sor_slcg_clkids), 2611 .clk_init_data = sor_slcg_clkids, 2612 .lvl2_offset = LVL2_CLK_GATE_OVRA, 2613 .lvl2_mask = BIT(1) | BIT(2), 2614 }, 2615 [TEGRA_POWERGATE_DIS] = { 2616 .handle_lvl2_ovr = tegra210_disp_mbist_war, 2617 .num_clks = ARRAY_SIZE(disp_slcg_clkids), 2618 .clk_init_data = disp_slcg_clkids, 2619 }, 2620 [TEGRA_POWERGATE_DISB] = { 2621 .num_clks = ARRAY_SIZE(disp_slcg_clkids), 2622 .clk_init_data = disp_slcg_clkids, 2623 .handle_lvl2_ovr = tegra210_generic_mbist_war, 2624 .lvl2_offset = LVL2_CLK_GATE_OVRA, 2625 .lvl2_mask = BIT(2), 2626 }, 2627 [TEGRA_POWERGATE_XUSBA] = { 2628 .num_clks = ARRAY_SIZE(xusba_slcg_clkids), 2629 .clk_init_data = xusba_slcg_clkids, 2630 .handle_lvl2_ovr = tegra210_generic_mbist_war, 2631 .lvl2_offset = LVL2_CLK_GATE_OVRC, 2632 .lvl2_mask = BIT(30) | BIT(31), 2633 }, 2634 [TEGRA_POWERGATE_XUSBB] = { 2635 .num_clks = ARRAY_SIZE(xusbb_slcg_clkids), 2636 .clk_init_data = xusbb_slcg_clkids, 2637 .handle_lvl2_ovr = tegra210_generic_mbist_war, 2638 .lvl2_offset = LVL2_CLK_GATE_OVRC, 2639 .lvl2_mask = BIT(30) | BIT(31), 2640 }, 2641 [TEGRA_POWERGATE_XUSBC] = { 2642 .num_clks = ARRAY_SIZE(xusbc_slcg_clkids), 2643 .clk_init_data = xusbc_slcg_clkids, 2644 .handle_lvl2_ovr = tegra210_generic_mbist_war, 2645 .lvl2_offset = LVL2_CLK_GATE_OVRC, 2646 .lvl2_mask = BIT(30) | BIT(31), 2647 }, 2648 [TEGRA_POWERGATE_VIC] = { 2649 .num_clks = ARRAY_SIZE(vic_slcg_clkids), 2650 .clk_init_data = vic_slcg_clkids, 2651 .handle_lvl2_ovr = tegra210_vic_mbist_war, 2652 }, 2653 [TEGRA_POWERGATE_NVDEC] = { 2654 .num_clks = ARRAY_SIZE(nvdec_slcg_clkids), 2655 .clk_init_data = nvdec_slcg_clkids, 2656 .handle_lvl2_ovr = tegra210_generic_mbist_war, 2657 .lvl2_offset = LVL2_CLK_GATE_OVRC, 2658 .lvl2_mask = BIT(9) | BIT(31), 2659 }, 2660 [TEGRA_POWERGATE_NVJPG] = { 2661 .num_clks = ARRAY_SIZE(nvjpg_slcg_clkids), 2662 .clk_init_data = nvjpg_slcg_clkids, 2663 .handle_lvl2_ovr = tegra210_generic_mbist_war, 2664 .lvl2_offset = LVL2_CLK_GATE_OVRC, 2665 .lvl2_mask = BIT(9) | BIT(31), 2666 }, 2667 [TEGRA_POWERGATE_AUD] = { 2668 .num_clks = ARRAY_SIZE(ape_slcg_clkids), 2669 .clk_init_data = ape_slcg_clkids, 2670 .handle_lvl2_ovr = tegra210_ape_mbist_war, 2671 }, 2672 [TEGRA_POWERGATE_VE2] = { 2673 .handle_lvl2_ovr = tegra210_generic_mbist_war, 2674 .lvl2_offset = LVL2_CLK_GATE_OVRD, 2675 .lvl2_mask = BIT(22), 2676 }, 2677 }; 2678 2679 int tegra210_clk_handle_mbist_war(unsigned int id) 2680 { 2681 int err; 2682 struct tegra210_domain_mbist_war *mbist_war; 2683 2684 if (id >= ARRAY_SIZE(tegra210_pg_mbist_war)) { 2685 WARN(1, "unknown domain id in MBIST WAR handler\n"); 2686 return -EINVAL; 2687 } 2688 2689 mbist_war = &tegra210_pg_mbist_war[id]; 2690 if (!mbist_war->handle_lvl2_ovr) 2691 return 0; 2692 2693 if (mbist_war->num_clks && !mbist_war->clks) 2694 return -ENODEV; 2695 2696 err = clk_bulk_prepare_enable(mbist_war->num_clks, mbist_war->clks); 2697 if (err < 0) 2698 return err; 2699 2700 mutex_lock(&lvl2_ovr_lock); 2701 2702 mbist_war->handle_lvl2_ovr(mbist_war); 2703 2704 mutex_unlock(&lvl2_ovr_lock); 2705 2706 clk_bulk_disable_unprepare(mbist_war->num_clks, mbist_war->clks); 2707 2708 return 0; 2709 } 2710 2711 void tegra210_put_utmipll_in_iddq(void) 2712 { 2713 u32 reg; 2714 2715 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 2716 2717 if (reg & UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK) { 2718 pr_err("trying to assert IDDQ while UTMIPLL is locked\n"); 2719 return; 2720 } 2721 2722 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 2723 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 2724 } 2725 EXPORT_SYMBOL_GPL(tegra210_put_utmipll_in_iddq); 2726 2727 void tegra210_put_utmipll_out_iddq(void) 2728 { 2729 u32 reg; 2730 2731 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 2732 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 2733 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 2734 } 2735 EXPORT_SYMBOL_GPL(tegra210_put_utmipll_out_iddq); 2736 2737 static void tegra210_utmi_param_configure(void) 2738 { 2739 u32 reg; 2740 int i; 2741 2742 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 2743 if (osc_freq == utmi_parameters[i].osc_frequency) 2744 break; 2745 } 2746 2747 if (i >= ARRAY_SIZE(utmi_parameters)) { 2748 pr_err("%s: Unexpected oscillator freq %lu\n", __func__, 2749 osc_freq); 2750 return; 2751 } 2752 2753 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 2754 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 2755 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 2756 2757 udelay(10); 2758 2759 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 2760 2761 /* Program UTMIP PLL stable and active counts */ 2762 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ 2763 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 2764 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); 2765 2766 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 2767 reg |= 2768 UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count); 2769 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 2770 2771 /* Program UTMIP PLL delay and oscillator frequency counts */ 2772 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 2773 2774 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 2775 reg |= 2776 UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count); 2777 2778 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 2779 reg |= 2780 UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].xtal_freq_count); 2781 2782 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 2783 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 2784 2785 /* Remove power downs from UTMIP PLL control bits */ 2786 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 2787 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 2788 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 2789 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 2790 2791 udelay(20); 2792 2793 /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */ 2794 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 2795 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP; 2796 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP; 2797 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP; 2798 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 2799 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 2800 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN; 2801 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 2802 2803 /* Setup HW control of UTMIPLL */ 2804 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 2805 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 2806 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 2807 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 2808 2809 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 2810 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 2811 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 2812 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 2813 2814 udelay(1); 2815 2816 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); 2817 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY; 2818 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); 2819 2820 udelay(1); 2821 2822 /* Enable HW control UTMIPLL */ 2823 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 2824 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 2825 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 2826 } 2827 2828 static int tegra210_enable_pllu(void) 2829 { 2830 struct tegra_clk_pll_freq_table *fentry; 2831 struct tegra_clk_pll pllu; 2832 u32 reg; 2833 2834 for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) { 2835 if (fentry->input_rate == pll_ref_freq) 2836 break; 2837 } 2838 2839 if (!fentry->input_rate) { 2840 pr_err("Unknown PLL_U reference frequency %lu\n", pll_ref_freq); 2841 return -EINVAL; 2842 } 2843 2844 /* clear IDDQ bit */ 2845 pllu.params = &pll_u_vco_params; 2846 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); 2847 reg &= ~BIT(pllu.params->iddq_bit_idx); 2848 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); 2849 udelay(5); 2850 2851 reg = readl_relaxed(clk_base + PLLU_BASE); 2852 reg &= ~GENMASK(20, 0); 2853 reg |= fentry->m; 2854 reg |= fentry->n << 8; 2855 reg |= fentry->p << 16; 2856 writel(reg, clk_base + PLLU_BASE); 2857 udelay(1); 2858 reg |= PLL_ENABLE; 2859 writel(reg, clk_base + PLLU_BASE); 2860 2861 readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg, 2862 reg & PLL_BASE_LOCK, 2, 1000); 2863 if (!(reg & PLL_BASE_LOCK)) { 2864 pr_err("Timed out waiting for PLL_U to lock\n"); 2865 return -ETIMEDOUT; 2866 } 2867 2868 return 0; 2869 } 2870 2871 static int tegra210_init_pllu(void) 2872 { 2873 u32 reg; 2874 int err; 2875 2876 tegra210_pllu_set_defaults(&pll_u_vco_params); 2877 /* skip initialization when pllu is in hw controlled mode */ 2878 reg = readl_relaxed(clk_base + PLLU_BASE); 2879 if (reg & PLLU_BASE_OVERRIDE) { 2880 if (!(reg & PLL_ENABLE)) { 2881 err = tegra210_enable_pllu(); 2882 if (err < 0) { 2883 WARN_ON(1); 2884 return err; 2885 } 2886 } 2887 /* enable hw controlled mode */ 2888 reg = readl_relaxed(clk_base + PLLU_BASE); 2889 reg &= ~PLLU_BASE_OVERRIDE; 2890 writel(reg, clk_base + PLLU_BASE); 2891 2892 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); 2893 reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE | 2894 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT | 2895 PLLU_HW_PWRDN_CFG0_USE_LOCKDET; 2896 reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL | 2897 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL); 2898 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); 2899 2900 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); 2901 reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK; 2902 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); 2903 udelay(1); 2904 2905 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); 2906 reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE; 2907 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); 2908 udelay(1); 2909 2910 reg = readl_relaxed(clk_base + PLLU_BASE); 2911 reg &= ~PLLU_BASE_CLKENABLE_USB; 2912 writel_relaxed(reg, clk_base + PLLU_BASE); 2913 } 2914 2915 /* enable UTMIPLL hw control if not yet done by the bootloader */ 2916 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 2917 if (!(reg & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE)) 2918 tegra210_utmi_param_configure(); 2919 2920 return 0; 2921 } 2922 2923 static const char * const sor1_out_parents[] = { 2924 /* 2925 * Bit 0 of the mux selects sor1_pad_clkout, irrespective of bit 1, so 2926 * the sor1_pad_clkout parent appears twice in the list below. This is 2927 * merely to support clk_get_parent() if firmware happened to set 2928 * these bits to 0b11. While not an invalid setting, code should 2929 * always set the bits to 0b01 to select sor1_pad_clkout. 2930 */ 2931 "sor_safe", "sor1_pad_clkout", "sor1", "sor1_pad_clkout", 2932 }; 2933 2934 static const char * const sor1_parents[] = { 2935 "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m", 2936 }; 2937 2938 static u32 sor1_parents_idx[] = { 0, 2, 5, 6 }; 2939 2940 static struct tegra_periph_init_data tegra210_periph[] = { 2941 TEGRA_INIT_DATA_TABLE("sor1", NULL, NULL, sor1_parents, 2942 CLK_SOURCE_SOR1, 29, 0x7, 0, 0, 8, 1, 2943 TEGRA_DIVIDER_ROUND_UP, 183, 0, tegra_clk_sor1, 2944 sor1_parents_idx, 0, &sor1_lock), 2945 }; 2946 2947 static const char * const la_parents[] = { 2948 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_re_out1", "pll_a1", "clk_m", "pll_c4_out0" 2949 }; 2950 2951 static struct tegra_clk_periph tegra210_la = 2952 TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, 0); 2953 2954 static __init void tegra210_periph_clk_init(void __iomem *clk_base, 2955 void __iomem *pmc_base) 2956 { 2957 struct clk *clk; 2958 unsigned int i; 2959 2960 /* xusb_ss_div2 */ 2961 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, 2962 1, 2); 2963 clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; 2964 2965 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base, 2966 1, 17, 222); 2967 clks[TEGRA210_CLK_SOR_SAFE] = clk; 2968 2969 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, 2970 1, 17, 181); 2971 clks[TEGRA210_CLK_DPAUX] = clk; 2972 2973 clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base, 2974 1, 17, 207); 2975 clks[TEGRA210_CLK_DPAUX1] = clk; 2976 2977 clk = clk_register_mux_table(NULL, "sor1_out", sor1_out_parents, 2978 ARRAY_SIZE(sor1_out_parents), 0, 2979 clk_base + CLK_SOURCE_SOR1, 14, 0x3, 2980 0, NULL, &sor1_lock); 2981 clks[TEGRA210_CLK_SOR1_OUT] = clk; 2982 2983 /* pll_d_dsi_out */ 2984 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, 2985 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock); 2986 clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk; 2987 2988 /* dsia */ 2989 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0, 2990 clk_base, 0, 48, 2991 periph_clk_enb_refcnt); 2992 clks[TEGRA210_CLK_DSIA] = clk; 2993 2994 /* dsib */ 2995 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, 2996 clk_base, 0, 82, 2997 periph_clk_enb_refcnt); 2998 clks[TEGRA210_CLK_DSIB] = clk; 2999 3000 /* la */ 3001 clk = tegra_clk_register_periph("la", la_parents, 3002 ARRAY_SIZE(la_parents), &tegra210_la, clk_base, 3003 CLK_SOURCE_LA, 0); 3004 clks[TEGRA210_CLK_LA] = clk; 3005 3006 /* emc mux */ 3007 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 3008 ARRAY_SIZE(mux_pllmcp_clkm), 0, 3009 clk_base + CLK_SOURCE_EMC, 3010 29, 3, 0, &emc_lock); 3011 3012 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, 3013 &emc_lock); 3014 clks[TEGRA210_CLK_MC] = clk; 3015 3016 /* cml0 */ 3017 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, 3018 0, 0, &pll_e_lock); 3019 clk_register_clkdev(clk, "cml0", NULL); 3020 clks[TEGRA210_CLK_CML0] = clk; 3021 3022 /* cml1 */ 3023 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, 3024 1, 0, &pll_e_lock); 3025 clk_register_clkdev(clk, "cml1", NULL); 3026 clks[TEGRA210_CLK_CML1] = clk; 3027 3028 clk = tegra_clk_register_super_clk("aclk", aclk_parents, 3029 ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0, 3030 0, NULL); 3031 clks[TEGRA210_CLK_ACLK] = clk; 3032 3033 for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) { 3034 struct tegra_periph_init_data *init = &tegra210_periph[i]; 3035 struct clk **clkp; 3036 3037 clkp = tegra_lookup_dt_id(init->clk_id, tegra210_clks); 3038 if (!clkp) { 3039 pr_warn("clock %u not found\n", init->clk_id); 3040 continue; 3041 } 3042 3043 clk = tegra_clk_register_periph_data(clk_base, init); 3044 *clkp = clk; 3045 } 3046 3047 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params); 3048 } 3049 3050 static void __init tegra210_pll_init(void __iomem *clk_base, 3051 void __iomem *pmc) 3052 { 3053 struct clk *clk; 3054 3055 /* PLLC */ 3056 clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base, 3057 pmc, 0, &pll_c_params, NULL); 3058 if (!WARN_ON(IS_ERR(clk))) 3059 clk_register_clkdev(clk, "pll_c", NULL); 3060 clks[TEGRA210_CLK_PLL_C] = clk; 3061 3062 /* PLLC_OUT1 */ 3063 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 3064 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 3065 8, 8, 1, NULL); 3066 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 3067 clk_base + PLLC_OUT, 1, 0, 3068 CLK_SET_RATE_PARENT, 0, NULL); 3069 clk_register_clkdev(clk, "pll_c_out1", NULL); 3070 clks[TEGRA210_CLK_PLL_C_OUT1] = clk; 3071 3072 /* PLLC_UD */ 3073 clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c", 3074 CLK_SET_RATE_PARENT, 1, 1); 3075 clk_register_clkdev(clk, "pll_c_ud", NULL); 3076 clks[TEGRA210_CLK_PLL_C_UD] = clk; 3077 3078 /* PLLC2 */ 3079 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base, 3080 pmc, 0, &pll_c2_params, NULL); 3081 clk_register_clkdev(clk, "pll_c2", NULL); 3082 clks[TEGRA210_CLK_PLL_C2] = clk; 3083 3084 /* PLLC3 */ 3085 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base, 3086 pmc, 0, &pll_c3_params, NULL); 3087 clk_register_clkdev(clk, "pll_c3", NULL); 3088 clks[TEGRA210_CLK_PLL_C3] = clk; 3089 3090 /* PLLM */ 3091 clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc, 3092 CLK_SET_RATE_GATE, &pll_m_params, NULL); 3093 clk_register_clkdev(clk, "pll_m", NULL); 3094 clks[TEGRA210_CLK_PLL_M] = clk; 3095 3096 /* PLLMB */ 3097 clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc, 3098 CLK_SET_RATE_GATE, &pll_mb_params, NULL); 3099 clk_register_clkdev(clk, "pll_mb", NULL); 3100 clks[TEGRA210_CLK_PLL_MB] = clk; 3101 3102 /* PLLM_UD */ 3103 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 3104 CLK_SET_RATE_PARENT, 1, 1); 3105 clk_register_clkdev(clk, "pll_m_ud", NULL); 3106 clks[TEGRA210_CLK_PLL_M_UD] = clk; 3107 3108 /* PLLU_VCO */ 3109 if (!tegra210_init_pllu()) { 3110 clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0, 3111 480*1000*1000); 3112 clk_register_clkdev(clk, "pll_u_vco", NULL); 3113 clks[TEGRA210_CLK_PLL_U] = clk; 3114 } 3115 3116 /* PLLU_OUT */ 3117 clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0, 3118 clk_base + PLLU_BASE, 16, 4, 0, 3119 pll_vco_post_div_table, NULL); 3120 clk_register_clkdev(clk, "pll_u_out", NULL); 3121 clks[TEGRA210_CLK_PLL_U_OUT] = clk; 3122 3123 /* PLLU_OUT1 */ 3124 clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out", 3125 clk_base + PLLU_OUTA, 0, 3126 TEGRA_DIVIDER_ROUND_UP, 3127 8, 8, 1, &pll_u_lock); 3128 clk = tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div", 3129 clk_base + PLLU_OUTA, 1, 0, 3130 CLK_SET_RATE_PARENT, 0, &pll_u_lock); 3131 clk_register_clkdev(clk, "pll_u_out1", NULL); 3132 clks[TEGRA210_CLK_PLL_U_OUT1] = clk; 3133 3134 /* PLLU_OUT2 */ 3135 clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out", 3136 clk_base + PLLU_OUTA, 0, 3137 TEGRA_DIVIDER_ROUND_UP, 3138 24, 8, 1, &pll_u_lock); 3139 clk = tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div", 3140 clk_base + PLLU_OUTA, 17, 16, 3141 CLK_SET_RATE_PARENT, 0, &pll_u_lock); 3142 clk_register_clkdev(clk, "pll_u_out2", NULL); 3143 clks[TEGRA210_CLK_PLL_U_OUT2] = clk; 3144 3145 /* PLLU_480M */ 3146 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco", 3147 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 3148 22, 0, &pll_u_lock); 3149 clk_register_clkdev(clk, "pll_u_480M", NULL); 3150 clks[TEGRA210_CLK_PLL_U_480M] = clk; 3151 3152 /* PLLU_60M */ 3153 clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2", 3154 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 3155 23, 0, &pll_u_lock); 3156 clk_register_clkdev(clk, "pll_u_60M", NULL); 3157 clks[TEGRA210_CLK_PLL_U_60M] = clk; 3158 3159 /* PLLU_48M */ 3160 clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1", 3161 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 3162 25, 0, &pll_u_lock); 3163 clk_register_clkdev(clk, "pll_u_48M", NULL); 3164 clks[TEGRA210_CLK_PLL_U_48M] = clk; 3165 3166 /* PLLD */ 3167 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, 3168 &pll_d_params, &pll_d_lock); 3169 clk_register_clkdev(clk, "pll_d", NULL); 3170 clks[TEGRA210_CLK_PLL_D] = clk; 3171 3172 /* PLLD_OUT0 */ 3173 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 3174 CLK_SET_RATE_PARENT, 1, 2); 3175 clk_register_clkdev(clk, "pll_d_out0", NULL); 3176 clks[TEGRA210_CLK_PLL_D_OUT0] = clk; 3177 3178 /* PLLRE */ 3179 clk = tegra_clk_register_pllre_tegra210("pll_re_vco", "pll_ref", 3180 clk_base, pmc, 0, 3181 &pll_re_vco_params, 3182 &pll_re_lock, pll_ref_freq); 3183 clk_register_clkdev(clk, "pll_re_vco", NULL); 3184 clks[TEGRA210_CLK_PLL_RE_VCO] = clk; 3185 3186 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, 3187 clk_base + PLLRE_BASE, 16, 5, 0, 3188 pll_vco_post_div_table, &pll_re_lock); 3189 clk_register_clkdev(clk, "pll_re_out", NULL); 3190 clks[TEGRA210_CLK_PLL_RE_OUT] = clk; 3191 3192 clk = tegra_clk_register_divider("pll_re_out1_div", "pll_re_vco", 3193 clk_base + PLLRE_OUT1, 0, 3194 TEGRA_DIVIDER_ROUND_UP, 3195 8, 8, 1, NULL); 3196 clk = tegra_clk_register_pll_out("pll_re_out1", "pll_re_out1_div", 3197 clk_base + PLLRE_OUT1, 1, 0, 3198 CLK_SET_RATE_PARENT, 0, NULL); 3199 clks[TEGRA210_CLK_PLL_RE_OUT1] = clk; 3200 3201 /* PLLE */ 3202 clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref", 3203 clk_base, 0, &pll_e_params, NULL); 3204 clk_register_clkdev(clk, "pll_e", NULL); 3205 clks[TEGRA210_CLK_PLL_E] = clk; 3206 3207 /* PLLC4 */ 3208 clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc, 3209 0, &pll_c4_vco_params, NULL, pll_ref_freq); 3210 clk_register_clkdev(clk, "pll_c4_vco", NULL); 3211 clks[TEGRA210_CLK_PLL_C4] = clk; 3212 3213 /* PLLC4_OUT0 */ 3214 clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0, 3215 clk_base + PLLC4_BASE, 19, 4, 0, 3216 pll_vco_post_div_table, NULL); 3217 clk_register_clkdev(clk, "pll_c4_out0", NULL); 3218 clks[TEGRA210_CLK_PLL_C4_OUT0] = clk; 3219 3220 /* PLLC4_OUT1 */ 3221 clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco", 3222 CLK_SET_RATE_PARENT, 1, 3); 3223 clk_register_clkdev(clk, "pll_c4_out1", NULL); 3224 clks[TEGRA210_CLK_PLL_C4_OUT1] = clk; 3225 3226 /* PLLC4_OUT2 */ 3227 clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco", 3228 CLK_SET_RATE_PARENT, 1, 5); 3229 clk_register_clkdev(clk, "pll_c4_out2", NULL); 3230 clks[TEGRA210_CLK_PLL_C4_OUT2] = clk; 3231 3232 /* PLLC4_OUT3 */ 3233 clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0", 3234 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 3235 8, 8, 1, NULL); 3236 clk = tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div", 3237 clk_base + PLLC4_OUT, 1, 0, 3238 CLK_SET_RATE_PARENT, 0, NULL); 3239 clk_register_clkdev(clk, "pll_c4_out3", NULL); 3240 clks[TEGRA210_CLK_PLL_C4_OUT3] = clk; 3241 3242 /* PLLDP */ 3243 clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base, 3244 0, &pll_dp_params, NULL); 3245 clk_register_clkdev(clk, "pll_dp", NULL); 3246 clks[TEGRA210_CLK_PLL_DP] = clk; 3247 3248 /* PLLD2 */ 3249 clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base, 3250 0, &pll_d2_params, NULL); 3251 clk_register_clkdev(clk, "pll_d2", NULL); 3252 clks[TEGRA210_CLK_PLL_D2] = clk; 3253 3254 /* PLLD2_OUT0 */ 3255 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 3256 CLK_SET_RATE_PARENT, 1, 1); 3257 clk_register_clkdev(clk, "pll_d2_out0", NULL); 3258 clks[TEGRA210_CLK_PLL_D2_OUT0] = clk; 3259 3260 /* PLLP_OUT2 */ 3261 clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p", 3262 CLK_SET_RATE_PARENT, 1, 2); 3263 clk_register_clkdev(clk, "pll_p_out2", NULL); 3264 clks[TEGRA210_CLK_PLL_P_OUT2] = clk; 3265 3266 } 3267 3268 /* Tegra210 CPU clock and reset control functions */ 3269 static void tegra210_wait_cpu_in_reset(u32 cpu) 3270 { 3271 unsigned int reg; 3272 3273 do { 3274 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 3275 cpu_relax(); 3276 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 3277 } 3278 3279 static void tegra210_disable_cpu_clock(u32 cpu) 3280 { 3281 /* flow controller would take care in the power sequence. */ 3282 } 3283 3284 #ifdef CONFIG_PM_SLEEP 3285 static void tegra210_cpu_clock_suspend(void) 3286 { 3287 /* switch coresite to clk_m, save off original source */ 3288 tegra210_cpu_clk_sctx.clk_csite_src = 3289 readl(clk_base + CLK_SOURCE_CSITE); 3290 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); 3291 } 3292 3293 static void tegra210_cpu_clock_resume(void) 3294 { 3295 writel(tegra210_cpu_clk_sctx.clk_csite_src, 3296 clk_base + CLK_SOURCE_CSITE); 3297 } 3298 #endif 3299 3300 static struct tegra_cpu_car_ops tegra210_cpu_car_ops = { 3301 .wait_for_reset = tegra210_wait_cpu_in_reset, 3302 .disable_clock = tegra210_disable_cpu_clock, 3303 #ifdef CONFIG_PM_SLEEP 3304 .suspend = tegra210_cpu_clock_suspend, 3305 .resume = tegra210_cpu_clock_resume, 3306 #endif 3307 }; 3308 3309 static const struct of_device_id pmc_match[] __initconst = { 3310 { .compatible = "nvidia,tegra210-pmc" }, 3311 { }, 3312 }; 3313 3314 static struct tegra_clk_init_table init_table[] __initdata = { 3315 { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 }, 3316 { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 }, 3317 { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 }, 3318 { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 }, 3319 { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 }, 3320 { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 }, 3321 { TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 }, 3322 { TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 }, 3323 { TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 }, 3324 { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, 3325 { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, 3326 { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, 3327 { TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, 3328 { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 }, 3329 { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 }, 3330 { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 }, 3331 { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 0 }, 3332 { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 }, 3333 { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 }, 3334 { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 }, 3335 { TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 }, 3336 { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 }, 3337 { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 }, 3338 { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 }, 3339 { TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 }, 3340 { TEGRA210_CLK_XUSB_SSP_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 }, 3341 { TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 204000000, 0 }, 3342 { TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 }, 3343 { TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 }, 3344 { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 }, 3345 { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 }, 3346 { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 }, 3347 { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 }, 3348 /* TODO find a way to enable this on-demand */ 3349 { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 }, 3350 { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 }, 3351 { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 }, 3352 { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 }, 3353 { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 }, 3354 { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 }, 3355 { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 }, 3356 { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 }, 3357 { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 }, 3358 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 }, 3359 { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 }, 3360 { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 }, 3361 { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 }, 3362 /* This MUST be the last entry. */ 3363 { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 }, 3364 }; 3365 3366 /** 3367 * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs 3368 * 3369 * Program an initial clock rate and enable or disable clocks needed 3370 * by the rest of the kernel, for Tegra210 SoCs. It is intended to be 3371 * called by assigning a pointer to it to tegra_clk_apply_init_table - 3372 * this will be called as an arch_initcall. No return value. 3373 */ 3374 static void __init tegra210_clock_apply_init_table(void) 3375 { 3376 tegra_init_from_table(init_table, clks, TEGRA210_CLK_CLK_MAX); 3377 } 3378 3379 /** 3380 * tegra210_car_barrier - wait for pending writes to the CAR to complete 3381 * 3382 * Wait for any outstanding writes to the CAR MMIO space from this CPU 3383 * to complete before continuing execution. No return value. 3384 */ 3385 static void tegra210_car_barrier(void) 3386 { 3387 readl_relaxed(clk_base + RST_DFLL_DVCO); 3388 } 3389 3390 /** 3391 * tegra210_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset 3392 * 3393 * Assert the reset line of the DFLL's DVCO. No return value. 3394 */ 3395 static void tegra210_clock_assert_dfll_dvco_reset(void) 3396 { 3397 u32 v; 3398 3399 v = readl_relaxed(clk_base + RST_DFLL_DVCO); 3400 v |= (1 << DVFS_DFLL_RESET_SHIFT); 3401 writel_relaxed(v, clk_base + RST_DFLL_DVCO); 3402 tegra210_car_barrier(); 3403 } 3404 3405 /** 3406 * tegra210_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset 3407 * 3408 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to 3409 * operate. No return value. 3410 */ 3411 static void tegra210_clock_deassert_dfll_dvco_reset(void) 3412 { 3413 u32 v; 3414 3415 v = readl_relaxed(clk_base + RST_DFLL_DVCO); 3416 v &= ~(1 << DVFS_DFLL_RESET_SHIFT); 3417 writel_relaxed(v, clk_base + RST_DFLL_DVCO); 3418 tegra210_car_barrier(); 3419 } 3420 3421 static int tegra210_reset_assert(unsigned long id) 3422 { 3423 if (id == TEGRA210_RST_DFLL_DVCO) 3424 tegra210_clock_assert_dfll_dvco_reset(); 3425 else if (id == TEGRA210_RST_ADSP) 3426 writel(GENMASK(26, 21) | BIT(7), 3427 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET); 3428 else 3429 return -EINVAL; 3430 3431 return 0; 3432 } 3433 3434 static int tegra210_reset_deassert(unsigned long id) 3435 { 3436 if (id == TEGRA210_RST_DFLL_DVCO) 3437 tegra210_clock_deassert_dfll_dvco_reset(); 3438 else if (id == TEGRA210_RST_ADSP) { 3439 writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); 3440 /* 3441 * Considering adsp cpu clock (min: 12.5MHZ, max: 1GHz) 3442 * a delay of 5us ensures that it's at least 3443 * 6 * adsp_cpu_cycle_period long. 3444 */ 3445 udelay(5); 3446 writel(GENMASK(26, 22) | BIT(7), 3447 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); 3448 } else 3449 return -EINVAL; 3450 3451 return 0; 3452 } 3453 3454 static void tegra210_mbist_clk_init(void) 3455 { 3456 unsigned int i, j; 3457 3458 for (i = 0; i < ARRAY_SIZE(tegra210_pg_mbist_war); i++) { 3459 unsigned int num_clks = tegra210_pg_mbist_war[i].num_clks; 3460 struct clk_bulk_data *clk_data; 3461 3462 if (!num_clks) 3463 continue; 3464 3465 clk_data = kmalloc_array(num_clks, sizeof(*clk_data), 3466 GFP_KERNEL); 3467 if (WARN_ON(!clk_data)) 3468 return; 3469 3470 tegra210_pg_mbist_war[i].clks = clk_data; 3471 for (j = 0; j < num_clks; j++) { 3472 int clk_id = tegra210_pg_mbist_war[i].clk_init_data[j]; 3473 struct clk *clk = clks[clk_id]; 3474 3475 if (WARN(IS_ERR(clk), "clk_id: %d\n", clk_id)) { 3476 kfree(clk_data); 3477 tegra210_pg_mbist_war[i].clks = NULL; 3478 break; 3479 } 3480 clk_data[j].clk = clk; 3481 } 3482 } 3483 } 3484 3485 /** 3486 * tegra210_clock_init - Tegra210-specific clock initialization 3487 * @np: struct device_node * of the DT node for the SoC CAR IP block 3488 * 3489 * Register most SoC clocks for the Tegra210 system-on-chip. Intended 3490 * to be called by the OF init code when a DT node with the 3491 * "nvidia,tegra210-car" string is encountered, and declared with 3492 * CLK_OF_DECLARE. No return value. 3493 */ 3494 static void __init tegra210_clock_init(struct device_node *np) 3495 { 3496 struct device_node *node; 3497 u32 value, clk_m_div; 3498 3499 clk_base = of_iomap(np, 0); 3500 if (!clk_base) { 3501 pr_err("ioremap tegra210 CAR failed\n"); 3502 return; 3503 } 3504 3505 node = of_find_matching_node(NULL, pmc_match); 3506 if (!node) { 3507 pr_err("Failed to find pmc node\n"); 3508 WARN_ON(1); 3509 return; 3510 } 3511 3512 pmc_base = of_iomap(node, 0); 3513 if (!pmc_base) { 3514 pr_err("Can't map pmc registers\n"); 3515 WARN_ON(1); 3516 return; 3517 } 3518 3519 ahub_base = ioremap(TEGRA210_AHUB_BASE, SZ_64K); 3520 if (!ahub_base) { 3521 pr_err("ioremap tegra210 APE failed\n"); 3522 return; 3523 } 3524 3525 dispa_base = ioremap(TEGRA210_DISPA_BASE, SZ_256K); 3526 if (!dispa_base) { 3527 pr_err("ioremap tegra210 DISPA failed\n"); 3528 return; 3529 } 3530 3531 vic_base = ioremap(TEGRA210_VIC_BASE, SZ_256K); 3532 if (!vic_base) { 3533 pr_err("ioremap tegra210 VIC failed\n"); 3534 return; 3535 } 3536 3537 clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX, 3538 TEGRA210_CAR_BANK_COUNT); 3539 if (!clks) 3540 return; 3541 3542 value = clk_readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT; 3543 clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1; 3544 3545 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq, 3546 ARRAY_SIZE(tegra210_input_freq), clk_m_div, 3547 &osc_freq, &pll_ref_freq) < 0) 3548 return; 3549 3550 tegra_fixed_clk_init(tegra210_clks); 3551 tegra210_pll_init(clk_base, pmc_base); 3552 tegra210_periph_clk_init(clk_base, pmc_base); 3553 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks, 3554 tegra210_audio_plls, 3555 ARRAY_SIZE(tegra210_audio_plls)); 3556 tegra_pmc_clk_init(pmc_base, tegra210_clks); 3557 3558 /* For Tegra210, PLLD is the only source for DSIA & DSIB */ 3559 value = clk_readl(clk_base + PLLD_BASE); 3560 value &= ~BIT(25); 3561 clk_writel(value, clk_base + PLLD_BASE); 3562 3563 tegra_clk_apply_init_table = tegra210_clock_apply_init_table; 3564 3565 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks, 3566 &pll_x_params); 3567 tegra_init_special_resets(2, tegra210_reset_assert, 3568 tegra210_reset_deassert); 3569 3570 tegra_add_of_provider(np, of_clk_src_onecell_get); 3571 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 3572 3573 tegra210_mbist_clk_init(); 3574 3575 tegra_cpu_car_ops = &tegra210_cpu_car_ops; 3576 } 3577 CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init); 3578