1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/clk/tegra.h> 10 #include <linux/device.h> 11 #include <linux/module.h> 12 #include <linux/io.h> 13 #include <linux/slab.h> 14 15 #include "clk.h" 16 17 #define CLK_SOURCE_EMC 0x19c 18 #define CLK_SOURCE_EMC_2X_CLK_SRC GENMASK(31, 29) 19 #define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ BIT(16) 20 #define CLK_SOURCE_EMC_2X_CLK_DIVISOR GENMASK(7, 0) 21 22 #define CLK_SRC_PLLM 0 23 #define CLK_SRC_PLLC 1 24 #define CLK_SRC_PLLP 2 25 #define CLK_SRC_CLK_M 3 26 #define CLK_SRC_PLLM_UD 4 27 #define CLK_SRC_PLLMB_UD 5 28 #define CLK_SRC_PLLMB 6 29 #define CLK_SRC_PLLP_UD 7 30 31 struct tegra210_clk_emc { 32 struct clk_hw hw; 33 void __iomem *regs; 34 35 struct tegra210_clk_emc_provider *provider; 36 37 struct clk *parents[8]; 38 }; 39 40 static inline struct tegra210_clk_emc * 41 to_tegra210_clk_emc(struct clk_hw *hw) 42 { 43 return container_of(hw, struct tegra210_clk_emc, hw); 44 } 45 46 static const char *tegra210_clk_emc_parents[] = { 47 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb_ud", 48 "pll_mb", "pll_p_ud", 49 }; 50 51 static u8 tegra210_clk_emc_get_parent(struct clk_hw *hw) 52 { 53 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); 54 u32 value; 55 u8 src; 56 57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); 58 src = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_SRC, value); 59 60 return src; 61 } 62 63 static unsigned long tegra210_clk_emc_recalc_rate(struct clk_hw *hw, 64 unsigned long parent_rate) 65 { 66 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); 67 u32 value, div; 68 69 /* 70 * CCF assumes that neither the parent nor its rate will change during 71 * ->set_rate(), so the parent rate passed in here was cached from the 72 * parent before the ->set_rate() call. 73 * 74 * This can lead to wrong results being reported for the EMC clock if 75 * the parent and/or parent rate have changed as part of the EMC rate 76 * change sequence. Fix this by overriding the parent clock with what 77 * we know to be the correct value after the rate change. 78 */ 79 parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); 80 81 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); 82 83 div = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_DIVISOR, value); 84 div += 2; 85 86 return DIV_ROUND_UP(parent_rate * 2, div); 87 } 88 89 static int tegra210_clk_emc_determine_rate(struct clk_hw *hw, 90 struct clk_rate_request *req) 91 { 92 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); 93 struct tegra210_clk_emc_provider *provider = emc->provider; 94 unsigned int i; 95 96 if (!provider || !provider->configs || provider->num_configs == 0) { 97 req->rate = clk_hw_get_rate(hw); 98 99 return 0; 100 } 101 102 for (i = 0; i < provider->num_configs; i++) { 103 if (provider->configs[i].rate >= req->rate) { 104 req->rate = provider->configs[i].rate; 105 106 return 0; 107 } 108 } 109 110 req->rate = provider->configs[i - 1].rate; 111 112 return 0; 113 } 114 115 static struct clk *tegra210_clk_emc_find_parent(struct tegra210_clk_emc *emc, 116 u8 index) 117 { 118 struct clk_hw *parent = clk_hw_get_parent_by_index(&emc->hw, index); 119 const char *name = clk_hw_get_name(parent); 120 121 /* XXX implement cache? */ 122 123 return __clk_lookup(name); 124 } 125 126 static int tegra210_clk_emc_set_rate(struct clk_hw *hw, unsigned long rate, 127 unsigned long parent_rate) 128 { 129 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); 130 struct tegra210_clk_emc_provider *provider = emc->provider; 131 struct tegra210_clk_emc_config *config; 132 struct device *dev = provider->dev; 133 struct clk_hw *old, *new, *parent; 134 u8 old_idx, new_idx, index; 135 struct clk *clk; 136 unsigned int i; 137 int err; 138 139 if (!provider->configs || provider->num_configs == 0) 140 return -EINVAL; 141 142 for (i = 0; i < provider->num_configs; i++) { 143 if (provider->configs[i].rate >= rate) { 144 config = &provider->configs[i]; 145 break; 146 } 147 } 148 149 if (i == provider->num_configs) 150 config = &provider->configs[i - 1]; 151 152 old_idx = tegra210_clk_emc_get_parent(hw); 153 new_idx = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_SRC, config->value); 154 155 old = clk_hw_get_parent_by_index(hw, old_idx); 156 new = clk_hw_get_parent_by_index(hw, new_idx); 157 158 /* if the rate has changed... */ 159 if (config->parent_rate != clk_hw_get_rate(old)) { 160 /* ... but the clock source remains the same ... */ 161 if (new_idx == old_idx) { 162 /* ... switch to the alternative clock source. */ 163 switch (new_idx) { 164 case CLK_SRC_PLLM: 165 new_idx = CLK_SRC_PLLMB; 166 break; 167 168 case CLK_SRC_PLLM_UD: 169 new_idx = CLK_SRC_PLLMB_UD; 170 break; 171 172 case CLK_SRC_PLLMB_UD: 173 new_idx = CLK_SRC_PLLM_UD; 174 break; 175 176 case CLK_SRC_PLLMB: 177 new_idx = CLK_SRC_PLLM; 178 break; 179 } 180 181 /* 182 * This should never happen because we can't deal with 183 * it. 184 */ 185 if (WARN_ON(new_idx == old_idx)) 186 return -EINVAL; 187 188 new = clk_hw_get_parent_by_index(hw, new_idx); 189 } 190 191 index = new_idx; 192 parent = new; 193 } else { 194 index = old_idx; 195 parent = old; 196 } 197 198 clk = tegra210_clk_emc_find_parent(emc, index); 199 if (IS_ERR(clk)) { 200 err = PTR_ERR(clk); 201 dev_err(dev, "failed to get parent clock for index %u: %d\n", 202 index, err); 203 return err; 204 } 205 206 /* set the new parent clock to the required rate */ 207 if (clk_get_rate(clk) != config->parent_rate) { 208 err = clk_set_rate(clk, config->parent_rate); 209 if (err < 0) { 210 dev_err(dev, "failed to set rate %lu Hz for %pC: %d\n", 211 config->parent_rate, clk, err); 212 return err; 213 } 214 } 215 216 /* enable the new parent clock */ 217 if (parent != old) { 218 err = clk_prepare_enable(clk); 219 if (err < 0) { 220 dev_err(dev, "failed to enable parent clock %pC: %d\n", 221 clk, err); 222 return err; 223 } 224 } 225 226 /* update the EMC source configuration to reflect the new parent */ 227 config->value &= ~CLK_SOURCE_EMC_2X_CLK_SRC; 228 config->value |= FIELD_PREP(CLK_SOURCE_EMC_2X_CLK_SRC, index); 229 230 /* 231 * Finally, switch the EMC programming with both old and new parent 232 * clocks enabled. 233 */ 234 err = provider->set_rate(dev, config); 235 if (err < 0) { 236 dev_err(dev, "failed to set EMC rate to %lu Hz: %d\n", rate, 237 err); 238 239 /* 240 * If we're unable to switch to the new EMC frequency, we no 241 * longer need the new parent to be enabled. 242 */ 243 if (parent != old) 244 clk_disable_unprepare(clk); 245 246 return err; 247 } 248 249 /* reparent to new parent clock and disable the old parent clock */ 250 if (parent != old) { 251 clk = tegra210_clk_emc_find_parent(emc, old_idx); 252 if (IS_ERR(clk)) { 253 err = PTR_ERR(clk); 254 dev_err(dev, 255 "failed to get parent clock for index %u: %d\n", 256 old_idx, err); 257 return err; 258 } 259 260 clk_hw_reparent(hw, parent); 261 clk_disable_unprepare(clk); 262 } 263 264 return err; 265 } 266 267 static const struct clk_ops tegra210_clk_emc_ops = { 268 .get_parent = tegra210_clk_emc_get_parent, 269 .recalc_rate = tegra210_clk_emc_recalc_rate, 270 .determine_rate = tegra210_clk_emc_determine_rate, 271 .set_rate = tegra210_clk_emc_set_rate, 272 }; 273 274 struct clk *tegra210_clk_register_emc(struct device_node *np, 275 void __iomem *regs) 276 { 277 struct tegra210_clk_emc *emc; 278 struct clk_init_data init; 279 struct clk *clk; 280 281 emc = kzalloc(sizeof(*emc), GFP_KERNEL); 282 if (!emc) 283 return ERR_PTR(-ENOMEM); 284 285 emc->regs = regs; 286 287 init.name = "emc"; 288 init.ops = &tegra210_clk_emc_ops; 289 init.flags = CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE; 290 init.parent_names = tegra210_clk_emc_parents; 291 init.num_parents = ARRAY_SIZE(tegra210_clk_emc_parents); 292 emc->hw.init = &init; 293 294 clk = clk_register(NULL, &emc->hw); 295 if (IS_ERR(clk)) { 296 kfree(emc); 297 return clk; 298 } 299 300 return clk; 301 } 302 303 int tegra210_clk_emc_attach(struct clk *clk, 304 struct tegra210_clk_emc_provider *provider) 305 { 306 struct clk_hw *hw = __clk_get_hw(clk); 307 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); 308 struct device *dev = provider->dev; 309 unsigned int i; 310 int err; 311 312 if (!try_module_get(provider->owner)) 313 return -ENODEV; 314 315 for (i = 0; i < provider->num_configs; i++) { 316 struct tegra210_clk_emc_config *config = &provider->configs[i]; 317 struct clk_hw *parent; 318 bool same_freq; 319 u8 div, src; 320 321 div = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_DIVISOR, config->value); 322 src = FIELD_GET(CLK_SOURCE_EMC_2X_CLK_SRC, config->value); 323 324 /* do basic sanity checking on the EMC timings */ 325 if (div & 0x1) { 326 dev_err(dev, "invalid odd divider %u for rate %lu Hz\n", 327 div, config->rate); 328 err = -EINVAL; 329 goto put; 330 } 331 332 same_freq = config->value & CLK_SOURCE_EMC_MC_EMC_SAME_FREQ; 333 334 if (same_freq != config->same_freq) { 335 dev_err(dev, 336 "ambiguous EMC to MC ratio for rate %lu Hz\n", 337 config->rate); 338 err = -EINVAL; 339 goto put; 340 } 341 342 parent = clk_hw_get_parent_by_index(hw, src); 343 config->parent = src; 344 345 if (src == CLK_SRC_PLLM || src == CLK_SRC_PLLM_UD) { 346 config->parent_rate = config->rate * (1 + div / 2); 347 } else { 348 unsigned long rate = config->rate * (1 + div / 2); 349 350 config->parent_rate = clk_hw_get_rate(parent); 351 352 if (config->parent_rate != rate) { 353 dev_err(dev, 354 "rate %lu Hz does not match input\n", 355 config->rate); 356 err = -EINVAL; 357 goto put; 358 } 359 } 360 } 361 362 emc->provider = provider; 363 364 return 0; 365 366 put: 367 module_put(provider->owner); 368 return err; 369 } 370 EXPORT_SYMBOL_GPL(tegra210_clk_emc_attach); 371 372 void tegra210_clk_emc_detach(struct clk *clk) 373 { 374 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(__clk_get_hw(clk)); 375 376 module_put(emc->provider->owner); 377 emc->provider = NULL; 378 } 379 EXPORT_SYMBOL_GPL(tegra210_clk_emc_detach); 380