1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/io.h> 7 #include <linux/clk-provider.h> 8 #include <linux/clkdev.h> 9 #include <linux/init.h> 10 #include <linux/of.h> 11 #include <linux/of_address.h> 12 #include <linux/platform_device.h> 13 #include <linux/clk/tegra.h> 14 #include <linux/delay.h> 15 #include <dt-bindings/clock/tegra20-car.h> 16 17 #include "clk.h" 18 #include "clk-id.h" 19 20 #define MISC_CLK_ENB 0x48 21 22 #define OSC_CTRL 0x50 23 #define OSC_CTRL_OSC_FREQ_MASK (3u<<30) 24 #define OSC_CTRL_OSC_FREQ_13MHZ (0u<<30) 25 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1u<<30) 26 #define OSC_CTRL_OSC_FREQ_12MHZ (2u<<30) 27 #define OSC_CTRL_OSC_FREQ_26MHZ (3u<<30) 28 #define OSC_CTRL_MASK (0x3f2u | OSC_CTRL_OSC_FREQ_MASK) 29 30 #define OSC_CTRL_PLL_REF_DIV_MASK (3u<<28) 31 #define OSC_CTRL_PLL_REF_DIV_1 (0u<<28) 32 #define OSC_CTRL_PLL_REF_DIV_2 (1u<<28) 33 #define OSC_CTRL_PLL_REF_DIV_4 (2u<<28) 34 35 #define OSC_FREQ_DET 0x58 36 #define OSC_FREQ_DET_TRIG (1u<<31) 37 38 #define OSC_FREQ_DET_STATUS 0x5c 39 #define OSC_FREQ_DET_BUSYu (1<<31) 40 #define OSC_FREQ_DET_CNT_MASK 0xFFFFu 41 42 #define TEGRA20_CLK_PERIPH_BANKS 3 43 44 #define PLLS_BASE 0xf0 45 #define PLLS_MISC 0xf4 46 #define PLLC_BASE 0x80 47 #define PLLC_MISC 0x8c 48 #define PLLM_BASE 0x90 49 #define PLLM_MISC 0x9c 50 #define PLLP_BASE 0xa0 51 #define PLLP_MISC 0xac 52 #define PLLA_BASE 0xb0 53 #define PLLA_MISC 0xbc 54 #define PLLU_BASE 0xc0 55 #define PLLU_MISC 0xcc 56 #define PLLD_BASE 0xd0 57 #define PLLD_MISC 0xdc 58 #define PLLX_BASE 0xe0 59 #define PLLX_MISC 0xe4 60 #define PLLE_BASE 0xe8 61 #define PLLE_MISC 0xec 62 63 #define PLL_BASE_LOCK BIT(27) 64 #define PLLE_MISC_LOCK BIT(11) 65 66 #define PLL_MISC_LOCK_ENABLE 18 67 #define PLLDU_MISC_LOCK_ENABLE 22 68 #define PLLE_MISC_LOCK_ENABLE 9 69 70 #define PLLC_OUT 0x84 71 #define PLLM_OUT 0x94 72 #define PLLP_OUTA 0xa4 73 #define PLLP_OUTB 0xa8 74 #define PLLA_OUT 0xb4 75 76 #define CCLK_BURST_POLICY 0x20 77 #define SUPER_CCLK_DIVIDER 0x24 78 #define SCLK_BURST_POLICY 0x28 79 #define SUPER_SCLK_DIVIDER 0x2c 80 #define CLK_SYSTEM_RATE 0x30 81 82 #define CCLK_BURST_POLICY_SHIFT 28 83 #define CCLK_RUN_POLICY_SHIFT 4 84 #define CCLK_IDLE_POLICY_SHIFT 0 85 #define CCLK_IDLE_POLICY 1 86 #define CCLK_RUN_POLICY 2 87 #define CCLK_BURST_POLICY_PLLX 8 88 89 #define CLK_SOURCE_I2S1 0x100 90 #define CLK_SOURCE_I2S2 0x104 91 #define CLK_SOURCE_PWM 0x110 92 #define CLK_SOURCE_SPI 0x114 93 #define CLK_SOURCE_XIO 0x120 94 #define CLK_SOURCE_TWC 0x12c 95 #define CLK_SOURCE_IDE 0x144 96 #define CLK_SOURCE_HDMI 0x18c 97 #define CLK_SOURCE_DISP1 0x138 98 #define CLK_SOURCE_DISP2 0x13c 99 #define CLK_SOURCE_CSITE 0x1d4 100 #define CLK_SOURCE_I2C1 0x124 101 #define CLK_SOURCE_I2C2 0x198 102 #define CLK_SOURCE_I2C3 0x1b8 103 #define CLK_SOURCE_DVC 0x128 104 #define CLK_SOURCE_UARTA 0x178 105 #define CLK_SOURCE_UARTB 0x17c 106 #define CLK_SOURCE_UARTC 0x1a0 107 #define CLK_SOURCE_UARTD 0x1c0 108 #define CLK_SOURCE_UARTE 0x1c4 109 #define CLK_SOURCE_EMC 0x19c 110 111 #define AUDIO_SYNC_CLK 0x38 112 113 /* Tegra CPU clock and reset control regs */ 114 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 115 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 116 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 117 118 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) 119 #define CPU_RESET(cpu) (0x1111ul << (cpu)) 120 121 #ifdef CONFIG_PM_SLEEP 122 static struct cpu_clk_suspend_context { 123 u32 pllx_misc; 124 u32 pllx_base; 125 126 u32 cpu_burst; 127 u32 clk_csite_src; 128 u32 cclk_divider; 129 } tegra20_cpu_clk_sctx; 130 #endif 131 132 static void __iomem *clk_base; 133 static void __iomem *pmc_base; 134 135 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ 136 _clk_num, _gate_flags, _clk_id) \ 137 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 138 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 139 _clk_num, \ 140 _gate_flags, _clk_id) 141 142 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \ 143 _clk_num, _gate_flags, _clk_id) \ 144 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 145 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \ 146 _clk_num, _gate_flags, \ 147 _clk_id) 148 149 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ 150 _mux_shift, _mux_width, _clk_num, \ 151 _gate_flags, _clk_id) \ 152 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 153 _mux_shift, _mux_width, 0, 0, 0, 0, 0, \ 154 _clk_num, _gate_flags, \ 155 _clk_id) 156 157 static struct clk **clks; 158 159 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 160 { 12000000, 600000000, 600, 12, 1, 8 }, 161 { 13000000, 600000000, 600, 13, 1, 8 }, 162 { 19200000, 600000000, 500, 16, 1, 6 }, 163 { 26000000, 600000000, 600, 26, 1, 8 }, 164 { 0, 0, 0, 0, 0, 0 }, 165 }; 166 167 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 168 { 12000000, 666000000, 666, 12, 1, 8 }, 169 { 13000000, 666000000, 666, 13, 1, 8 }, 170 { 19200000, 666000000, 555, 16, 1, 8 }, 171 { 26000000, 666000000, 666, 26, 1, 8 }, 172 { 12000000, 600000000, 600, 12, 1, 8 }, 173 { 13000000, 600000000, 600, 13, 1, 8 }, 174 { 19200000, 600000000, 375, 12, 1, 6 }, 175 { 26000000, 600000000, 600, 26, 1, 8 }, 176 { 0, 0, 0, 0, 0, 0 }, 177 }; 178 179 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 180 { 12000000, 216000000, 432, 12, 2, 8 }, 181 { 13000000, 216000000, 432, 13, 2, 8 }, 182 { 19200000, 216000000, 90, 4, 2, 1 }, 183 { 26000000, 216000000, 432, 26, 2, 8 }, 184 { 12000000, 432000000, 432, 12, 1, 8 }, 185 { 13000000, 432000000, 432, 13, 1, 8 }, 186 { 19200000, 432000000, 90, 4, 1, 1 }, 187 { 26000000, 432000000, 432, 26, 1, 8 }, 188 { 0, 0, 0, 0, 0, 0 }, 189 }; 190 191 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 192 { 28800000, 56448000, 49, 25, 1, 1 }, 193 { 28800000, 73728000, 64, 25, 1, 1 }, 194 { 28800000, 24000000, 5, 6, 1, 1 }, 195 { 0, 0, 0, 0, 0, 0 }, 196 }; 197 198 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 199 { 12000000, 216000000, 216, 12, 1, 4 }, 200 { 13000000, 216000000, 216, 13, 1, 4 }, 201 { 19200000, 216000000, 135, 12, 1, 3 }, 202 { 26000000, 216000000, 216, 26, 1, 4 }, 203 { 12000000, 594000000, 594, 12, 1, 8 }, 204 { 13000000, 594000000, 594, 13, 1, 8 }, 205 { 19200000, 594000000, 495, 16, 1, 8 }, 206 { 26000000, 594000000, 594, 26, 1, 8 }, 207 { 12000000, 1000000000, 1000, 12, 1, 12 }, 208 { 13000000, 1000000000, 1000, 13, 1, 12 }, 209 { 19200000, 1000000000, 625, 12, 1, 8 }, 210 { 26000000, 1000000000, 1000, 26, 1, 12 }, 211 { 0, 0, 0, 0, 0, 0 }, 212 }; 213 214 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 215 { 12000000, 480000000, 960, 12, 1, 0 }, 216 { 13000000, 480000000, 960, 13, 1, 0 }, 217 { 19200000, 480000000, 200, 4, 1, 0 }, 218 { 26000000, 480000000, 960, 26, 1, 0 }, 219 { 0, 0, 0, 0, 0, 0 }, 220 }; 221 222 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 223 /* 1 GHz */ 224 { 12000000, 1000000000, 1000, 12, 1, 12 }, 225 { 13000000, 1000000000, 1000, 13, 1, 12 }, 226 { 19200000, 1000000000, 625, 12, 1, 8 }, 227 { 26000000, 1000000000, 1000, 26, 1, 12 }, 228 /* 912 MHz */ 229 { 12000000, 912000000, 912, 12, 1, 12 }, 230 { 13000000, 912000000, 912, 13, 1, 12 }, 231 { 19200000, 912000000, 760, 16, 1, 8 }, 232 { 26000000, 912000000, 912, 26, 1, 12 }, 233 /* 816 MHz */ 234 { 12000000, 816000000, 816, 12, 1, 12 }, 235 { 13000000, 816000000, 816, 13, 1, 12 }, 236 { 19200000, 816000000, 680, 16, 1, 8 }, 237 { 26000000, 816000000, 816, 26, 1, 12 }, 238 /* 760 MHz */ 239 { 12000000, 760000000, 760, 12, 1, 12 }, 240 { 13000000, 760000000, 760, 13, 1, 12 }, 241 { 19200000, 760000000, 950, 24, 1, 8 }, 242 { 26000000, 760000000, 760, 26, 1, 12 }, 243 /* 750 MHz */ 244 { 12000000, 750000000, 750, 12, 1, 12 }, 245 { 13000000, 750000000, 750, 13, 1, 12 }, 246 { 19200000, 750000000, 625, 16, 1, 8 }, 247 { 26000000, 750000000, 750, 26, 1, 12 }, 248 /* 608 MHz */ 249 { 12000000, 608000000, 608, 12, 1, 12 }, 250 { 13000000, 608000000, 608, 13, 1, 12 }, 251 { 19200000, 608000000, 380, 12, 1, 8 }, 252 { 26000000, 608000000, 608, 26, 1, 12 }, 253 /* 456 MHz */ 254 { 12000000, 456000000, 456, 12, 1, 12 }, 255 { 13000000, 456000000, 456, 13, 1, 12 }, 256 { 19200000, 456000000, 380, 16, 1, 8 }, 257 { 26000000, 456000000, 456, 26, 1, 12 }, 258 /* 312 MHz */ 259 { 12000000, 312000000, 312, 12, 1, 12 }, 260 { 13000000, 312000000, 312, 13, 1, 12 }, 261 { 19200000, 312000000, 260, 16, 1, 8 }, 262 { 26000000, 312000000, 312, 26, 1, 12 }, 263 { 0, 0, 0, 0, 0, 0 }, 264 }; 265 266 static const struct pdiv_map plle_p[] = { 267 { .pdiv = 1, .hw_val = 1 }, 268 { .pdiv = 0, .hw_val = 0 }, 269 }; 270 271 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 272 { 12000000, 100000000, 200, 24, 1, 0 }, 273 { 0, 0, 0, 0, 0, 0 }, 274 }; 275 276 /* PLL parameters */ 277 static struct tegra_clk_pll_params pll_c_params = { 278 .input_min = 2000000, 279 .input_max = 31000000, 280 .cf_min = 1000000, 281 .cf_max = 6000000, 282 .vco_min = 20000000, 283 .vco_max = 1400000000, 284 .base_reg = PLLC_BASE, 285 .misc_reg = PLLC_MISC, 286 .lock_mask = PLL_BASE_LOCK, 287 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 288 .lock_delay = 300, 289 .freq_table = pll_c_freq_table, 290 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 291 }; 292 293 static struct tegra_clk_pll_params pll_m_params = { 294 .input_min = 2000000, 295 .input_max = 31000000, 296 .cf_min = 1000000, 297 .cf_max = 6000000, 298 .vco_min = 20000000, 299 .vco_max = 1200000000, 300 .base_reg = PLLM_BASE, 301 .misc_reg = PLLM_MISC, 302 .lock_mask = PLL_BASE_LOCK, 303 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 304 .lock_delay = 300, 305 .freq_table = pll_m_freq_table, 306 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 307 }; 308 309 static struct tegra_clk_pll_params pll_p_params = { 310 .input_min = 2000000, 311 .input_max = 31000000, 312 .cf_min = 1000000, 313 .cf_max = 6000000, 314 .vco_min = 20000000, 315 .vco_max = 1400000000, 316 .base_reg = PLLP_BASE, 317 .misc_reg = PLLP_MISC, 318 .lock_mask = PLL_BASE_LOCK, 319 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 320 .lock_delay = 300, 321 .freq_table = pll_p_freq_table, 322 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | 323 TEGRA_PLL_HAS_LOCK_ENABLE, 324 .fixed_rate = 216000000, 325 }; 326 327 static struct tegra_clk_pll_params pll_a_params = { 328 .input_min = 2000000, 329 .input_max = 31000000, 330 .cf_min = 1000000, 331 .cf_max = 6000000, 332 .vco_min = 20000000, 333 .vco_max = 1400000000, 334 .base_reg = PLLA_BASE, 335 .misc_reg = PLLA_MISC, 336 .lock_mask = PLL_BASE_LOCK, 337 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 338 .lock_delay = 300, 339 .freq_table = pll_a_freq_table, 340 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 341 }; 342 343 static struct tegra_clk_pll_params pll_d_params = { 344 .input_min = 2000000, 345 .input_max = 40000000, 346 .cf_min = 1000000, 347 .cf_max = 6000000, 348 .vco_min = 40000000, 349 .vco_max = 1000000000, 350 .base_reg = PLLD_BASE, 351 .misc_reg = PLLD_MISC, 352 .lock_mask = PLL_BASE_LOCK, 353 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 354 .lock_delay = 1000, 355 .freq_table = pll_d_freq_table, 356 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 357 }; 358 359 static const struct pdiv_map pllu_p[] = { 360 { .pdiv = 1, .hw_val = 1 }, 361 { .pdiv = 2, .hw_val = 0 }, 362 { .pdiv = 0, .hw_val = 0 }, 363 }; 364 365 static struct tegra_clk_pll_params pll_u_params = { 366 .input_min = 2000000, 367 .input_max = 40000000, 368 .cf_min = 1000000, 369 .cf_max = 6000000, 370 .vco_min = 48000000, 371 .vco_max = 960000000, 372 .base_reg = PLLU_BASE, 373 .misc_reg = PLLU_MISC, 374 .lock_mask = PLL_BASE_LOCK, 375 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 376 .lock_delay = 1000, 377 .pdiv_tohw = pllu_p, 378 .freq_table = pll_u_freq_table, 379 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 380 }; 381 382 static struct tegra_clk_pll_params pll_x_params = { 383 .input_min = 2000000, 384 .input_max = 31000000, 385 .cf_min = 1000000, 386 .cf_max = 6000000, 387 .vco_min = 20000000, 388 .vco_max = 1200000000, 389 .base_reg = PLLX_BASE, 390 .misc_reg = PLLX_MISC, 391 .lock_mask = PLL_BASE_LOCK, 392 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 393 .lock_delay = 300, 394 .freq_table = pll_x_freq_table, 395 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, 396 .pre_rate_change = tegra_cclk_pre_pllx_rate_change, 397 .post_rate_change = tegra_cclk_post_pllx_rate_change, 398 }; 399 400 static struct tegra_clk_pll_params pll_e_params = { 401 .input_min = 12000000, 402 .input_max = 12000000, 403 .cf_min = 0, 404 .cf_max = 0, 405 .vco_min = 0, 406 .vco_max = 0, 407 .base_reg = PLLE_BASE, 408 .misc_reg = PLLE_MISC, 409 .lock_mask = PLLE_MISC_LOCK, 410 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 411 .lock_delay = 0, 412 .pdiv_tohw = plle_p, 413 .freq_table = pll_e_freq_table, 414 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | 415 TEGRA_PLL_HAS_LOCK_ENABLE, 416 .fixed_rate = 100000000, 417 }; 418 419 static struct tegra_devclk devclks[] = { 420 { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C }, 421 { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 }, 422 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P }, 423 { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 }, 424 { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 }, 425 { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 }, 426 { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 }, 427 { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M }, 428 { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 }, 429 { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X }, 430 { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U }, 431 { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D }, 432 { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 }, 433 { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A }, 434 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 }, 435 { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E }, 436 { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK }, 437 { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK }, 438 { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK }, 439 { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK }, 440 { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE }, 441 { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD }, 442 { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO }, 443 { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X }, 444 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 }, 445 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA }, 446 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC }, 447 { .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER }, 448 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC }, 449 { .con_id = "csus", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSUS }, 450 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP }, 451 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA }, 452 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV }, 453 { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC }, 454 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD }, 455 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 }, 456 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 }, 457 { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI }, 458 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI }, 459 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP }, 460 { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX }, 461 { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI }, 462 { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 }, 463 { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 }, 464 { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K }, 465 { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M }, 466 { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF }, 467 { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 }, 468 { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 }, 469 { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT }, 470 { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN }, 471 { .dev_id = "spi_tegra.0", .dt_id = TEGRA20_CLK_SBC1 }, 472 { .dev_id = "spi_tegra.1", .dt_id = TEGRA20_CLK_SBC2 }, 473 { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 }, 474 { .dev_id = "spi_tegra.3", .dt_id = TEGRA20_CLK_SBC4 }, 475 { .dev_id = "spi", .dt_id = TEGRA20_CLK_SPI }, 476 { .dev_id = "xio", .dt_id = TEGRA20_CLK_XIO }, 477 { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC }, 478 { .dev_id = "ide", .dt_id = TEGRA20_CLK_IDE }, 479 { .dev_id = "tegra_nand", .dt_id = TEGRA20_CLK_NDFLASH }, 480 { .dev_id = "vfir", .dt_id = TEGRA20_CLK_VFIR }, 481 { .dev_id = "csite", .dt_id = TEGRA20_CLK_CSITE }, 482 { .dev_id = "la", .dt_id = TEGRA20_CLK_LA }, 483 { .dev_id = "tegra_w1", .dt_id = TEGRA20_CLK_OWR }, 484 { .dev_id = "mipi", .dt_id = TEGRA20_CLK_MIPI }, 485 { .dev_id = "vde", .dt_id = TEGRA20_CLK_VDE }, 486 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI }, 487 { .dev_id = "epp", .dt_id = TEGRA20_CLK_EPP }, 488 { .dev_id = "mpe", .dt_id = TEGRA20_CLK_MPE }, 489 { .dev_id = "host1x", .dt_id = TEGRA20_CLK_HOST1X }, 490 { .dev_id = "3d", .dt_id = TEGRA20_CLK_GR3D }, 491 { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D }, 492 { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR }, 493 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 }, 494 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 }, 495 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 }, 496 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 }, 497 { .dev_id = "cve", .dt_id = TEGRA20_CLK_CVE }, 498 { .dev_id = "tvo", .dt_id = TEGRA20_CLK_TVO }, 499 { .dev_id = "tvdac", .dt_id = TEGRA20_CLK_TVDAC }, 500 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR }, 501 { .dev_id = "hdmi", .dt_id = TEGRA20_CLK_HDMI }, 502 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 }, 503 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 }, 504 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 }, 505 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC }, 506 { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM }, 507 { .dev_id = "tegra_uart.0", .dt_id = TEGRA20_CLK_UARTA }, 508 { .dev_id = "tegra_uart.1", .dt_id = TEGRA20_CLK_UARTB }, 509 { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC }, 510 { .dev_id = "tegra_uart.3", .dt_id = TEGRA20_CLK_UARTD }, 511 { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE }, 512 { .dev_id = "tegradc.0", .dt_id = TEGRA20_CLK_DISP1 }, 513 { .dev_id = "tegradc.1", .dt_id = TEGRA20_CLK_DISP2 }, 514 }; 515 516 static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = { 517 [tegra_clk_ahbdma] = { .dt_id = TEGRA20_CLK_AHBDMA, .present = true }, 518 [tegra_clk_apbdma] = { .dt_id = TEGRA20_CLK_APBDMA, .present = true }, 519 [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true }, 520 [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true }, 521 [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true }, 522 [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true }, 523 [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true }, 524 [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true }, 525 [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true }, 526 [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true }, 527 [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true }, 528 [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true }, 529 [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true }, 530 [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true }, 531 [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true }, 532 [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true }, 533 [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true }, 534 [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true }, 535 [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true }, 536 [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true }, 537 [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true }, 538 [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true }, 539 [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true }, 540 [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true }, 541 [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true }, 542 [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true }, 543 [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true }, 544 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true }, 545 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true }, 546 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true }, 547 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true }, 548 [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true }, 549 [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true }, 550 [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true }, 551 [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true }, 552 [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true }, 553 [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true }, 554 [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true }, 555 [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true }, 556 [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true }, 557 [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true }, 558 [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true }, 559 [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true }, 560 [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true }, 561 [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true }, 562 [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true }, 563 [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true }, 564 [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true }, 565 [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true }, 566 [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true }, 567 [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true }, 568 [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true }, 569 }; 570 571 static unsigned long tegra20_clk_measure_input_freq(void) 572 { 573 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 574 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK; 575 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 576 unsigned long input_freq; 577 578 switch (auto_clk_control) { 579 case OSC_CTRL_OSC_FREQ_12MHZ: 580 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 581 input_freq = 12000000; 582 break; 583 case OSC_CTRL_OSC_FREQ_13MHZ: 584 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 585 input_freq = 13000000; 586 break; 587 case OSC_CTRL_OSC_FREQ_19_2MHZ: 588 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 589 input_freq = 19200000; 590 break; 591 case OSC_CTRL_OSC_FREQ_26MHZ: 592 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 593 input_freq = 26000000; 594 break; 595 default: 596 pr_err("Unexpected clock autodetect value %d", 597 auto_clk_control); 598 BUG(); 599 return 0; 600 } 601 602 return input_freq; 603 } 604 605 static unsigned int tegra20_get_pll_ref_div(void) 606 { 607 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & 608 OSC_CTRL_PLL_REF_DIV_MASK; 609 610 switch (pll_ref_div) { 611 case OSC_CTRL_PLL_REF_DIV_1: 612 return 1; 613 case OSC_CTRL_PLL_REF_DIV_2: 614 return 2; 615 case OSC_CTRL_PLL_REF_DIV_4: 616 return 4; 617 default: 618 pr_err("Invalid pll ref divider %d\n", pll_ref_div); 619 BUG(); 620 } 621 return 0; 622 } 623 624 static void tegra20_pll_init(void) 625 { 626 struct clk *clk; 627 628 /* PLLC */ 629 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, 630 &pll_c_params, NULL); 631 clks[TEGRA20_CLK_PLL_C] = clk; 632 633 /* PLLC_OUT1 */ 634 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 635 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 636 8, 8, 1, NULL); 637 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 638 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 639 0, NULL); 640 clks[TEGRA20_CLK_PLL_C_OUT1] = clk; 641 642 /* PLLM */ 643 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, 644 CLK_SET_RATE_GATE, &pll_m_params, NULL); 645 clks[TEGRA20_CLK_PLL_M] = clk; 646 647 /* PLLM_OUT1 */ 648 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 649 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 650 8, 8, 1, NULL); 651 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 652 clk_base + PLLM_OUT, 1, 0, 653 CLK_SET_RATE_PARENT, 0, NULL); 654 clks[TEGRA20_CLK_PLL_M_OUT1] = clk; 655 656 /* PLLX */ 657 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, 658 &pll_x_params, NULL); 659 clks[TEGRA20_CLK_PLL_X] = clk; 660 661 /* PLLU */ 662 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, 663 &pll_u_params, NULL); 664 clks[TEGRA20_CLK_PLL_U] = clk; 665 666 /* PLLD */ 667 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, 668 &pll_d_params, NULL); 669 clks[TEGRA20_CLK_PLL_D] = clk; 670 671 /* PLLD_OUT0 */ 672 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 673 CLK_SET_RATE_PARENT, 1, 2); 674 clks[TEGRA20_CLK_PLL_D_OUT0] = clk; 675 676 /* PLLA */ 677 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, 678 &pll_a_params, NULL); 679 clks[TEGRA20_CLK_PLL_A] = clk; 680 681 /* PLLA_OUT0 */ 682 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 683 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 684 8, 8, 1, NULL); 685 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 686 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 687 CLK_SET_RATE_PARENT, 0, NULL); 688 clks[TEGRA20_CLK_PLL_A_OUT0] = clk; 689 690 /* PLLE */ 691 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, 692 0, &pll_e_params, NULL); 693 clks[TEGRA20_CLK_PLL_E] = clk; 694 } 695 696 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 697 "pll_p", "pll_p_out4", 698 "pll_p_out3", "clk_d", "pll_x" }; 699 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 700 "pll_p_out3", "pll_p_out2", "clk_d", 701 "clk_32k", "pll_m_out1" }; 702 703 static void tegra20_super_clk_init(void) 704 { 705 struct clk *clk; 706 707 /* CCLK */ 708 clk = tegra_clk_register_super_cclk("cclk", cclk_parents, 709 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, 710 clk_base + CCLK_BURST_POLICY, TEGRA20_SUPER_CLK, 711 NULL); 712 clks[TEGRA20_CLK_CCLK] = clk; 713 714 /* twd */ 715 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4); 716 clks[TEGRA20_CLK_TWD] = clk; 717 } 718 719 static const char *audio_parents[] = { "spdif_in", "i2s1", "i2s2", "unused", 720 "pll_a_out0", "unused", "unused", 721 "unused" }; 722 723 static void __init tegra20_audio_clk_init(void) 724 { 725 struct clk *clk; 726 727 /* audio */ 728 clk = clk_register_mux(NULL, "audio_mux", audio_parents, 729 ARRAY_SIZE(audio_parents), 730 CLK_SET_RATE_NO_REPARENT, 731 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL); 732 clk = clk_register_gate(NULL, "audio", "audio_mux", 0, 733 clk_base + AUDIO_SYNC_CLK, 4, 734 CLK_GATE_SET_TO_DISABLE, NULL); 735 clks[TEGRA20_CLK_AUDIO] = clk; 736 737 /* audio_2x */ 738 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio", 739 CLK_SET_RATE_PARENT, 2, 1); 740 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler", 741 TEGRA_PERIPH_NO_RESET, clk_base, 742 CLK_SET_RATE_PARENT, 89, 743 periph_clk_enb_refcnt); 744 clks[TEGRA20_CLK_AUDIO_2X] = clk; 745 } 746 747 static const char *i2s1_parents[] = { "pll_a_out0", "audio_2x", "pll_p", 748 "clk_m" }; 749 static const char *i2s2_parents[] = { "pll_a_out0", "audio_2x", "pll_p", 750 "clk_m" }; 751 static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m", 752 "clk_32k" }; 753 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" }; 754 static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c", 755 "clk_m" }; 756 757 static struct tegra_periph_init_data tegra_periph_clk_list[] = { 758 TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1), 759 TEGRA_INIT_DATA_MUX("i2s2", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S2), 760 TEGRA_INIT_DATA_MUX("spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_SPI), 761 TEGRA_INIT_DATA_MUX("xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, TEGRA20_CLK_XIO), 762 TEGRA_INIT_DATA_MUX("twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_TWC), 763 TEGRA_INIT_DATA_MUX("ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, TEGRA20_CLK_IDE), 764 TEGRA_INIT_DATA_DIV16("dvc", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_DVC), 765 TEGRA_INIT_DATA_DIV16("i2c1", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C1), 766 TEGRA_INIT_DATA_DIV16("i2c2", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C2), 767 TEGRA_INIT_DATA_DIV16("i2c3", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C3), 768 TEGRA_INIT_DATA_MUX("hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA20_CLK_HDMI), 769 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_PWM), 770 }; 771 772 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 773 TEGRA_INIT_DATA_NODIV("uarta", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA), 774 TEGRA_INIT_DATA_NODIV("uartb", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB), 775 TEGRA_INIT_DATA_NODIV("uartc", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC), 776 TEGRA_INIT_DATA_NODIV("uartd", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD), 777 TEGRA_INIT_DATA_NODIV("uarte", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE), 778 TEGRA_INIT_DATA_NODIV("disp1", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, TEGRA20_CLK_DISP1), 779 TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2), 780 }; 781 782 static void __init tegra20_periph_clk_init(void) 783 { 784 struct tegra_periph_init_data *data; 785 struct clk *clk; 786 unsigned int i; 787 788 /* ac97 */ 789 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", 790 TEGRA_PERIPH_ON_APB, 791 clk_base, 0, 3, periph_clk_enb_refcnt); 792 clks[TEGRA20_CLK_AC97] = clk; 793 794 /* emc */ 795 clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, false); 796 797 clks[TEGRA20_CLK_EMC] = clk; 798 799 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, 800 NULL); 801 clks[TEGRA20_CLK_MC] = clk; 802 803 /* dsi */ 804 clk = tegra_clk_register_periph_gate("dsi", "pll_d_out0", 0, 805 clk_base, 0, TEGRA20_CLK_DSI, 806 periph_clk_enb_refcnt); 807 clks[TEGRA20_CLK_DSI] = clk; 808 809 /* pex */ 810 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, 811 periph_clk_enb_refcnt); 812 clks[TEGRA20_CLK_PEX] = clk; 813 814 /* dev1 OSC divider */ 815 clk_register_divider(NULL, "dev1_osc_div", "clk_m", 816 0, clk_base + MISC_CLK_ENB, 22, 2, 817 CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY, 818 NULL); 819 820 /* dev2 OSC divider */ 821 clk_register_divider(NULL, "dev2_osc_div", "clk_m", 822 0, clk_base + MISC_CLK_ENB, 20, 2, 823 CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY, 824 NULL); 825 826 /* cdev1 */ 827 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0, 828 clk_base, 0, 94, periph_clk_enb_refcnt); 829 clks[TEGRA20_CLK_CDEV1] = clk; 830 831 /* cdev2 */ 832 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0, 833 clk_base, 0, 93, periph_clk_enb_refcnt); 834 clks[TEGRA20_CLK_CDEV2] = clk; 835 836 /* csus */ 837 clk = tegra_clk_register_periph_gate("csus", "csus_mux", 0, 838 clk_base, 0, TEGRA20_CLK_CSUS, 839 periph_clk_enb_refcnt); 840 clks[TEGRA20_CLK_CSUS] = clk; 841 842 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 843 data = &tegra_periph_clk_list[i]; 844 clk = tegra_clk_register_periph_data(clk_base, data); 845 clks[data->clk_id] = clk; 846 } 847 848 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 849 data = &tegra_periph_nodiv_clk_list[i]; 850 clk = tegra_clk_register_periph_nodiv(data->name, 851 data->p.parent_names, 852 data->num_parents, &data->periph, 853 clk_base, data->offset); 854 clks[data->clk_id] = clk; 855 } 856 857 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params); 858 } 859 860 static void __init tegra20_osc_clk_init(void) 861 { 862 struct clk *clk; 863 unsigned long input_freq; 864 unsigned int pll_ref_div; 865 866 input_freq = tegra20_clk_measure_input_freq(); 867 868 /* clk_m */ 869 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IGNORE_UNUSED, 870 input_freq); 871 clks[TEGRA20_CLK_CLK_M] = clk; 872 873 /* pll_ref */ 874 pll_ref_div = tegra20_get_pll_ref_div(); 875 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 876 CLK_SET_RATE_PARENT, 1, pll_ref_div); 877 clks[TEGRA20_CLK_PLL_REF] = clk; 878 } 879 880 /* Tegra20 CPU clock and reset control functions */ 881 static void tegra20_wait_cpu_in_reset(u32 cpu) 882 { 883 unsigned int reg; 884 885 do { 886 reg = readl(clk_base + 887 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 888 cpu_relax(); 889 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 890 891 return; 892 } 893 894 static void tegra20_put_cpu_in_reset(u32 cpu) 895 { 896 writel(CPU_RESET(cpu), 897 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 898 dmb(); 899 } 900 901 static void tegra20_cpu_out_of_reset(u32 cpu) 902 { 903 writel(CPU_RESET(cpu), 904 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 905 wmb(); 906 } 907 908 static void tegra20_enable_cpu_clock(u32 cpu) 909 { 910 unsigned int reg; 911 912 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 913 writel(reg & ~CPU_CLOCK(cpu), 914 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 915 barrier(); 916 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 917 } 918 919 static void tegra20_disable_cpu_clock(u32 cpu) 920 { 921 unsigned int reg; 922 923 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 924 writel(reg | CPU_CLOCK(cpu), 925 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 926 } 927 928 #ifdef CONFIG_PM_SLEEP 929 static bool tegra20_cpu_rail_off_ready(void) 930 { 931 unsigned int cpu_rst_status; 932 933 cpu_rst_status = readl(clk_base + 934 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 935 936 return !!(cpu_rst_status & 0x2); 937 } 938 939 static void tegra20_cpu_clock_suspend(void) 940 { 941 /* switch coresite to clk_m, save off original source */ 942 tegra20_cpu_clk_sctx.clk_csite_src = 943 readl(clk_base + CLK_SOURCE_CSITE); 944 writel(3<<30, clk_base + CLK_SOURCE_CSITE); 945 946 tegra20_cpu_clk_sctx.cpu_burst = 947 readl(clk_base + CCLK_BURST_POLICY); 948 tegra20_cpu_clk_sctx.pllx_base = 949 readl(clk_base + PLLX_BASE); 950 tegra20_cpu_clk_sctx.pllx_misc = 951 readl(clk_base + PLLX_MISC); 952 tegra20_cpu_clk_sctx.cclk_divider = 953 readl(clk_base + SUPER_CCLK_DIVIDER); 954 } 955 956 static void tegra20_cpu_clock_resume(void) 957 { 958 unsigned int reg, policy; 959 u32 misc, base; 960 961 /* Is CPU complex already running on PLLX? */ 962 reg = readl(clk_base + CCLK_BURST_POLICY); 963 policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF; 964 965 if (policy == CCLK_IDLE_POLICY) 966 reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF; 967 else if (policy == CCLK_RUN_POLICY) 968 reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF; 969 else 970 BUG(); 971 972 if (reg != CCLK_BURST_POLICY_PLLX) { 973 misc = readl_relaxed(clk_base + PLLX_MISC); 974 base = readl_relaxed(clk_base + PLLX_BASE); 975 976 if (misc != tegra20_cpu_clk_sctx.pllx_misc || 977 base != tegra20_cpu_clk_sctx.pllx_base) { 978 /* restore PLLX settings if CPU is on different PLL */ 979 writel(tegra20_cpu_clk_sctx.pllx_misc, 980 clk_base + PLLX_MISC); 981 writel(tegra20_cpu_clk_sctx.pllx_base, 982 clk_base + PLLX_BASE); 983 984 /* wait for PLL stabilization if PLLX was enabled */ 985 if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30)) 986 udelay(300); 987 } 988 } 989 990 /* 991 * Restore original burst policy setting for calls resulting from CPU 992 * LP2 in idle or system suspend. 993 */ 994 writel(tegra20_cpu_clk_sctx.cclk_divider, 995 clk_base + SUPER_CCLK_DIVIDER); 996 writel(tegra20_cpu_clk_sctx.cpu_burst, 997 clk_base + CCLK_BURST_POLICY); 998 999 writel(tegra20_cpu_clk_sctx.clk_csite_src, 1000 clk_base + CLK_SOURCE_CSITE); 1001 } 1002 #endif 1003 1004 static struct tegra_cpu_car_ops tegra20_cpu_car_ops = { 1005 .wait_for_reset = tegra20_wait_cpu_in_reset, 1006 .put_in_reset = tegra20_put_cpu_in_reset, 1007 .out_of_reset = tegra20_cpu_out_of_reset, 1008 .enable_clock = tegra20_enable_cpu_clock, 1009 .disable_clock = tegra20_disable_cpu_clock, 1010 #ifdef CONFIG_PM_SLEEP 1011 .rail_off_ready = tegra20_cpu_rail_off_ready, 1012 .suspend = tegra20_cpu_clock_suspend, 1013 .resume = tegra20_cpu_clock_resume, 1014 #endif 1015 }; 1016 1017 static struct tegra_clk_init_table init_table[] = { 1018 { TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1 }, 1019 { TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1 }, 1020 { TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 }, 1021 { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 }, 1022 { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 }, 1023 { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 }, 1024 { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 0 }, 1025 { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 120000000, 0 }, 1026 { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 120000000, 0 }, 1027 { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 }, 1028 { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 }, 1029 { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 }, 1030 { TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 }, 1031 { TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 }, 1032 { TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 }, 1033 { TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 }, 1034 { TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 }, 1035 { TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 0 }, 1036 { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 0 }, 1037 { TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 }, 1038 { TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 }, 1039 { TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 }, 1040 { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 }, 1041 { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 }, 1042 { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 }, 1043 { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 }, 1044 { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 }, 1045 { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 }, 1046 { TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 }, 1047 { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 }, 1048 { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 }, 1049 { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, 1050 { TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 }, 1051 { TEGRA20_CLK_PWM, TEGRA20_CLK_PLL_P, 48000000, 0 }, 1052 /* must be the last entry */ 1053 { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, 1054 }; 1055 1056 /* 1057 * Some clocks may be used by different drivers depending on the board 1058 * configuration. List those here to register them twice in the clock lookup 1059 * table under two names. 1060 */ 1061 static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1062 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL), 1063 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL), 1064 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL), 1065 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"), 1066 /* must be the last entry */ 1067 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL), 1068 }; 1069 1070 static const struct of_device_id pmc_match[] __initconst = { 1071 { .compatible = "nvidia,tegra20-pmc" }, 1072 { }, 1073 }; 1074 1075 static bool tegra20_car_initialized; 1076 1077 static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec, 1078 void *data) 1079 { 1080 struct clk_hw *parent_hw; 1081 struct clk_hw *hw; 1082 struct clk *clk; 1083 1084 /* 1085 * Timer clocks are needed early, the rest of the clocks shouldn't be 1086 * available to device drivers until clock tree is fully initialized. 1087 */ 1088 if (clkspec->args[0] != TEGRA20_CLK_RTC && 1089 clkspec->args[0] != TEGRA20_CLK_TWD && 1090 clkspec->args[0] != TEGRA20_CLK_TIMER && 1091 !tegra20_car_initialized) 1092 return ERR_PTR(-EPROBE_DEFER); 1093 1094 clk = of_clk_src_onecell_get(clkspec, data); 1095 if (IS_ERR(clk)) 1096 return clk; 1097 1098 hw = __clk_get_hw(clk); 1099 1100 /* 1101 * Tegra20 CDEV1, CDEV2 and CSUS clocks are a bit special case, their 1102 * parent clock is created by the pinctrl driver. It is possible for 1103 * clk user to request these clocks before pinctrl driver got probed 1104 * and hence user will get an orphaned clock. That might be undesirable 1105 * because user may expect parent clock to be enabled by the child. 1106 */ 1107 if (clkspec->args[0] == TEGRA20_CLK_CDEV1 || 1108 clkspec->args[0] == TEGRA20_CLK_CDEV2 || 1109 clkspec->args[0] == TEGRA20_CLK_CSUS) { 1110 parent_hw = clk_hw_get_parent(hw); 1111 if (!parent_hw) 1112 return ERR_PTR(-EPROBE_DEFER); 1113 } 1114 1115 if (clkspec->args[0] == TEGRA20_CLK_EMC) { 1116 if (!tegra20_clk_emc_driver_available(hw)) 1117 return ERR_PTR(-EPROBE_DEFER); 1118 } 1119 1120 return clk; 1121 } 1122 1123 static void __init tegra20_clock_init(struct device_node *np) 1124 { 1125 struct device_node *node; 1126 1127 clk_base = of_iomap(np, 0); 1128 if (!clk_base) { 1129 pr_err("Can't map CAR registers\n"); 1130 BUG(); 1131 } 1132 1133 node = of_find_matching_node(NULL, pmc_match); 1134 if (!node) { 1135 pr_err("Failed to find pmc node\n"); 1136 BUG(); 1137 } 1138 1139 pmc_base = of_iomap(node, 0); 1140 of_node_put(node); 1141 if (!pmc_base) { 1142 pr_err("Can't map pmc registers\n"); 1143 BUG(); 1144 } 1145 1146 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX, 1147 TEGRA20_CLK_PERIPH_BANKS); 1148 if (!clks) 1149 return; 1150 1151 tegra20_osc_clk_init(); 1152 tegra_fixed_clk_init(tegra20_clks); 1153 tegra20_pll_init(); 1154 tegra20_super_clk_init(); 1155 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL); 1156 tegra20_periph_clk_init(); 1157 tegra20_audio_clk_init(); 1158 1159 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX); 1160 1161 tegra_add_of_provider(np, tegra20_clk_src_onecell_get); 1162 1163 tegra_cpu_car_ops = &tegra20_cpu_car_ops; 1164 } 1165 CLK_OF_DECLARE_DRIVER(tegra20, "nvidia,tegra20-car", tegra20_clock_init); 1166 1167 /* 1168 * Clocks that use runtime PM can't be created at the tegra20_clock_init 1169 * time because drivers' base isn't initialized yet, and thus platform 1170 * devices can't be created for the clocks. Hence we need to split the 1171 * registration of the clocks into two phases. The first phase registers 1172 * essential clocks which don't require RPM and are actually used during 1173 * early boot. The second phase registers clocks which use RPM and this 1174 * is done when device drivers' core API is ready. 1175 */ 1176 static int tegra20_car_probe(struct platform_device *pdev) 1177 { 1178 struct clk *clk; 1179 1180 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 1181 ARRAY_SIZE(sclk_parents), 1182 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1183 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 1184 clks[TEGRA20_CLK_SCLK] = clk; 1185 1186 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1187 tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX); 1188 tegra20_car_initialized = true; 1189 1190 return 0; 1191 } 1192 1193 static const struct of_device_id tegra20_car_match[] = { 1194 { .compatible = "nvidia,tegra20-car" }, 1195 { } 1196 }; 1197 1198 static struct platform_driver tegra20_car_driver = { 1199 .driver = { 1200 .name = "tegra20-car", 1201 .of_match_table = tegra20_car_match, 1202 .suppress_bind_attrs = true, 1203 }, 1204 .probe = tegra20_car_probe, 1205 }; 1206 builtin_platform_driver(tegra20_car_driver); 1207