1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/io.h> 7 #include <linux/clk-provider.h> 8 #include <linux/clkdev.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/delay.h> 12 #include <linux/export.h> 13 #include <linux/clk/tegra.h> 14 #include <dt-bindings/clock/tegra124-car.h> 15 #include <dt-bindings/reset/tegra124-car.h> 16 17 #include "clk.h" 18 #include "clk-id.h" 19 20 /* 21 * TEGRA124_CAR_BANK_COUNT: the number of peripheral clock register 22 * banks present in the Tegra124/132 CAR IP block. The banks are 23 * identified by single letters, e.g.: L, H, U, V, W, X. See 24 * periph_regs[] in drivers/clk/tegra/clk.c 25 */ 26 #define TEGRA124_CAR_BANK_COUNT 6 27 28 #define CLK_SOURCE_CSITE 0x1d4 29 #define CLK_SOURCE_EMC 0x19c 30 31 #define RST_DFLL_DVCO 0x2f4 32 #define DVFS_DFLL_RESET_SHIFT 0 33 34 #define PLLC_BASE 0x80 35 #define PLLC_OUT 0x84 36 #define PLLC_MISC2 0x88 37 #define PLLC_MISC 0x8c 38 #define PLLC2_BASE 0x4e8 39 #define PLLC2_MISC 0x4ec 40 #define PLLC3_BASE 0x4fc 41 #define PLLC3_MISC 0x500 42 #define PLLM_BASE 0x90 43 #define PLLM_OUT 0x94 44 #define PLLM_MISC 0x9c 45 #define PLLP_BASE 0xa0 46 #define PLLP_MISC 0xac 47 #define PLLA_BASE 0xb0 48 #define PLLA_MISC 0xbc 49 #define PLLD_BASE 0xd0 50 #define PLLD_MISC 0xdc 51 #define PLLU_BASE 0xc0 52 #define PLLU_MISC 0xcc 53 #define PLLX_BASE 0xe0 54 #define PLLX_MISC 0xe4 55 #define PLLX_MISC2 0x514 56 #define PLLX_MISC3 0x518 57 #define PLLE_BASE 0xe8 58 #define PLLE_MISC 0xec 59 #define PLLD2_BASE 0x4b8 60 #define PLLD2_MISC 0x4bc 61 #define PLLE_AUX 0x48c 62 #define PLLRE_BASE 0x4c4 63 #define PLLRE_MISC 0x4c8 64 #define PLLDP_BASE 0x590 65 #define PLLDP_MISC 0x594 66 #define PLLC4_BASE 0x5a4 67 #define PLLC4_MISC 0x5a8 68 69 #define PLLC_IDDQ_BIT 26 70 #define PLLRE_IDDQ_BIT 16 71 #define PLLSS_IDDQ_BIT 19 72 73 #define PLL_BASE_LOCK BIT(27) 74 #define PLLE_MISC_LOCK BIT(11) 75 #define PLLRE_MISC_LOCK BIT(24) 76 77 #define PLL_MISC_LOCK_ENABLE 18 78 #define PLLC_MISC_LOCK_ENABLE 24 79 #define PLLDU_MISC_LOCK_ENABLE 22 80 #define PLLE_MISC_LOCK_ENABLE 9 81 #define PLLRE_MISC_LOCK_ENABLE 30 82 #define PLLSS_MISC_LOCK_ENABLE 30 83 84 #define PLLXC_SW_MAX_P 6 85 86 #define PMC_PLLM_WB0_OVERRIDE 0x1dc 87 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 88 89 #define CCLKG_BURST_POLICY 0x368 90 91 /* Tegra CPU clock and reset control regs */ 92 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 93 94 #ifdef CONFIG_PM_SLEEP 95 static struct cpu_clk_suspend_context { 96 u32 clk_csite_src; 97 u32 cclkg_burst; 98 u32 cclkg_divider; 99 } tegra124_cpu_clk_sctx; 100 #endif 101 102 static void __iomem *clk_base; 103 static void __iomem *pmc_base; 104 105 static unsigned long osc_freq; 106 static unsigned long pll_ref_freq; 107 108 static DEFINE_SPINLOCK(pll_d_lock); 109 static DEFINE_SPINLOCK(pll_e_lock); 110 static DEFINE_SPINLOCK(pll_re_lock); 111 static DEFINE_SPINLOCK(pll_u_lock); 112 static DEFINE_SPINLOCK(emc_lock); 113 114 /* possible OSC frequencies in Hz */ 115 static unsigned long tegra124_input_freq[] = { 116 [ 0] = 13000000, 117 [ 1] = 16800000, 118 [ 4] = 19200000, 119 [ 5] = 38400000, 120 [ 8] = 12000000, 121 [ 9] = 48000000, 122 [12] = 26000000, 123 }; 124 125 static struct div_nmp pllxc_nmp = { 126 .divm_shift = 0, 127 .divm_width = 8, 128 .divn_shift = 8, 129 .divn_width = 8, 130 .divp_shift = 20, 131 .divp_width = 4, 132 }; 133 134 static const struct pdiv_map pllxc_p[] = { 135 { .pdiv = 1, .hw_val = 0 }, 136 { .pdiv = 2, .hw_val = 1 }, 137 { .pdiv = 3, .hw_val = 2 }, 138 { .pdiv = 4, .hw_val = 3 }, 139 { .pdiv = 5, .hw_val = 4 }, 140 { .pdiv = 6, .hw_val = 5 }, 141 { .pdiv = 8, .hw_val = 6 }, 142 { .pdiv = 10, .hw_val = 7 }, 143 { .pdiv = 12, .hw_val = 8 }, 144 { .pdiv = 16, .hw_val = 9 }, 145 { .pdiv = 12, .hw_val = 10 }, 146 { .pdiv = 16, .hw_val = 11 }, 147 { .pdiv = 20, .hw_val = 12 }, 148 { .pdiv = 24, .hw_val = 13 }, 149 { .pdiv = 32, .hw_val = 14 }, 150 { .pdiv = 0, .hw_val = 0 }, 151 }; 152 153 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 154 /* 1 GHz */ 155 { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */ 156 { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */ 157 { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */ 158 { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */ 159 { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */ 160 { 0, 0, 0, 0, 0, 0 }, 161 }; 162 163 static struct tegra_clk_pll_params pll_x_params = { 164 .input_min = 12000000, 165 .input_max = 800000000, 166 .cf_min = 12000000, 167 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 168 .vco_min = 700000000, 169 .vco_max = 3000000000UL, 170 .base_reg = PLLX_BASE, 171 .misc_reg = PLLX_MISC, 172 .lock_mask = PLL_BASE_LOCK, 173 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 174 .lock_delay = 300, 175 .iddq_reg = PLLX_MISC3, 176 .iddq_bit_idx = 3, 177 .max_p = 6, 178 .dyn_ramp_reg = PLLX_MISC2, 179 .stepa_shift = 16, 180 .stepb_shift = 24, 181 .pdiv_tohw = pllxc_p, 182 .div_nmp = &pllxc_nmp, 183 .freq_table = pll_x_freq_table, 184 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 185 }; 186 187 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 188 { 12000000, 624000000, 104, 1, 2, 0 }, 189 { 12000000, 600000000, 100, 1, 2, 0 }, 190 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */ 191 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */ 192 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */ 193 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */ 194 { 0, 0, 0, 0, 0, 0 }, 195 }; 196 197 static struct tegra_clk_pll_params pll_c_params = { 198 .input_min = 12000000, 199 .input_max = 800000000, 200 .cf_min = 12000000, 201 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 202 .vco_min = 600000000, 203 .vco_max = 1400000000, 204 .base_reg = PLLC_BASE, 205 .misc_reg = PLLC_MISC, 206 .lock_mask = PLL_BASE_LOCK, 207 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE, 208 .lock_delay = 300, 209 .iddq_reg = PLLC_MISC, 210 .iddq_bit_idx = PLLC_IDDQ_BIT, 211 .max_p = PLLXC_SW_MAX_P, 212 .dyn_ramp_reg = PLLC_MISC2, 213 .stepa_shift = 17, 214 .stepb_shift = 9, 215 .pdiv_tohw = pllxc_p, 216 .div_nmp = &pllxc_nmp, 217 .freq_table = pll_c_freq_table, 218 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 219 }; 220 221 static struct div_nmp pllcx_nmp = { 222 .divm_shift = 0, 223 .divm_width = 2, 224 .divn_shift = 8, 225 .divn_width = 8, 226 .divp_shift = 20, 227 .divp_width = 3, 228 }; 229 230 static const struct pdiv_map pllc_p[] = { 231 { .pdiv = 1, .hw_val = 0 }, 232 { .pdiv = 2, .hw_val = 1 }, 233 { .pdiv = 3, .hw_val = 2 }, 234 { .pdiv = 4, .hw_val = 3 }, 235 { .pdiv = 6, .hw_val = 4 }, 236 { .pdiv = 8, .hw_val = 5 }, 237 { .pdiv = 12, .hw_val = 6 }, 238 { .pdiv = 16, .hw_val = 7 }, 239 { .pdiv = 0, .hw_val = 0 }, 240 }; 241 242 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { 243 { 12000000, 600000000, 100, 1, 2, 0 }, 244 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */ 245 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */ 246 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */ 247 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */ 248 { 0, 0, 0, 0, 0, 0 }, 249 }; 250 251 static struct tegra_clk_pll_params pll_c2_params = { 252 .input_min = 12000000, 253 .input_max = 48000000, 254 .cf_min = 12000000, 255 .cf_max = 19200000, 256 .vco_min = 600000000, 257 .vco_max = 1200000000, 258 .base_reg = PLLC2_BASE, 259 .misc_reg = PLLC2_MISC, 260 .lock_mask = PLL_BASE_LOCK, 261 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 262 .lock_delay = 300, 263 .pdiv_tohw = pllc_p, 264 .div_nmp = &pllcx_nmp, 265 .max_p = 7, 266 .ext_misc_reg[0] = 0x4f0, 267 .ext_misc_reg[1] = 0x4f4, 268 .ext_misc_reg[2] = 0x4f8, 269 .freq_table = pll_cx_freq_table, 270 .flags = TEGRA_PLL_USE_LOCK, 271 }; 272 273 static struct tegra_clk_pll_params pll_c3_params = { 274 .input_min = 12000000, 275 .input_max = 48000000, 276 .cf_min = 12000000, 277 .cf_max = 19200000, 278 .vco_min = 600000000, 279 .vco_max = 1200000000, 280 .base_reg = PLLC3_BASE, 281 .misc_reg = PLLC3_MISC, 282 .lock_mask = PLL_BASE_LOCK, 283 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 284 .lock_delay = 300, 285 .pdiv_tohw = pllc_p, 286 .div_nmp = &pllcx_nmp, 287 .max_p = 7, 288 .ext_misc_reg[0] = 0x504, 289 .ext_misc_reg[1] = 0x508, 290 .ext_misc_reg[2] = 0x50c, 291 .freq_table = pll_cx_freq_table, 292 .flags = TEGRA_PLL_USE_LOCK, 293 }; 294 295 static struct div_nmp pllss_nmp = { 296 .divm_shift = 0, 297 .divm_width = 8, 298 .divn_shift = 8, 299 .divn_width = 8, 300 .divp_shift = 20, 301 .divp_width = 4, 302 }; 303 304 static const struct pdiv_map pll12g_ssd_esd_p[] = { 305 { .pdiv = 1, .hw_val = 0 }, 306 { .pdiv = 2, .hw_val = 1 }, 307 { .pdiv = 3, .hw_val = 2 }, 308 { .pdiv = 4, .hw_val = 3 }, 309 { .pdiv = 5, .hw_val = 4 }, 310 { .pdiv = 6, .hw_val = 5 }, 311 { .pdiv = 8, .hw_val = 6 }, 312 { .pdiv = 10, .hw_val = 7 }, 313 { .pdiv = 12, .hw_val = 8 }, 314 { .pdiv = 16, .hw_val = 9 }, 315 { .pdiv = 12, .hw_val = 10 }, 316 { .pdiv = 16, .hw_val = 11 }, 317 { .pdiv = 20, .hw_val = 12 }, 318 { .pdiv = 24, .hw_val = 13 }, 319 { .pdiv = 32, .hw_val = 14 }, 320 { .pdiv = 0, .hw_val = 0 }, 321 }; 322 323 static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = { 324 { 12000000, 600000000, 100, 1, 2, 0 }, 325 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */ 326 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */ 327 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */ 328 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */ 329 { 0, 0, 0, 0, 0, 0 }, 330 }; 331 332 static struct tegra_clk_pll_params pll_c4_params = { 333 .input_min = 12000000, 334 .input_max = 1000000000, 335 .cf_min = 12000000, 336 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 337 .vco_min = 600000000, 338 .vco_max = 1200000000, 339 .base_reg = PLLC4_BASE, 340 .misc_reg = PLLC4_MISC, 341 .lock_mask = PLL_BASE_LOCK, 342 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, 343 .lock_delay = 300, 344 .iddq_reg = PLLC4_BASE, 345 .iddq_bit_idx = PLLSS_IDDQ_BIT, 346 .pdiv_tohw = pll12g_ssd_esd_p, 347 .div_nmp = &pllss_nmp, 348 .ext_misc_reg[0] = 0x5ac, 349 .ext_misc_reg[1] = 0x5b0, 350 .ext_misc_reg[2] = 0x5b4, 351 .freq_table = pll_c4_freq_table, 352 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 353 }; 354 355 static const struct pdiv_map pllm_p[] = { 356 { .pdiv = 1, .hw_val = 0 }, 357 { .pdiv = 2, .hw_val = 1 }, 358 { .pdiv = 3, .hw_val = 2 }, 359 { .pdiv = 4, .hw_val = 3 }, 360 { .pdiv = 5, .hw_val = 4 }, 361 { .pdiv = 6, .hw_val = 5 }, 362 { .pdiv = 8, .hw_val = 6 }, 363 { .pdiv = 10, .hw_val = 7 }, 364 { .pdiv = 12, .hw_val = 8 }, 365 { .pdiv = 16, .hw_val = 9 }, 366 { .pdiv = 12, .hw_val = 10 }, 367 { .pdiv = 16, .hw_val = 11 }, 368 { .pdiv = 20, .hw_val = 12 }, 369 { .pdiv = 24, .hw_val = 13 }, 370 { .pdiv = 32, .hw_val = 14 }, 371 { .pdiv = 0, .hw_val = 0 }, 372 }; 373 374 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 375 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */ 376 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */ 377 { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */ 378 { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */ 379 { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */ 380 { 0, 0, 0, 0, 0, 0}, 381 }; 382 383 static struct div_nmp pllm_nmp = { 384 .divm_shift = 0, 385 .divm_width = 8, 386 .override_divm_shift = 0, 387 .divn_shift = 8, 388 .divn_width = 8, 389 .override_divn_shift = 8, 390 .divp_shift = 20, 391 .divp_width = 1, 392 .override_divp_shift = 27, 393 }; 394 395 static struct tegra_clk_pll_params pll_m_params = { 396 .input_min = 12000000, 397 .input_max = 500000000, 398 .cf_min = 12000000, 399 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 400 .vco_min = 400000000, 401 .vco_max = 1066000000, 402 .base_reg = PLLM_BASE, 403 .misc_reg = PLLM_MISC, 404 .lock_mask = PLL_BASE_LOCK, 405 .lock_delay = 300, 406 .max_p = 5, 407 .pdiv_tohw = pllm_p, 408 .div_nmp = &pllm_nmp, 409 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 410 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, 411 .freq_table = pll_m_freq_table, 412 .flags = TEGRA_PLL_USE_LOCK, 413 }; 414 415 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 416 /* PLLE special case: use cpcon field to store cml divider value */ 417 { 336000000, 100000000, 100, 21, 16, 11 }, 418 { 312000000, 100000000, 200, 26, 24, 13 }, 419 { 13000000, 100000000, 200, 1, 26, 13 }, 420 { 12000000, 100000000, 200, 1, 24, 13 }, 421 { 0, 0, 0, 0, 0, 0 }, 422 }; 423 424 static const struct pdiv_map plle_p[] = { 425 { .pdiv = 1, .hw_val = 0 }, 426 { .pdiv = 2, .hw_val = 1 }, 427 { .pdiv = 3, .hw_val = 2 }, 428 { .pdiv = 4, .hw_val = 3 }, 429 { .pdiv = 5, .hw_val = 4 }, 430 { .pdiv = 6, .hw_val = 5 }, 431 { .pdiv = 8, .hw_val = 6 }, 432 { .pdiv = 10, .hw_val = 7 }, 433 { .pdiv = 12, .hw_val = 8 }, 434 { .pdiv = 16, .hw_val = 9 }, 435 { .pdiv = 12, .hw_val = 10 }, 436 { .pdiv = 16, .hw_val = 11 }, 437 { .pdiv = 20, .hw_val = 12 }, 438 { .pdiv = 24, .hw_val = 13 }, 439 { .pdiv = 32, .hw_val = 14 }, 440 { .pdiv = 1, .hw_val = 0 }, 441 }; 442 443 static struct div_nmp plle_nmp = { 444 .divm_shift = 0, 445 .divm_width = 8, 446 .divn_shift = 8, 447 .divn_width = 8, 448 .divp_shift = 24, 449 .divp_width = 4, 450 }; 451 452 static struct tegra_clk_pll_params pll_e_params = { 453 .input_min = 12000000, 454 .input_max = 1000000000, 455 .cf_min = 12000000, 456 .cf_max = 75000000, 457 .vco_min = 1600000000, 458 .vco_max = 2400000000U, 459 .base_reg = PLLE_BASE, 460 .misc_reg = PLLE_MISC, 461 .aux_reg = PLLE_AUX, 462 .lock_mask = PLLE_MISC_LOCK, 463 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 464 .lock_delay = 300, 465 .pdiv_tohw = plle_p, 466 .div_nmp = &plle_nmp, 467 .freq_table = pll_e_freq_table, 468 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE, 469 .fixed_rate = 100000000, 470 }; 471 472 static const struct clk_div_table pll_re_div_table[] = { 473 { .val = 0, .div = 1 }, 474 { .val = 1, .div = 2 }, 475 { .val = 2, .div = 3 }, 476 { .val = 3, .div = 4 }, 477 { .val = 4, .div = 5 }, 478 { .val = 5, .div = 6 }, 479 { .val = 0, .div = 0 }, 480 }; 481 482 static struct div_nmp pllre_nmp = { 483 .divm_shift = 0, 484 .divm_width = 8, 485 .divn_shift = 8, 486 .divn_width = 8, 487 .divp_shift = 16, 488 .divp_width = 4, 489 }; 490 491 static struct tegra_clk_pll_params pll_re_vco_params = { 492 .input_min = 12000000, 493 .input_max = 1000000000, 494 .cf_min = 12000000, 495 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 496 .vco_min = 300000000, 497 .vco_max = 600000000, 498 .base_reg = PLLRE_BASE, 499 .misc_reg = PLLRE_MISC, 500 .lock_mask = PLLRE_MISC_LOCK, 501 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE, 502 .lock_delay = 300, 503 .iddq_reg = PLLRE_MISC, 504 .iddq_bit_idx = PLLRE_IDDQ_BIT, 505 .div_nmp = &pllre_nmp, 506 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE | 507 TEGRA_PLL_LOCK_MISC, 508 }; 509 510 static struct div_nmp pllp_nmp = { 511 .divm_shift = 0, 512 .divm_width = 5, 513 .divn_shift = 8, 514 .divn_width = 10, 515 .divp_shift = 20, 516 .divp_width = 3, 517 }; 518 519 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 520 { 12000000, 408000000, 408, 12, 1, 8 }, 521 { 13000000, 408000000, 408, 13, 1, 8 }, 522 { 16800000, 408000000, 340, 14, 1, 8 }, 523 { 19200000, 408000000, 340, 16, 1, 8 }, 524 { 26000000, 408000000, 408, 26, 1, 8 }, 525 { 0, 0, 0, 0, 0, 0 }, 526 }; 527 528 static struct tegra_clk_pll_params pll_p_params = { 529 .input_min = 2000000, 530 .input_max = 31000000, 531 .cf_min = 1000000, 532 .cf_max = 6000000, 533 .vco_min = 200000000, 534 .vco_max = 700000000, 535 .base_reg = PLLP_BASE, 536 .misc_reg = PLLP_MISC, 537 .lock_mask = PLL_BASE_LOCK, 538 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 539 .lock_delay = 300, 540 .div_nmp = &pllp_nmp, 541 .freq_table = pll_p_freq_table, 542 .fixed_rate = 408000000, 543 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | 544 TEGRA_PLL_HAS_LOCK_ENABLE, 545 }; 546 547 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 548 { 9600000, 282240000, 147, 5, 1, 4 }, 549 { 9600000, 368640000, 192, 5, 1, 4 }, 550 { 9600000, 240000000, 200, 8, 1, 8 }, 551 { 28800000, 282240000, 245, 25, 1, 8 }, 552 { 28800000, 368640000, 320, 25, 1, 8 }, 553 { 28800000, 240000000, 200, 24, 1, 8 }, 554 { 0, 0, 0, 0, 0, 0 }, 555 }; 556 557 static struct tegra_clk_pll_params pll_a_params = { 558 .input_min = 2000000, 559 .input_max = 31000000, 560 .cf_min = 1000000, 561 .cf_max = 6000000, 562 .vco_min = 200000000, 563 .vco_max = 700000000, 564 .base_reg = PLLA_BASE, 565 .misc_reg = PLLA_MISC, 566 .lock_mask = PLL_BASE_LOCK, 567 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 568 .lock_delay = 300, 569 .div_nmp = &pllp_nmp, 570 .freq_table = pll_a_freq_table, 571 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK | 572 TEGRA_PLL_HAS_LOCK_ENABLE, 573 }; 574 575 static struct div_nmp plld_nmp = { 576 .divm_shift = 0, 577 .divm_width = 5, 578 .divn_shift = 8, 579 .divn_width = 11, 580 .divp_shift = 20, 581 .divp_width = 3, 582 }; 583 584 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 585 { 12000000, 216000000, 864, 12, 4, 12 }, 586 { 13000000, 216000000, 864, 13, 4, 12 }, 587 { 16800000, 216000000, 720, 14, 4, 12 }, 588 { 19200000, 216000000, 720, 16, 4, 12 }, 589 { 26000000, 216000000, 864, 26, 4, 12 }, 590 { 12000000, 594000000, 594, 12, 1, 12 }, 591 { 13000000, 594000000, 594, 13, 1, 12 }, 592 { 16800000, 594000000, 495, 14, 1, 12 }, 593 { 19200000, 594000000, 495, 16, 1, 12 }, 594 { 26000000, 594000000, 594, 26, 1, 12 }, 595 { 12000000, 1000000000, 1000, 12, 1, 12 }, 596 { 13000000, 1000000000, 1000, 13, 1, 12 }, 597 { 19200000, 1000000000, 625, 12, 1, 12 }, 598 { 26000000, 1000000000, 1000, 26, 1, 12 }, 599 { 0, 0, 0, 0, 0, 0 }, 600 }; 601 602 static struct tegra_clk_pll_params pll_d_params = { 603 .input_min = 2000000, 604 .input_max = 40000000, 605 .cf_min = 1000000, 606 .cf_max = 6000000, 607 .vco_min = 500000000, 608 .vco_max = 1000000000, 609 .base_reg = PLLD_BASE, 610 .misc_reg = PLLD_MISC, 611 .lock_mask = PLL_BASE_LOCK, 612 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 613 .lock_delay = 1000, 614 .div_nmp = &plld_nmp, 615 .freq_table = pll_d_freq_table, 616 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 617 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 618 }; 619 620 static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = { 621 { 12000000, 594000000, 99, 1, 2, 0 }, 622 { 13000000, 594000000, 91, 1, 2, 0 }, /* actual: 591.5 MHz */ 623 { 16800000, 594000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */ 624 { 19200000, 594000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */ 625 { 26000000, 594000000, 91, 2, 2, 0 }, /* actual: 591.5 MHz */ 626 { 0, 0, 0, 0, 0, 0 }, 627 }; 628 629 static struct tegra_clk_pll_params tegra124_pll_d2_params = { 630 .input_min = 12000000, 631 .input_max = 1000000000, 632 .cf_min = 12000000, 633 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 634 .vco_min = 600000000, 635 .vco_max = 1200000000, 636 .base_reg = PLLD2_BASE, 637 .misc_reg = PLLD2_MISC, 638 .lock_mask = PLL_BASE_LOCK, 639 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, 640 .lock_delay = 300, 641 .iddq_reg = PLLD2_BASE, 642 .iddq_bit_idx = PLLSS_IDDQ_BIT, 643 .pdiv_tohw = pll12g_ssd_esd_p, 644 .div_nmp = &pllss_nmp, 645 .ext_misc_reg[0] = 0x570, 646 .ext_misc_reg[1] = 0x574, 647 .ext_misc_reg[2] = 0x578, 648 .max_p = 15, 649 .freq_table = tegra124_pll_d2_freq_table, 650 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 651 }; 652 653 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = { 654 { 12000000, 600000000, 100, 1, 2, 0 }, 655 { 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */ 656 { 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */ 657 { 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */ 658 { 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */ 659 { 0, 0, 0, 0, 0, 0 }, 660 }; 661 662 static struct tegra_clk_pll_params pll_dp_params = { 663 .input_min = 12000000, 664 .input_max = 1000000000, 665 .cf_min = 12000000, 666 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 667 .vco_min = 600000000, 668 .vco_max = 1200000000, 669 .base_reg = PLLDP_BASE, 670 .misc_reg = PLLDP_MISC, 671 .lock_mask = PLL_BASE_LOCK, 672 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, 673 .lock_delay = 300, 674 .iddq_reg = PLLDP_BASE, 675 .iddq_bit_idx = PLLSS_IDDQ_BIT, 676 .pdiv_tohw = pll12g_ssd_esd_p, 677 .div_nmp = &pllss_nmp, 678 .ext_misc_reg[0] = 0x598, 679 .ext_misc_reg[1] = 0x59c, 680 .ext_misc_reg[2] = 0x5a0, 681 .max_p = 5, 682 .freq_table = pll_dp_freq_table, 683 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 684 }; 685 686 static const struct pdiv_map pllu_p[] = { 687 { .pdiv = 1, .hw_val = 1 }, 688 { .pdiv = 2, .hw_val = 0 }, 689 { .pdiv = 0, .hw_val = 0 }, 690 }; 691 692 static struct div_nmp pllu_nmp = { 693 .divm_shift = 0, 694 .divm_width = 5, 695 .divn_shift = 8, 696 .divn_width = 10, 697 .divp_shift = 20, 698 .divp_width = 1, 699 }; 700 701 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 702 { 12000000, 480000000, 960, 12, 2, 12 }, 703 { 13000000, 480000000, 960, 13, 2, 12 }, 704 { 16800000, 480000000, 400, 7, 2, 5 }, 705 { 19200000, 480000000, 200, 4, 2, 3 }, 706 { 26000000, 480000000, 960, 26, 2, 12 }, 707 { 0, 0, 0, 0, 0, 0 }, 708 }; 709 710 static struct tegra_clk_pll_params pll_u_params = { 711 .input_min = 2000000, 712 .input_max = 40000000, 713 .cf_min = 1000000, 714 .cf_max = 6000000, 715 .vco_min = 480000000, 716 .vco_max = 960000000, 717 .base_reg = PLLU_BASE, 718 .misc_reg = PLLU_MISC, 719 .lock_mask = PLL_BASE_LOCK, 720 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 721 .lock_delay = 1000, 722 .pdiv_tohw = pllu_p, 723 .div_nmp = &pllu_nmp, 724 .freq_table = pll_u_freq_table, 725 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 726 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 727 }; 728 729 static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { 730 [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true }, 731 [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true }, 732 [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true }, 733 [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true }, 734 [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true }, 735 [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true }, 736 [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true }, 737 [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true }, 738 [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true }, 739 [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true }, 740 [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true }, 741 [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true }, 742 [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true }, 743 [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true }, 744 [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true }, 745 [tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true }, 746 [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true }, 747 [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true }, 748 [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true }, 749 [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true }, 750 [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true }, 751 [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true }, 752 [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true }, 753 [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true }, 754 [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true }, 755 [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true }, 756 [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true }, 757 [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true }, 758 [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true }, 759 [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true }, 760 [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true }, 761 [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true }, 762 [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true }, 763 [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true }, 764 [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true }, 765 [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true }, 766 [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true }, 767 [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true }, 768 [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true }, 769 [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true }, 770 [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true }, 771 [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true }, 772 [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true }, 773 [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true }, 774 [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true }, 775 [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true }, 776 [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true }, 777 [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true }, 778 [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true }, 779 [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true }, 780 [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true }, 781 [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true }, 782 [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true }, 783 [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true }, 784 [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true }, 785 [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true }, 786 [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true }, 787 [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true }, 788 [tegra_clk_i2c4] = { .dt_id = TEGRA124_CLK_I2C4, .present = true }, 789 [tegra_clk_sbc5] = { .dt_id = TEGRA124_CLK_SBC5, .present = true }, 790 [tegra_clk_sbc6] = { .dt_id = TEGRA124_CLK_SBC6, .present = true }, 791 [tegra_clk_d_audio] = { .dt_id = TEGRA124_CLK_D_AUDIO, .present = true }, 792 [tegra_clk_apbif] = { .dt_id = TEGRA124_CLK_APBIF, .present = true }, 793 [tegra_clk_dam0] = { .dt_id = TEGRA124_CLK_DAM0, .present = true }, 794 [tegra_clk_dam1] = { .dt_id = TEGRA124_CLK_DAM1, .present = true }, 795 [tegra_clk_dam2] = { .dt_id = TEGRA124_CLK_DAM2, .present = true }, 796 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA124_CLK_HDA2CODEC_2X, .present = true }, 797 [tegra_clk_audio0_2x] = { .dt_id = TEGRA124_CLK_AUDIO0_2X, .present = true }, 798 [tegra_clk_audio1_2x] = { .dt_id = TEGRA124_CLK_AUDIO1_2X, .present = true }, 799 [tegra_clk_audio2_2x] = { .dt_id = TEGRA124_CLK_AUDIO2_2X, .present = true }, 800 [tegra_clk_audio3_2x] = { .dt_id = TEGRA124_CLK_AUDIO3_2X, .present = true }, 801 [tegra_clk_audio4_2x] = { .dt_id = TEGRA124_CLK_AUDIO4_2X, .present = true }, 802 [tegra_clk_spdif_2x] = { .dt_id = TEGRA124_CLK_SPDIF_2X, .present = true }, 803 [tegra_clk_actmon] = { .dt_id = TEGRA124_CLK_ACTMON, .present = true }, 804 [tegra_clk_extern1] = { .dt_id = TEGRA124_CLK_EXTERN1, .present = true }, 805 [tegra_clk_extern2] = { .dt_id = TEGRA124_CLK_EXTERN2, .present = true }, 806 [tegra_clk_extern3] = { .dt_id = TEGRA124_CLK_EXTERN3, .present = true }, 807 [tegra_clk_sata_oob] = { .dt_id = TEGRA124_CLK_SATA_OOB, .present = true }, 808 [tegra_clk_sata] = { .dt_id = TEGRA124_CLK_SATA, .present = true }, 809 [tegra_clk_hda] = { .dt_id = TEGRA124_CLK_HDA, .present = true }, 810 [tegra_clk_se] = { .dt_id = TEGRA124_CLK_SE, .present = true }, 811 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA124_CLK_HDA2HDMI, .present = true }, 812 [tegra_clk_sata_cold] = { .dt_id = TEGRA124_CLK_SATA_COLD, .present = true }, 813 [tegra_clk_cilab] = { .dt_id = TEGRA124_CLK_CILAB, .present = true }, 814 [tegra_clk_cilcd] = { .dt_id = TEGRA124_CLK_CILCD, .present = true }, 815 [tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true }, 816 [tegra_clk_dsialp] = { .dt_id = TEGRA124_CLK_DSIALP, .present = true }, 817 [tegra_clk_dsiblp] = { .dt_id = TEGRA124_CLK_DSIBLP, .present = true }, 818 [tegra_clk_entropy] = { .dt_id = TEGRA124_CLK_ENTROPY, .present = true }, 819 [tegra_clk_dds] = { .dt_id = TEGRA124_CLK_DDS, .present = true }, 820 [tegra_clk_dp2] = { .dt_id = TEGRA124_CLK_DP2, .present = true }, 821 [tegra_clk_amx] = { .dt_id = TEGRA124_CLK_AMX, .present = true }, 822 [tegra_clk_adx] = { .dt_id = TEGRA124_CLK_ADX, .present = true }, 823 [tegra_clk_xusb_ss] = { .dt_id = TEGRA124_CLK_XUSB_SS, .present = true }, 824 [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true }, 825 [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true }, 826 [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true }, 827 [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true }, 828 [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true }, 829 [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true }, 830 [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true }, 831 [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true }, 832 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA124_CLK_SOR0_LVDS, .present = true }, 833 [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true }, 834 [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true }, 835 [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true }, 836 [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true }, 837 [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true }, 838 [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true }, 839 [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true }, 840 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true }, 841 [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true }, 842 [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true }, 843 [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true }, 844 [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true }, 845 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true }, 846 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true }, 847 [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true }, 848 [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true }, 849 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true }, 850 [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true }, 851 [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true }, 852 [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true }, 853 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA124_CLK_PLL_M_OUT1, .present = true }, 854 [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true }, 855 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA124_CLK_PLL_P_OUT1, .present = true }, 856 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA124_CLK_PLL_P_OUT2, .present = true }, 857 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA124_CLK_PLL_P_OUT3, .present = true }, 858 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA124_CLK_PLL_P_OUT4, .present = true }, 859 [tegra_clk_pll_a] = { .dt_id = TEGRA124_CLK_PLL_A, .present = true }, 860 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA124_CLK_PLL_A_OUT0, .present = true }, 861 [tegra_clk_pll_d] = { .dt_id = TEGRA124_CLK_PLL_D, .present = true }, 862 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA124_CLK_PLL_D_OUT0, .present = true }, 863 [tegra_clk_pll_d2] = { .dt_id = TEGRA124_CLK_PLL_D2, .present = true }, 864 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA124_CLK_PLL_D2_OUT0, .present = true }, 865 [tegra_clk_pll_u] = { .dt_id = TEGRA124_CLK_PLL_U, .present = true }, 866 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA124_CLK_PLL_U_480M, .present = true }, 867 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA124_CLK_PLL_U_60M, .present = true }, 868 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA124_CLK_PLL_U_48M, .present = true }, 869 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA124_CLK_PLL_U_12M, .present = true }, 870 [tegra_clk_pll_x] = { .dt_id = TEGRA124_CLK_PLL_X, .present = true }, 871 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA124_CLK_PLL_X_OUT0, .present = true }, 872 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA124_CLK_PLL_RE_VCO, .present = true }, 873 [tegra_clk_pll_re_out] = { .dt_id = TEGRA124_CLK_PLL_RE_OUT, .present = true }, 874 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC, .present = true }, 875 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA124_CLK_I2S0_SYNC, .present = true }, 876 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA124_CLK_I2S1_SYNC, .present = true }, 877 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA124_CLK_I2S2_SYNC, .present = true }, 878 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA124_CLK_I2S3_SYNC, .present = true }, 879 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA124_CLK_I2S4_SYNC, .present = true }, 880 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA124_CLK_VIMCLK_SYNC, .present = true }, 881 [tegra_clk_audio0] = { .dt_id = TEGRA124_CLK_AUDIO0, .present = true }, 882 [tegra_clk_audio1] = { .dt_id = TEGRA124_CLK_AUDIO1, .present = true }, 883 [tegra_clk_audio2] = { .dt_id = TEGRA124_CLK_AUDIO2, .present = true }, 884 [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true }, 885 [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true }, 886 [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true }, 887 [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true }, 888 [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true }, 889 [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true }, 890 [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true }, 891 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true }, 892 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true }, 893 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true }, 894 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true }, 895 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA124_CLK_XUSB_SS_DIV2, .present = true }, 896 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true }, 897 [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true }, 898 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true }, 899 [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true }, 900 [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true }, 901 [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true }, 902 [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true }, 903 [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true }, 904 [tegra_clk_dfll_ref] = { .dt_id = TEGRA124_CLK_DFLL_REF, .present = true }, 905 [tegra_clk_dfll_soc] = { .dt_id = TEGRA124_CLK_DFLL_SOC, .present = true }, 906 [tegra_clk_vi_sensor2] = { .dt_id = TEGRA124_CLK_VI_SENSOR2, .present = true }, 907 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA124_CLK_PLL_P_OUT5, .present = true }, 908 [tegra_clk_pll_c4] = { .dt_id = TEGRA124_CLK_PLL_C4, .present = true }, 909 [tegra_clk_pll_dp] = { .dt_id = TEGRA124_CLK_PLL_DP, .present = true }, 910 [tegra_clk_audio0_mux] = { .dt_id = TEGRA124_CLK_AUDIO0_MUX, .present = true }, 911 [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true }, 912 [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true }, 913 [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true }, 914 [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true }, 915 [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true }, 916 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true }, 917 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true }, 918 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true }, 919 [tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true }, 920 }; 921 922 static struct tegra_devclk devclks[] __initdata = { 923 { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M }, 924 { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF }, 925 { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K }, 926 { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 }, 927 { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 }, 928 { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C }, 929 { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 }, 930 { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 }, 931 { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 }, 932 { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P }, 933 { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 }, 934 { .con_id = "pll_p_out2", .dt_id = TEGRA124_CLK_PLL_P_OUT2 }, 935 { .con_id = "pll_p_out3", .dt_id = TEGRA124_CLK_PLL_P_OUT3 }, 936 { .con_id = "pll_p_out4", .dt_id = TEGRA124_CLK_PLL_P_OUT4 }, 937 { .con_id = "pll_m", .dt_id = TEGRA124_CLK_PLL_M }, 938 { .con_id = "pll_m_out1", .dt_id = TEGRA124_CLK_PLL_M_OUT1 }, 939 { .con_id = "pll_x", .dt_id = TEGRA124_CLK_PLL_X }, 940 { .con_id = "pll_x_out0", .dt_id = TEGRA124_CLK_PLL_X_OUT0 }, 941 { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U }, 942 { .con_id = "pll_u_480M", .dt_id = TEGRA124_CLK_PLL_U_480M }, 943 { .con_id = "pll_u_60M", .dt_id = TEGRA124_CLK_PLL_U_60M }, 944 { .con_id = "pll_u_48M", .dt_id = TEGRA124_CLK_PLL_U_48M }, 945 { .con_id = "pll_u_12M", .dt_id = TEGRA124_CLK_PLL_U_12M }, 946 { .con_id = "pll_d", .dt_id = TEGRA124_CLK_PLL_D }, 947 { .con_id = "pll_d_out0", .dt_id = TEGRA124_CLK_PLL_D_OUT0 }, 948 { .con_id = "pll_d2", .dt_id = TEGRA124_CLK_PLL_D2 }, 949 { .con_id = "pll_d2_out0", .dt_id = TEGRA124_CLK_PLL_D2_OUT0 }, 950 { .con_id = "pll_a", .dt_id = TEGRA124_CLK_PLL_A }, 951 { .con_id = "pll_a_out0", .dt_id = TEGRA124_CLK_PLL_A_OUT0 }, 952 { .con_id = "pll_re_vco", .dt_id = TEGRA124_CLK_PLL_RE_VCO }, 953 { .con_id = "pll_re_out", .dt_id = TEGRA124_CLK_PLL_RE_OUT }, 954 { .con_id = "spdif_in_sync", .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC }, 955 { .con_id = "i2s0_sync", .dt_id = TEGRA124_CLK_I2S0_SYNC }, 956 { .con_id = "i2s1_sync", .dt_id = TEGRA124_CLK_I2S1_SYNC }, 957 { .con_id = "i2s2_sync", .dt_id = TEGRA124_CLK_I2S2_SYNC }, 958 { .con_id = "i2s3_sync", .dt_id = TEGRA124_CLK_I2S3_SYNC }, 959 { .con_id = "i2s4_sync", .dt_id = TEGRA124_CLK_I2S4_SYNC }, 960 { .con_id = "vimclk_sync", .dt_id = TEGRA124_CLK_VIMCLK_SYNC }, 961 { .con_id = "audio0", .dt_id = TEGRA124_CLK_AUDIO0 }, 962 { .con_id = "audio1", .dt_id = TEGRA124_CLK_AUDIO1 }, 963 { .con_id = "audio2", .dt_id = TEGRA124_CLK_AUDIO2 }, 964 { .con_id = "audio3", .dt_id = TEGRA124_CLK_AUDIO3 }, 965 { .con_id = "audio4", .dt_id = TEGRA124_CLK_AUDIO4 }, 966 { .con_id = "spdif", .dt_id = TEGRA124_CLK_SPDIF }, 967 { .con_id = "audio0_2x", .dt_id = TEGRA124_CLK_AUDIO0_2X }, 968 { .con_id = "audio1_2x", .dt_id = TEGRA124_CLK_AUDIO1_2X }, 969 { .con_id = "audio2_2x", .dt_id = TEGRA124_CLK_AUDIO2_2X }, 970 { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X }, 971 { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X }, 972 { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X }, 973 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 }, 974 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 }, 975 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 }, 976 { .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK }, 977 { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G }, 978 { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP }, 979 { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK }, 980 { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK }, 981 { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK }, 982 { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE }, 983 { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC }, 984 { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER }, 985 { .con_id = "hda", .dt_id = TEGRA124_CLK_HDA }, 986 { .con_id = "hda2codec_2x", .dt_id = TEGRA124_CLK_HDA2CODEC_2X }, 987 { .con_id = "hda2hdmi", .dt_id = TEGRA124_CLK_HDA2HDMI }, 988 }; 989 990 static struct clk **clks; 991 992 static __init void tegra124_periph_clk_init(void __iomem *clk_base, 993 void __iomem *pmc_base) 994 { 995 struct clk *clk; 996 997 /* xusb_ss_div2 */ 998 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, 999 1, 2); 1000 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk; 1001 1002 clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, 1003 1, 17, 181); 1004 clks[TEGRA124_CLK_DPAUX] = clk; 1005 1006 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, 1007 clk_base + PLLD_MISC, 30, 0, &pll_d_lock); 1008 clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk; 1009 1010 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0, 1011 clk_base, 0, 48, 1012 periph_clk_enb_refcnt); 1013 clks[TEGRA124_CLK_DSIA] = clk; 1014 1015 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, 1016 clk_base, 0, 82, 1017 periph_clk_enb_refcnt); 1018 clks[TEGRA124_CLK_DSIB] = clk; 1019 1020 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, 1021 &emc_lock); 1022 clks[TEGRA124_CLK_MC] = clk; 1023 1024 /* cml0 */ 1025 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, 1026 0, 0, &pll_e_lock); 1027 clk_register_clkdev(clk, "cml0", NULL); 1028 clks[TEGRA124_CLK_CML0] = clk; 1029 1030 /* cml1 */ 1031 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, 1032 1, 0, &pll_e_lock); 1033 clk_register_clkdev(clk, "cml1", NULL); 1034 clks[TEGRA124_CLK_CML1] = clk; 1035 1036 tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params); 1037 } 1038 1039 static void __init tegra124_pll_init(void __iomem *clk_base, 1040 void __iomem *pmc) 1041 { 1042 struct clk *clk; 1043 1044 /* PLLC */ 1045 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, 1046 pmc, 0, &pll_c_params, NULL); 1047 clk_register_clkdev(clk, "pll_c", NULL); 1048 clks[TEGRA124_CLK_PLL_C] = clk; 1049 1050 /* PLLC_OUT1 */ 1051 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 1052 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1053 8, 8, 1, NULL); 1054 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 1055 clk_base + PLLC_OUT, 1, 0, 1056 CLK_SET_RATE_PARENT, 0, NULL); 1057 clk_register_clkdev(clk, "pll_c_out1", NULL); 1058 clks[TEGRA124_CLK_PLL_C_OUT1] = clk; 1059 1060 /* PLLC_UD */ 1061 clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c", 1062 CLK_SET_RATE_PARENT, 1, 1); 1063 clk_register_clkdev(clk, "pll_c_ud", NULL); 1064 clks[TEGRA124_CLK_PLL_C_UD] = clk; 1065 1066 /* PLLC2 */ 1067 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 1068 &pll_c2_params, NULL); 1069 clk_register_clkdev(clk, "pll_c2", NULL); 1070 clks[TEGRA124_CLK_PLL_C2] = clk; 1071 1072 /* PLLC3 */ 1073 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 1074 &pll_c3_params, NULL); 1075 clk_register_clkdev(clk, "pll_c3", NULL); 1076 clks[TEGRA124_CLK_PLL_C3] = clk; 1077 1078 /* PLLM */ 1079 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, 1080 CLK_SET_RATE_GATE, &pll_m_params, NULL); 1081 clk_register_clkdev(clk, "pll_m", NULL); 1082 clks[TEGRA124_CLK_PLL_M] = clk; 1083 1084 /* PLLM_OUT1 */ 1085 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 1086 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1087 8, 8, 1, NULL); 1088 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 1089 clk_base + PLLM_OUT, 1, 0, 1090 CLK_SET_RATE_PARENT, 0, NULL); 1091 clk_register_clkdev(clk, "pll_m_out1", NULL); 1092 clks[TEGRA124_CLK_PLL_M_OUT1] = clk; 1093 1094 /* PLLM_UD */ 1095 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 1096 CLK_SET_RATE_PARENT, 1, 1); 1097 clk_register_clkdev(clk, "pll_m_ud", NULL); 1098 clks[TEGRA124_CLK_PLL_M_UD] = clk; 1099 1100 /* PLLU */ 1101 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0, 1102 &pll_u_params, &pll_u_lock); 1103 clk_register_clkdev(clk, "pll_u", NULL); 1104 clks[TEGRA124_CLK_PLL_U] = clk; 1105 1106 /* PLLU_480M */ 1107 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", 1108 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 1109 22, 0, &pll_u_lock); 1110 clk_register_clkdev(clk, "pll_u_480M", NULL); 1111 clks[TEGRA124_CLK_PLL_U_480M] = clk; 1112 1113 /* PLLU_60M */ 1114 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", 1115 CLK_SET_RATE_PARENT, 1, 8); 1116 clk_register_clkdev(clk, "pll_u_60M", NULL); 1117 clks[TEGRA124_CLK_PLL_U_60M] = clk; 1118 1119 /* PLLU_48M */ 1120 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", 1121 CLK_SET_RATE_PARENT, 1, 10); 1122 clk_register_clkdev(clk, "pll_u_48M", NULL); 1123 clks[TEGRA124_CLK_PLL_U_48M] = clk; 1124 1125 /* PLLU_12M */ 1126 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", 1127 CLK_SET_RATE_PARENT, 1, 40); 1128 clk_register_clkdev(clk, "pll_u_12M", NULL); 1129 clks[TEGRA124_CLK_PLL_U_12M] = clk; 1130 1131 /* PLLD */ 1132 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, 1133 &pll_d_params, &pll_d_lock); 1134 clk_register_clkdev(clk, "pll_d", NULL); 1135 clks[TEGRA124_CLK_PLL_D] = clk; 1136 1137 /* PLLD_OUT0 */ 1138 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 1139 CLK_SET_RATE_PARENT, 1, 2); 1140 clk_register_clkdev(clk, "pll_d_out0", NULL); 1141 clks[TEGRA124_CLK_PLL_D_OUT0] = clk; 1142 1143 /* PLLRE */ 1144 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, 1145 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq); 1146 clk_register_clkdev(clk, "pll_re_vco", NULL); 1147 clks[TEGRA124_CLK_PLL_RE_VCO] = clk; 1148 1149 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, 1150 clk_base + PLLRE_BASE, 16, 4, 0, 1151 pll_re_div_table, &pll_re_lock); 1152 clk_register_clkdev(clk, "pll_re_out", NULL); 1153 clks[TEGRA124_CLK_PLL_RE_OUT] = clk; 1154 1155 /* PLLE */ 1156 clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref", 1157 clk_base, 0, &pll_e_params, NULL); 1158 clk_register_clkdev(clk, "pll_e", NULL); 1159 clks[TEGRA124_CLK_PLL_E] = clk; 1160 1161 /* PLLC4 */ 1162 clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0, 1163 &pll_c4_params, NULL); 1164 clk_register_clkdev(clk, "pll_c4", NULL); 1165 clks[TEGRA124_CLK_PLL_C4] = clk; 1166 1167 /* PLLDP */ 1168 clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0, 1169 &pll_dp_params, NULL); 1170 clk_register_clkdev(clk, "pll_dp", NULL); 1171 clks[TEGRA124_CLK_PLL_DP] = clk; 1172 1173 /* PLLD2 */ 1174 clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0, 1175 &tegra124_pll_d2_params, NULL); 1176 clk_register_clkdev(clk, "pll_d2", NULL); 1177 clks[TEGRA124_CLK_PLL_D2] = clk; 1178 1179 /* PLLD2_OUT0 */ 1180 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 1181 CLK_SET_RATE_PARENT, 1, 1); 1182 clk_register_clkdev(clk, "pll_d2_out0", NULL); 1183 clks[TEGRA124_CLK_PLL_D2_OUT0] = clk; 1184 1185 } 1186 1187 /* Tegra124 CPU clock and reset control functions */ 1188 static void tegra124_wait_cpu_in_reset(u32 cpu) 1189 { 1190 unsigned int reg; 1191 1192 do { 1193 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1194 cpu_relax(); 1195 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 1196 } 1197 1198 static void tegra124_disable_cpu_clock(u32 cpu) 1199 { 1200 /* flow controller would take care in the power sequence. */ 1201 } 1202 1203 #ifdef CONFIG_PM_SLEEP 1204 static void tegra124_cpu_clock_suspend(void) 1205 { 1206 /* switch coresite to clk_m, save off original source */ 1207 tegra124_cpu_clk_sctx.clk_csite_src = 1208 readl(clk_base + CLK_SOURCE_CSITE); 1209 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); 1210 1211 tegra124_cpu_clk_sctx.cclkg_burst = 1212 readl(clk_base + CCLKG_BURST_POLICY); 1213 tegra124_cpu_clk_sctx.cclkg_divider = 1214 readl(clk_base + CCLKG_BURST_POLICY + 4); 1215 } 1216 1217 static void tegra124_cpu_clock_resume(void) 1218 { 1219 writel(tegra124_cpu_clk_sctx.clk_csite_src, 1220 clk_base + CLK_SOURCE_CSITE); 1221 1222 writel(tegra124_cpu_clk_sctx.cclkg_burst, 1223 clk_base + CCLKG_BURST_POLICY); 1224 writel(tegra124_cpu_clk_sctx.cclkg_divider, 1225 clk_base + CCLKG_BURST_POLICY + 4); 1226 } 1227 #endif 1228 1229 static struct tegra_cpu_car_ops tegra124_cpu_car_ops = { 1230 .wait_for_reset = tegra124_wait_cpu_in_reset, 1231 .disable_clock = tegra124_disable_cpu_clock, 1232 #ifdef CONFIG_PM_SLEEP 1233 .suspend = tegra124_cpu_clock_suspend, 1234 .resume = tegra124_cpu_clock_resume, 1235 #endif 1236 }; 1237 1238 static const struct of_device_id pmc_match[] __initconst = { 1239 { .compatible = "nvidia,tegra124-pmc" }, 1240 { }, 1241 }; 1242 1243 static struct tegra_clk_init_table common_init_table[] __initdata = { 1244 { TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0 }, 1245 { TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 }, 1246 { TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 }, 1247 { TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 }, 1248 { TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 }, 1249 { TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 }, 1250 { TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 }, 1251 { TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1 }, 1252 { TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1 }, 1253 { TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, 1254 { TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, 1255 { TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, 1256 { TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, 1257 { TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, 1258 { TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_C3, 600000000, 0 }, 1259 { TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 }, 1260 { TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 }, 1261 { TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 }, 1262 { TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 0 }, 1263 { TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1 }, 1264 { TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1 }, 1265 { TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0 }, 1266 { TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0 }, 1267 { TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1 }, 1268 { TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0 }, 1269 { TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0 }, 1270 { TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0 }, 1271 { TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0 }, 1272 { TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0 }, 1273 { TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0 }, 1274 { TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0 }, 1275 { TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0 }, 1276 { TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0 }, 1277 { TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0 }, 1278 { TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 }, 1279 { TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 }, 1280 { TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 }, 1281 { TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 }, 1282 { TEGRA124_CLK_SPDIF_IN_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, 1283 { TEGRA124_CLK_I2S0_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, 1284 { TEGRA124_CLK_I2S1_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, 1285 { TEGRA124_CLK_I2S2_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, 1286 { TEGRA124_CLK_I2S3_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, 1287 { TEGRA124_CLK_I2S4_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, 1288 { TEGRA124_CLK_VIMCLK_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 }, 1289 /* must be the last entry */ 1290 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 }, 1291 }; 1292 1293 static struct tegra_clk_init_table tegra124_init_table[] __initdata = { 1294 { TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0 }, 1295 { TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1 }, 1296 { TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0 }, 1297 { TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0 }, 1298 /* must be the last entry */ 1299 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 }, 1300 }; 1301 1302 /* Tegra132 requires the SOC_THERM clock to remain active */ 1303 static struct tegra_clk_init_table tegra132_init_table[] __initdata = { 1304 { TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1 }, 1305 /* must be the last entry */ 1306 { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 }, 1307 }; 1308 1309 static struct tegra_audio_clk_info tegra124_audio_plls[] = { 1310 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" }, 1311 }; 1312 1313 /** 1314 * tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs 1315 * 1316 * Program an initial clock rate and enable or disable clocks needed 1317 * by the rest of the kernel, for Tegra124 SoCs. It is intended to be 1318 * called by assigning a pointer to it to tegra_clk_apply_init_table - 1319 * this will be called as an arch_initcall. No return value. 1320 */ 1321 static void __init tegra124_clock_apply_init_table(void) 1322 { 1323 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX); 1324 tegra_init_from_table(tegra124_init_table, clks, TEGRA124_CLK_CLK_MAX); 1325 } 1326 1327 /** 1328 * tegra124_car_barrier - wait for pending writes to the CAR to complete 1329 * 1330 * Wait for any outstanding writes to the CAR MMIO space from this CPU 1331 * to complete before continuing execution. No return value. 1332 */ 1333 static void tegra124_car_barrier(void) 1334 { 1335 readl_relaxed(clk_base + RST_DFLL_DVCO); 1336 } 1337 1338 /** 1339 * tegra124_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset 1340 * 1341 * Assert the reset line of the DFLL's DVCO. No return value. 1342 */ 1343 static void tegra124_clock_assert_dfll_dvco_reset(void) 1344 { 1345 u32 v; 1346 1347 v = readl_relaxed(clk_base + RST_DFLL_DVCO); 1348 v |= (1 << DVFS_DFLL_RESET_SHIFT); 1349 writel_relaxed(v, clk_base + RST_DFLL_DVCO); 1350 tegra124_car_barrier(); 1351 } 1352 1353 /** 1354 * tegra124_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset 1355 * 1356 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to 1357 * operate. No return value. 1358 */ 1359 static void tegra124_clock_deassert_dfll_dvco_reset(void) 1360 { 1361 u32 v; 1362 1363 v = readl_relaxed(clk_base + RST_DFLL_DVCO); 1364 v &= ~(1 << DVFS_DFLL_RESET_SHIFT); 1365 writel_relaxed(v, clk_base + RST_DFLL_DVCO); 1366 tegra124_car_barrier(); 1367 } 1368 1369 static int tegra124_reset_assert(unsigned long id) 1370 { 1371 if (id == TEGRA124_RST_DFLL_DVCO) 1372 tegra124_clock_assert_dfll_dvco_reset(); 1373 else 1374 return -EINVAL; 1375 1376 return 0; 1377 } 1378 1379 static int tegra124_reset_deassert(unsigned long id) 1380 { 1381 if (id == TEGRA124_RST_DFLL_DVCO) 1382 tegra124_clock_deassert_dfll_dvco_reset(); 1383 else 1384 return -EINVAL; 1385 1386 return 0; 1387 } 1388 1389 /** 1390 * tegra132_clock_apply_init_table - initialize clocks on Tegra132 SoCs 1391 * 1392 * Program an initial clock rate and enable or disable clocks needed 1393 * by the rest of the kernel, for Tegra132 SoCs. It is intended to be 1394 * called by assigning a pointer to it to tegra_clk_apply_init_table - 1395 * this will be called as an arch_initcall. No return value. 1396 */ 1397 static void __init tegra132_clock_apply_init_table(void) 1398 { 1399 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX); 1400 tegra_init_from_table(tegra132_init_table, clks, TEGRA124_CLK_CLK_MAX); 1401 } 1402 1403 /** 1404 * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132 1405 * @np: struct device_node * of the DT node for the SoC CAR IP block 1406 * 1407 * Register most of the clocks controlled by the CAR IP block, along 1408 * with a few clocks controlled by the PMC IP block. Everything in 1409 * this function should be common to Tegra124 and Tegra132. XXX The 1410 * PMC clock initialization should probably be moved to PMC-specific 1411 * driver code. No return value. 1412 */ 1413 static void __init tegra124_132_clock_init_pre(struct device_node *np) 1414 { 1415 struct device_node *node; 1416 u32 plld_base; 1417 1418 clk_base = of_iomap(np, 0); 1419 if (!clk_base) { 1420 pr_err("ioremap tegra124/tegra132 CAR failed\n"); 1421 return; 1422 } 1423 1424 node = of_find_matching_node(NULL, pmc_match); 1425 if (!node) { 1426 pr_err("Failed to find pmc node\n"); 1427 WARN_ON(1); 1428 return; 1429 } 1430 1431 pmc_base = of_iomap(node, 0); 1432 if (!pmc_base) { 1433 pr_err("Can't map pmc registers\n"); 1434 WARN_ON(1); 1435 return; 1436 } 1437 1438 clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 1439 TEGRA124_CAR_BANK_COUNT); 1440 if (!clks) 1441 return; 1442 1443 if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq, 1444 ARRAY_SIZE(tegra124_input_freq), 1, &osc_freq, 1445 &pll_ref_freq) < 0) 1446 return; 1447 1448 tegra_fixed_clk_init(tegra124_clks); 1449 tegra124_pll_init(clk_base, pmc_base); 1450 tegra124_periph_clk_init(clk_base, pmc_base); 1451 tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, 1452 tegra124_audio_plls, 1453 ARRAY_SIZE(tegra124_audio_plls), 24576000); 1454 tegra_pmc_clk_init(pmc_base, tegra124_clks); 1455 1456 /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */ 1457 plld_base = readl(clk_base + PLLD_BASE); 1458 plld_base &= ~BIT(25); 1459 writel(plld_base, clk_base + PLLD_BASE); 1460 } 1461 1462 /** 1463 * tegra124_132_clock_init_post - clock initialization postamble for T124/T132 1464 * @np: struct device_node * of the DT node for the SoC CAR IP block 1465 * 1466 * Register most of the along with a few clocks controlled by the PMC 1467 * IP block. Everything in this function should be common to Tegra124 1468 * and Tegra132. This function must be called after 1469 * tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will 1470 * not be set. No return value. 1471 */ 1472 static void __init tegra124_132_clock_init_post(struct device_node *np) 1473 { 1474 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks, 1475 &pll_x_params); 1476 tegra_init_special_resets(1, tegra124_reset_assert, 1477 tegra124_reset_deassert); 1478 tegra_add_of_provider(np, of_clk_src_onecell_get); 1479 1480 clks[TEGRA124_CLK_EMC] = tegra_clk_register_emc(clk_base, np, 1481 &emc_lock); 1482 1483 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1484 1485 tegra_cpu_car_ops = &tegra124_cpu_car_ops; 1486 } 1487 1488 /** 1489 * tegra124_clock_init - Tegra124-specific clock initialization 1490 * @np: struct device_node * of the DT node for the SoC CAR IP block 1491 * 1492 * Register most SoC clocks for the Tegra124 system-on-chip. Most of 1493 * this code is shared between the Tegra124 and Tegra132 SoCs, 1494 * although some of the initial clock settings and CPU clocks differ. 1495 * Intended to be called by the OF init code when a DT node with the 1496 * "nvidia,tegra124-car" string is encountered, and declared with 1497 * CLK_OF_DECLARE. No return value. 1498 */ 1499 static void __init tegra124_clock_init(struct device_node *np) 1500 { 1501 tegra124_132_clock_init_pre(np); 1502 tegra_clk_apply_init_table = tegra124_clock_apply_init_table; 1503 tegra124_132_clock_init_post(np); 1504 } 1505 1506 /** 1507 * tegra132_clock_init - Tegra132-specific clock initialization 1508 * @np: struct device_node * of the DT node for the SoC CAR IP block 1509 * 1510 * Register most SoC clocks for the Tegra132 system-on-chip. Most of 1511 * this code is shared between the Tegra124 and Tegra132 SoCs, 1512 * although some of the initial clock settings and CPU clocks differ. 1513 * Intended to be called by the OF init code when a DT node with the 1514 * "nvidia,tegra132-car" string is encountered, and declared with 1515 * CLK_OF_DECLARE. No return value. 1516 */ 1517 static void __init tegra132_clock_init(struct device_node *np) 1518 { 1519 tegra124_132_clock_init_pre(np); 1520 1521 /* 1522 * On Tegra132, these clocks are controlled by the 1523 * CLUSTER_clocks IP block, located in the CPU complex 1524 */ 1525 tegra124_clks[tegra_clk_cclk_g].present = false; 1526 tegra124_clks[tegra_clk_cclk_lp].present = false; 1527 tegra124_clks[tegra_clk_pll_x].present = false; 1528 tegra124_clks[tegra_clk_pll_x_out0].present = false; 1529 1530 tegra_clk_apply_init_table = tegra132_clock_apply_init_table; 1531 tegra124_132_clock_init_post(np); 1532 } 1533 CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init); 1534 CLK_OF_DECLARE(tegra132, "nvidia,tegra132-car", tegra132_clock_init); 1535