1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014 Free Electrons 4 * 5 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> 6 * 7 * Allwinner A31 APB0 clock driver 8 */ 9 10 #include <linux/clk-provider.h> 11 #include <linux/init.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 15 /* 16 * The APB0 clk has a configurable divisor. 17 * 18 * We must use a clk_div_table and not a regular power of 2 19 * divisor here, because the first 2 values divide the clock 20 * by 2. 21 */ 22 static const struct clk_div_table sun6i_a31_apb0_divs[] = { 23 { .val = 0, .div = 2, }, 24 { .val = 1, .div = 2, }, 25 { .val = 2, .div = 4, }, 26 { .val = 3, .div = 8, }, 27 { /* sentinel */ }, 28 }; 29 30 static int sun6i_a31_apb0_clk_probe(struct platform_device *pdev) 31 { 32 struct device_node *np = pdev->dev.of_node; 33 const char *clk_name = np->name; 34 const char *clk_parent; 35 void __iomem *reg; 36 struct clk *clk; 37 38 reg = devm_platform_ioremap_resource(pdev, 0); 39 if (IS_ERR(reg)) 40 return PTR_ERR(reg); 41 42 clk_parent = of_clk_get_parent_name(np, 0); 43 if (!clk_parent) 44 return -EINVAL; 45 46 of_property_read_string(np, "clock-output-names", &clk_name); 47 48 clk = clk_register_divider_table(&pdev->dev, clk_name, clk_parent, 49 0, reg, 0, 2, 0, sun6i_a31_apb0_divs, 50 NULL); 51 if (IS_ERR(clk)) 52 return PTR_ERR(clk); 53 54 return of_clk_add_provider(np, of_clk_src_simple_get, clk); 55 } 56 57 static const struct of_device_id sun6i_a31_apb0_clk_dt_ids[] = { 58 { .compatible = "allwinner,sun6i-a31-apb0-clk" }, 59 { /* sentinel */ } 60 }; 61 62 static struct platform_driver sun6i_a31_apb0_clk_driver = { 63 .driver = { 64 .name = "sun6i-a31-apb0-clk", 65 .of_match_table = sun6i_a31_apb0_clk_dt_ids, 66 }, 67 .probe = sun6i_a31_apb0_clk_probe, 68 }; 69 builtin_platform_driver(sun6i_a31_apb0_clk_driver); 70