1 /* 2 * Copyright 2013 Emilio López 3 * Emilio López <emilio@elopez.com.ar> 4 * 5 * Copyright 2013 Chen-Yu Tsai 6 * Chen-Yu Tsai <wens@csie.org> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/clk-provider.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/slab.h> 23 24 static DEFINE_SPINLOCK(gmac_lock); 25 26 /** 27 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module 28 * 29 * This clock looks something like this 30 * ________________________ 31 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core 32 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY 33 * Ext. 125MHz RGMII TX clk >--|__divider__/ | 34 * |________________________| 35 * 36 * The external 125 MHz reference is optional, i.e. GMAC can use its 37 * internal TX clock just fine. The A31 GMAC clock module does not have 38 * the divider controls for the external reference. 39 * 40 * To keep it simple, let the GMAC use either the MII TX clock for MII mode, 41 * and its internal TX clock for GMII and RGMII modes. The GMAC driver should 42 * select the appropriate source and gate/ungate the output to the PHY. 43 * 44 * Only the GMAC should use this clock. Altering the clock so that it doesn't 45 * match the GMAC's operation parameters will result in the GMAC not being 46 * able to send traffic out. The GMAC driver should set the clock rate and 47 * enable/disable this clock to configure the required state. The clock 48 * driver then responds by auto-reparenting the clock. 49 */ 50 51 #define SUN7I_A20_GMAC_GPIT 2 52 #define SUN7I_A20_GMAC_MASK 0x3 53 #define SUN7I_A20_GMAC_PARENTS 2 54 55 static u32 sun7i_a20_gmac_mux_table[SUN7I_A20_GMAC_PARENTS] = { 56 0x00, /* Select mii_phy_tx_clk */ 57 0x02, /* Select gmac_int_tx_clk */ 58 }; 59 60 static void __init sun7i_a20_gmac_clk_setup(struct device_node *node) 61 { 62 struct clk *clk; 63 struct clk_mux *mux; 64 struct clk_gate *gate; 65 const char *clk_name = node->name; 66 const char *parents[SUN7I_A20_GMAC_PARENTS]; 67 void __iomem *reg; 68 69 if (of_property_read_string(node, "clock-output-names", &clk_name)) 70 return; 71 72 /* allocate mux and gate clock structs */ 73 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); 74 if (!mux) 75 return; 76 77 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); 78 if (!gate) 79 goto free_mux; 80 81 /* gmac clock requires exactly 2 parents */ 82 if (of_clk_parent_fill(node, parents, 2) != 2) 83 goto free_gate; 84 85 reg = of_iomap(node, 0); 86 if (!reg) 87 goto free_gate; 88 89 /* set up gate and fixed rate properties */ 90 gate->reg = reg; 91 gate->bit_idx = SUN7I_A20_GMAC_GPIT; 92 gate->lock = &gmac_lock; 93 mux->reg = reg; 94 mux->mask = SUN7I_A20_GMAC_MASK; 95 mux->table = sun7i_a20_gmac_mux_table; 96 mux->lock = &gmac_lock; 97 98 clk = clk_register_composite(NULL, clk_name, 99 parents, SUN7I_A20_GMAC_PARENTS, 100 &mux->hw, &clk_mux_ops, 101 NULL, NULL, 102 &gate->hw, &clk_gate_ops, 103 0); 104 105 if (IS_ERR(clk)) 106 goto iounmap_reg; 107 108 of_clk_add_provider(node, of_clk_src_simple_get, clk); 109 110 return; 111 112 iounmap_reg: 113 iounmap(reg); 114 free_gate: 115 kfree(gate); 116 free_mux: 117 kfree(mux); 118 } 119 CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk", 120 sun7i_a20_gmac_clk_setup); 121