1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 Maxime Ripard 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/io.h> 9 10 #include "ccu_gate.h" 11 #include "ccu_mp.h" 12 13 static unsigned int next_div(unsigned int div, bool shift) 14 { 15 if (shift) 16 return div << 1; 17 return div + 1; 18 } 19 20 static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate, 21 unsigned int max_m, unsigned int max_p, 22 bool shift, 23 unsigned int *m, unsigned int *p) 24 { 25 unsigned long best_rate = 0; 26 unsigned int best_m = 0, best_p = 0; 27 unsigned int _m, _p; 28 29 for (_p = 1; _p <= max_p; _p = next_div(_p, shift)) { 30 for (_m = 1; _m <= max_m; _m++) { 31 unsigned long tmp_rate = parent / _p / _m; 32 33 if (tmp_rate > rate) 34 continue; 35 36 if ((rate - tmp_rate) < (rate - best_rate)) { 37 best_rate = tmp_rate; 38 best_m = _m; 39 best_p = _p; 40 } 41 } 42 } 43 44 *m = best_m; 45 *p = best_p; 46 47 return best_rate; 48 } 49 50 static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw, 51 unsigned long *parent, 52 unsigned long rate, 53 unsigned int max_m, 54 unsigned int max_p, 55 bool shift) 56 { 57 unsigned long parent_rate_saved; 58 unsigned long parent_rate, now; 59 unsigned long best_rate = 0; 60 unsigned int _m, _p, div; 61 unsigned long maxdiv; 62 63 parent_rate_saved = *parent; 64 65 /* 66 * The maximum divider we can use without overflowing 67 * unsigned long in rate * m * p below 68 */ 69 maxdiv = max_m * max_p; 70 maxdiv = min(ULONG_MAX / rate, maxdiv); 71 72 for (_p = 1; _p <= max_p; _p = next_div(_p, shift)) { 73 for (_m = 1; _m <= max_m; _m++) { 74 div = _m * _p; 75 76 if (div > maxdiv) 77 break; 78 79 if (rate * div == parent_rate_saved) { 80 /* 81 * It's the most ideal case if the requested 82 * rate can be divided from parent clock without 83 * needing to change parent rate, so return the 84 * divider immediately. 85 */ 86 *parent = parent_rate_saved; 87 return rate; 88 } 89 90 parent_rate = clk_hw_round_rate(hw, rate * div); 91 now = parent_rate / div; 92 93 if (now <= rate && now > best_rate) { 94 best_rate = now; 95 *parent = parent_rate; 96 97 if (now == rate) 98 return rate; 99 } 100 } 101 } 102 103 return best_rate; 104 } 105 106 static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux, 107 struct clk_hw *hw, 108 unsigned long *parent_rate, 109 unsigned long rate, 110 void *data) 111 { 112 struct ccu_mp *cmp = data; 113 unsigned int max_m, max_p; 114 unsigned int m, p; 115 bool shift = true; 116 117 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV) 118 rate *= cmp->fixed_post_div; 119 120 if (cmp->common.features & CCU_FEATURE_DUAL_DIV) 121 shift = false; 122 123 max_m = cmp->m.max ?: 1 << cmp->m.width; 124 if (shift) 125 max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); 126 else 127 max_p = cmp->p.max ?: 1 << cmp->p.width; 128 129 if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) { 130 rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, shift, 131 &m, &p); 132 } else { 133 rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate, 134 max_m, max_p, shift); 135 } 136 137 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV) 138 rate /= cmp->fixed_post_div; 139 140 return rate; 141 } 142 143 static void ccu_mp_disable(struct clk_hw *hw) 144 { 145 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 146 147 return ccu_gate_helper_disable(&cmp->common, cmp->enable); 148 } 149 150 static int ccu_mp_enable(struct clk_hw *hw) 151 { 152 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 153 154 return ccu_gate_helper_enable(&cmp->common, cmp->enable); 155 } 156 157 static int ccu_mp_is_enabled(struct clk_hw *hw) 158 { 159 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 160 161 return ccu_gate_helper_is_enabled(&cmp->common, cmp->enable); 162 } 163 164 static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw, 165 unsigned long parent_rate) 166 { 167 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 168 unsigned long rate; 169 unsigned int m, p; 170 u32 reg; 171 172 /* Adjust parent_rate according to pre-dividers */ 173 parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1, 174 parent_rate); 175 176 reg = readl(cmp->common.base + cmp->common.reg); 177 178 m = reg >> cmp->m.shift; 179 m &= (1 << cmp->m.width) - 1; 180 m += cmp->m.offset; 181 if (!m) 182 m++; 183 184 p = reg >> cmp->p.shift; 185 p &= (1 << cmp->p.width) - 1; 186 187 if (cmp->common.features & CCU_FEATURE_DUAL_DIV) 188 rate = (parent_rate / p) / m; 189 else 190 rate = (parent_rate >> p) / m; 191 192 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV) 193 rate /= cmp->fixed_post_div; 194 195 return rate; 196 } 197 198 static int ccu_mp_determine_rate(struct clk_hw *hw, 199 struct clk_rate_request *req) 200 { 201 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 202 203 return ccu_mux_helper_determine_rate(&cmp->common, &cmp->mux, 204 req, ccu_mp_round_rate, cmp); 205 } 206 207 static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate, 208 unsigned long parent_rate) 209 { 210 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 211 unsigned long flags; 212 unsigned int max_m, max_p; 213 unsigned int m, p; 214 bool shift = true; 215 u32 reg; 216 217 if (cmp->common.features & CCU_FEATURE_DUAL_DIV) 218 shift = false; 219 220 /* Adjust parent_rate according to pre-dividers */ 221 parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1, 222 parent_rate); 223 224 max_m = cmp->m.max ?: 1 << cmp->m.width; 225 if (shift) 226 max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); 227 else 228 max_p = cmp->p.max ?: 1 << cmp->p.width; 229 230 /* Adjust target rate according to post-dividers */ 231 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV) 232 rate = rate * cmp->fixed_post_div; 233 234 ccu_mp_find_best(parent_rate, rate, max_m, max_p, shift, &m, &p); 235 236 spin_lock_irqsave(cmp->common.lock, flags); 237 238 reg = readl(cmp->common.base + cmp->common.reg); 239 reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift); 240 reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift); 241 reg |= (m - cmp->m.offset) << cmp->m.shift; 242 if (shift) 243 reg |= ilog2(p) << cmp->p.shift; 244 else 245 reg |= (p - cmp->p.offset) << cmp->p.shift; 246 247 writel(reg, cmp->common.base + cmp->common.reg); 248 249 spin_unlock_irqrestore(cmp->common.lock, flags); 250 251 return 0; 252 } 253 254 static u8 ccu_mp_get_parent(struct clk_hw *hw) 255 { 256 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 257 258 return ccu_mux_helper_get_parent(&cmp->common, &cmp->mux); 259 } 260 261 static int ccu_mp_set_parent(struct clk_hw *hw, u8 index) 262 { 263 struct ccu_mp *cmp = hw_to_ccu_mp(hw); 264 265 return ccu_mux_helper_set_parent(&cmp->common, &cmp->mux, index); 266 } 267 268 const struct clk_ops ccu_mp_ops = { 269 .disable = ccu_mp_disable, 270 .enable = ccu_mp_enable, 271 .is_enabled = ccu_mp_is_enabled, 272 273 .get_parent = ccu_mp_get_parent, 274 .set_parent = ccu_mp_set_parent, 275 276 .determine_rate = ccu_mp_determine_rate, 277 .recalc_rate = ccu_mp_recalc_rate, 278 .set_rate = ccu_mp_set_rate, 279 }; 280 EXPORT_SYMBOL_NS_GPL(ccu_mp_ops, "SUNXI_CCU"); 281 282 /* 283 * Support for MMC timing mode switching 284 * 285 * The MMC clocks on some SoCs support switching between old and 286 * new timing modes. A platform specific API is provided to query 287 * and set the timing mode on supported SoCs. 288 * 289 * In addition, a special class of ccu_mp_ops is provided, which 290 * takes in to account the timing mode switch. When the new timing 291 * mode is active, the clock output rate is halved. This new class 292 * is a wrapper around the generic ccu_mp_ops. When clock rates 293 * are passed through to ccu_mp_ops callbacks, they are doubled 294 * if the new timing mode bit is set, to account for the post 295 * divider. Conversely, when clock rates are passed back, they 296 * are halved if the mode bit is set. 297 */ 298 299 static unsigned long ccu_mp_mmc_recalc_rate(struct clk_hw *hw, 300 unsigned long parent_rate) 301 { 302 unsigned long rate = ccu_mp_recalc_rate(hw, parent_rate); 303 struct ccu_common *cm = hw_to_ccu_common(hw); 304 u32 val = readl(cm->base + cm->reg); 305 306 if (val & CCU_MMC_NEW_TIMING_MODE) 307 return rate / 2; 308 return rate; 309 } 310 311 static int ccu_mp_mmc_determine_rate(struct clk_hw *hw, 312 struct clk_rate_request *req) 313 { 314 struct ccu_common *cm = hw_to_ccu_common(hw); 315 u32 val = readl(cm->base + cm->reg); 316 int ret; 317 318 /* adjust the requested clock rate */ 319 if (val & CCU_MMC_NEW_TIMING_MODE) { 320 req->rate *= 2; 321 req->min_rate *= 2; 322 req->max_rate *= 2; 323 } 324 325 ret = ccu_mp_determine_rate(hw, req); 326 327 /* re-adjust the requested clock rate back */ 328 if (val & CCU_MMC_NEW_TIMING_MODE) { 329 req->rate /= 2; 330 req->min_rate /= 2; 331 req->max_rate /= 2; 332 } 333 334 return ret; 335 } 336 337 static int ccu_mp_mmc_set_rate(struct clk_hw *hw, unsigned long rate, 338 unsigned long parent_rate) 339 { 340 struct ccu_common *cm = hw_to_ccu_common(hw); 341 u32 val = readl(cm->base + cm->reg); 342 343 if (val & CCU_MMC_NEW_TIMING_MODE) 344 rate *= 2; 345 346 return ccu_mp_set_rate(hw, rate, parent_rate); 347 } 348 349 const struct clk_ops ccu_mp_mmc_ops = { 350 .disable = ccu_mp_disable, 351 .enable = ccu_mp_enable, 352 .is_enabled = ccu_mp_is_enabled, 353 354 .get_parent = ccu_mp_get_parent, 355 .set_parent = ccu_mp_set_parent, 356 357 .determine_rate = ccu_mp_mmc_determine_rate, 358 .recalc_rate = ccu_mp_mmc_recalc_rate, 359 .set_rate = ccu_mp_mmc_set_rate, 360 }; 361 EXPORT_SYMBOL_NS_GPL(ccu_mp_mmc_ops, "SUNXI_CCU"); 362