xref: /linux/drivers/clk/sunxi-ng/ccu-sun9i-a80.h (revision c942fddf8793b2013be8c901b47d0a8dc02bf99f)
1*c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
2b8eb71dcSChen-Yu Tsai /*
3b8eb71dcSChen-Yu Tsai  * Copyright 2016 Chen-Yu Tsai
4b8eb71dcSChen-Yu Tsai  *
5b8eb71dcSChen-Yu Tsai  * Chen-Yu Tsai <wens@csie.org>
6b8eb71dcSChen-Yu Tsai  */
7b8eb71dcSChen-Yu Tsai 
8b8eb71dcSChen-Yu Tsai #ifndef _CCU_SUN9I_A80_H_
9b8eb71dcSChen-Yu Tsai #define _CCU_SUN9I_A80_H_
10b8eb71dcSChen-Yu Tsai 
11b8eb71dcSChen-Yu Tsai #include <dt-bindings/clock/sun9i-a80-ccu.h>
12b8eb71dcSChen-Yu Tsai #include <dt-bindings/reset/sun9i-a80-ccu.h>
13b8eb71dcSChen-Yu Tsai 
14b8eb71dcSChen-Yu Tsai #define CLK_PLL_C0CPUX		0
15b8eb71dcSChen-Yu Tsai #define CLK_PLL_C1CPUX		1
16b8eb71dcSChen-Yu Tsai 
17b8eb71dcSChen-Yu Tsai /* pll-audio and pll-periph0 are exported to the PRCM block */
18b8eb71dcSChen-Yu Tsai 
19b8eb71dcSChen-Yu Tsai #define CLK_PLL_VE		4
20b8eb71dcSChen-Yu Tsai #define CLK_PLL_DDR		5
21b8eb71dcSChen-Yu Tsai #define CLK_PLL_VIDEO0		6
22b8eb71dcSChen-Yu Tsai #define CLK_PLL_VIDEO1		7
23b8eb71dcSChen-Yu Tsai #define CLK_PLL_GPU		8
24b8eb71dcSChen-Yu Tsai #define CLK_PLL_DE		9
25b8eb71dcSChen-Yu Tsai #define CLK_PLL_ISP		10
26b8eb71dcSChen-Yu Tsai #define CLK_PLL_PERIPH1		11
27b8eb71dcSChen-Yu Tsai 
28b8eb71dcSChen-Yu Tsai /* The CPUX clocks are exported */
29b8eb71dcSChen-Yu Tsai 
30b8eb71dcSChen-Yu Tsai #define CLK_ATB0		14
31b8eb71dcSChen-Yu Tsai #define CLK_AXI0		15
32b8eb71dcSChen-Yu Tsai #define CLK_ATB1		16
33b8eb71dcSChen-Yu Tsai #define CLK_AXI1		17
34b8eb71dcSChen-Yu Tsai #define CLK_GTBUS		18
35b8eb71dcSChen-Yu Tsai #define CLK_AHB0		19
36b8eb71dcSChen-Yu Tsai #define CLK_AHB1		20
37b8eb71dcSChen-Yu Tsai #define CLK_AHB2		21
38b8eb71dcSChen-Yu Tsai #define CLK_APB0		22
39b8eb71dcSChen-Yu Tsai #define CLK_APB1		23
40b8eb71dcSChen-Yu Tsai #define CLK_CCI400		24
41b8eb71dcSChen-Yu Tsai #define CLK_ATS			25
42b8eb71dcSChen-Yu Tsai #define CLK_TRACE		26
43b8eb71dcSChen-Yu Tsai 
44b8eb71dcSChen-Yu Tsai /* module clocks and bus gates exported */
45b8eb71dcSChen-Yu Tsai 
46b8eb71dcSChen-Yu Tsai #define CLK_NUMBER		(CLK_BUS_UART5 + 1)
47b8eb71dcSChen-Yu Tsai 
48b8eb71dcSChen-Yu Tsai #endif /* _CCU_SUN9I_A80_H_ */
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