1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/platform_device.h> 10 11 #include "ccu_common.h" 12 #include "ccu_reset.h" 13 14 #include "ccu_div.h" 15 #include "ccu_gate.h" 16 #include "ccu_mp.h" 17 #include "ccu_nm.h" 18 19 #include "ccu-sun8i-r.h" 20 21 static const struct clk_parent_data ar100_parents[] = { 22 { .fw_name = "losc" }, 23 { .fw_name = "hosc" }, 24 { .fw_name = "pll-periph" }, 25 { .fw_name = "iosc" }, 26 }; 27 28 static const struct ccu_mux_var_prediv ar100_predivs[] = { 29 { .index = 2, .shift = 8, .width = 5 }, 30 }; 31 32 static struct ccu_div ar100_clk = { 33 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 34 35 .mux = { 36 .shift = 16, 37 .width = 2, 38 39 .var_predivs = ar100_predivs, 40 .n_var_predivs = ARRAY_SIZE(ar100_predivs), 41 }, 42 43 .common = { 44 .reg = 0x00, 45 .features = CCU_FEATURE_VARIABLE_PREDIV, 46 .hw.init = CLK_HW_INIT_PARENTS_DATA("ar100", 47 ar100_parents, 48 &ccu_div_ops, 49 0), 50 }, 51 }; 52 53 static CLK_FIXED_FACTOR_HW(ahb0_clk, "ahb0", &ar100_clk.common.hw, 1, 1, 0); 54 55 static SUNXI_CCU_M(apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0); 56 57 /* 58 * Define the parent as an array that can be reused to save space 59 * instead of having compound literals for each gate. Also have it 60 * non-const so we can change it on the A83T. 61 */ 62 static const struct clk_hw *apb0_gate_parent[] = { &apb0_clk.common.hw }; 63 static SUNXI_CCU_GATE_HWS(apb0_pio_clk, "apb0-pio", 64 apb0_gate_parent, 0x28, BIT(0), 0); 65 static SUNXI_CCU_GATE_HWS(apb0_ir_clk, "apb0-ir", 66 apb0_gate_parent, 0x28, BIT(1), 0); 67 static SUNXI_CCU_GATE_HWS(apb0_timer_clk, "apb0-timer", 68 apb0_gate_parent, 0x28, BIT(2), 0); 69 static SUNXI_CCU_GATE_HWS(apb0_rsb_clk, "apb0-rsb", 70 apb0_gate_parent, 0x28, BIT(3), 0); 71 static SUNXI_CCU_GATE_HWS(apb0_uart_clk, "apb0-uart", 72 apb0_gate_parent, 0x28, BIT(4), 0); 73 static SUNXI_CCU_GATE_HWS(apb0_i2c_clk, "apb0-i2c", 74 apb0_gate_parent, 0x28, BIT(6), 0); 75 static SUNXI_CCU_GATE_HWS(apb0_twd_clk, "apb0-twd", 76 apb0_gate_parent, 0x28, BIT(7), 0); 77 78 static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" }; 79 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", 80 r_mod0_default_parents, 0x54, 81 0, 4, /* M */ 82 16, 2, /* P */ 83 24, 2, /* mux */ 84 BIT(31), /* gate */ 85 0); 86 87 static const struct clk_parent_data a83t_r_mod0_parents[] = { 88 { .fw_name = "iosc" }, 89 { .fw_name = "hosc" }, 90 }; 91 static const struct ccu_mux_fixed_prediv a83t_ir_predivs[] = { 92 { .index = 0, .div = 16 }, 93 }; 94 static struct ccu_mp a83t_ir_clk = { 95 .enable = BIT(31), 96 97 .m = _SUNXI_CCU_DIV(0, 4), 98 .p = _SUNXI_CCU_DIV(16, 2), 99 100 .mux = { 101 .shift = 24, 102 .width = 2, 103 .fixed_predivs = a83t_ir_predivs, 104 .n_predivs = ARRAY_SIZE(a83t_ir_predivs), 105 }, 106 107 .common = { 108 .reg = 0x54, 109 .features = CCU_FEATURE_VARIABLE_PREDIV, 110 .hw.init = CLK_HW_INIT_PARENTS_DATA("ir", 111 a83t_r_mod0_parents, 112 &ccu_mp_ops, 113 0), 114 }, 115 }; 116 117 static struct ccu_common *sun8i_a83t_r_ccu_clks[] = { 118 &ar100_clk.common, 119 &apb0_clk.common, 120 &apb0_pio_clk.common, 121 &apb0_ir_clk.common, 122 &apb0_timer_clk.common, 123 &apb0_rsb_clk.common, 124 &apb0_uart_clk.common, 125 &apb0_i2c_clk.common, 126 &apb0_twd_clk.common, 127 &a83t_ir_clk.common, 128 }; 129 130 static struct ccu_common *sun8i_h3_r_ccu_clks[] = { 131 &ar100_clk.common, 132 &apb0_clk.common, 133 &apb0_pio_clk.common, 134 &apb0_ir_clk.common, 135 &apb0_timer_clk.common, 136 &apb0_uart_clk.common, 137 &apb0_i2c_clk.common, 138 &apb0_twd_clk.common, 139 &ir_clk.common, 140 }; 141 142 static struct ccu_common *sun50i_a64_r_ccu_clks[] = { 143 &ar100_clk.common, 144 &apb0_clk.common, 145 &apb0_pio_clk.common, 146 &apb0_ir_clk.common, 147 &apb0_timer_clk.common, 148 &apb0_rsb_clk.common, 149 &apb0_uart_clk.common, 150 &apb0_i2c_clk.common, 151 &apb0_twd_clk.common, 152 &ir_clk.common, 153 }; 154 155 static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = { 156 .hws = { 157 [CLK_AR100] = &ar100_clk.common.hw, 158 [CLK_AHB0] = &ahb0_clk.hw, 159 [CLK_APB0] = &apb0_clk.common.hw, 160 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 161 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 162 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 163 [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw, 164 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 165 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 166 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 167 [CLK_IR] = &a83t_ir_clk.common.hw, 168 }, 169 .num = CLK_NUMBER, 170 }; 171 172 static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = { 173 .hws = { 174 [CLK_AR100] = &ar100_clk.common.hw, 175 [CLK_AHB0] = &ahb0_clk.hw, 176 [CLK_APB0] = &apb0_clk.common.hw, 177 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 178 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 179 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 180 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 181 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 182 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 183 [CLK_IR] = &ir_clk.common.hw, 184 }, 185 .num = CLK_NUMBER, 186 }; 187 188 static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = { 189 .hws = { 190 [CLK_AR100] = &ar100_clk.common.hw, 191 [CLK_AHB0] = &ahb0_clk.hw, 192 [CLK_APB0] = &apb0_clk.common.hw, 193 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 194 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 195 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 196 [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw, 197 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 198 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 199 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 200 [CLK_IR] = &ir_clk.common.hw, 201 }, 202 .num = CLK_NUMBER, 203 }; 204 205 static struct ccu_reset_map sun8i_a83t_r_ccu_resets[] = { 206 [RST_APB0_IR] = { 0xb0, BIT(1) }, 207 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 208 [RST_APB0_RSB] = { 0xb0, BIT(3) }, 209 [RST_APB0_UART] = { 0xb0, BIT(4) }, 210 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 211 }; 212 213 static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = { 214 [RST_APB0_IR] = { 0xb0, BIT(1) }, 215 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 216 [RST_APB0_UART] = { 0xb0, BIT(4) }, 217 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 218 }; 219 220 static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = { 221 [RST_APB0_IR] = { 0xb0, BIT(1) }, 222 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 223 [RST_APB0_RSB] = { 0xb0, BIT(3) }, 224 [RST_APB0_UART] = { 0xb0, BIT(4) }, 225 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 226 }; 227 228 static const struct sunxi_ccu_desc sun8i_a83t_r_ccu_desc = { 229 .ccu_clks = sun8i_a83t_r_ccu_clks, 230 .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_r_ccu_clks), 231 232 .hw_clks = &sun8i_a83t_r_hw_clks, 233 234 .resets = sun8i_a83t_r_ccu_resets, 235 .num_resets = ARRAY_SIZE(sun8i_a83t_r_ccu_resets), 236 }; 237 238 static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = { 239 .ccu_clks = sun8i_h3_r_ccu_clks, 240 .num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks), 241 242 .hw_clks = &sun8i_h3_r_hw_clks, 243 244 .resets = sun8i_h3_r_ccu_resets, 245 .num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets), 246 }; 247 248 static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = { 249 .ccu_clks = sun50i_a64_r_ccu_clks, 250 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks), 251 252 .hw_clks = &sun50i_a64_r_hw_clks, 253 254 .resets = sun50i_a64_r_ccu_resets, 255 .num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets), 256 }; 257 258 static int sun8i_r_ccu_probe(struct platform_device *pdev) 259 { 260 const struct sunxi_ccu_desc *desc; 261 void __iomem *reg; 262 263 desc = of_device_get_match_data(&pdev->dev); 264 if (!desc) 265 return -EINVAL; 266 267 reg = devm_platform_ioremap_resource(pdev, 0); 268 if (IS_ERR(reg)) 269 return PTR_ERR(reg); 270 271 return devm_sunxi_ccu_probe(&pdev->dev, reg, desc); 272 } 273 274 static const struct of_device_id sun8i_r_ccu_ids[] = { 275 { 276 .compatible = "allwinner,sun8i-a83t-r-ccu", 277 .data = &sun8i_a83t_r_ccu_desc, 278 }, 279 { 280 .compatible = "allwinner,sun8i-h3-r-ccu", 281 .data = &sun8i_h3_r_ccu_desc, 282 }, 283 { 284 .compatible = "allwinner,sun50i-a64-r-ccu", 285 .data = &sun50i_a64_r_ccu_desc, 286 }, 287 { } 288 }; 289 290 static struct platform_driver sun8i_r_ccu_driver = { 291 .probe = sun8i_r_ccu_probe, 292 .driver = { 293 .name = "sun8i-r-ccu", 294 .suppress_bind_attrs = true, 295 .of_match_table = sun8i_r_ccu_ids, 296 }, 297 }; 298 module_platform_driver(sun8i_r_ccu_driver); 299 300 MODULE_IMPORT_NS(SUNXI_CCU); 301 MODULE_LICENSE("GPL"); 302